[PATCH] e1000e: Define E1000_SWSM_SMBI

Define yet another magic number. The definition was copied from: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/tree/drivers/net/ethernet/intel/e1000e/defines.h?h=v6.0.9#n374 Signed-off-by: Akihiko Odaki --- hw/net/e1000_regs.h | 7 +++ hw/net/e1000e_core.c | 2 +- 2

[PATCH 2/4] target/avr: implement small RAM/large RAM feature

translate.c functions use RAMPZ for RAM access. This register is also used for ROM reads. However, in MCUs with 64k RAM support RAMPZ is used for ROM only. Therefore when RAMPZ is set, addressing the RAM becomes incorrect in the emulator. This patch adds LARGE RAM feature which can be used in

[PATCH 1/4] target/avr: fix long address calculation

AVR ELPMX instruction (and some others) use three registers to form long 24-bit address from RAMPZ and two 8-bit registers. RAMPZ stores shifted 8 bits like ff to simplify address calculation. This patch fixes full address calculation in function gen_get_addr by changing the mess in offsets of

[PATCH 4/4] target/avr: fix interrupt processing

Interrupt bit vector has 64 bits, but interrupt vector is found with ctz32 function. This patch replaces it with ctz64. Signed-off-by: Pavel Dovgalyuk --- target/avr/helper.c |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/helper.c b/target/avr/helper.c

[PATCH 3/4] target/avr: fix avr features processing

Bit vector for features has 64 bits. This patch fixes bit shifts in avr_feature and set_avr_feature functions to be 64-bit too. Signed-off-by: Pavel Dovgalyuk --- target/avr/cpu.h |4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/target/avr/cpu.h b/target/avr/cpu.h

[PATCH 0/4] AVR target fixes

--- Pavel Dovgalyuk (4): target/avr: fix long address calculation target/avr: implement small RAM/large RAM feature target/avr: fix avr features processing target/avr: fix interrupt processing target/avr/cpu.h | 6 ++-- target/avr/helper.c| 4 +--

[PATCH] e1000e: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000e_core.c | 94

[PATCH] e1000: Mask registers when writing

When a register has effective bits fewer than their width, the old code inconsistently masked when writing or reading. Make the code consistent by always masking when writing, and remove some code duplication. Signed-off-by: Akihiko Odaki --- hw/net/e1000.c | 84

Re: [PATCH] gtk: disable GTK Clipboard with a new option 'gtk_clipboard'

I should make myself useful around here on occasion when items are within my skill set. But I already struggle to find time for that in the libvirt community :-). On 11/8/22 09:23, Claudio Fontana wrote: The GTK Clipboard implementation may cause guest hangs. Therefore implement a new

Re: Plugin Memory Callback Debugging

On Nov 15 22:36, Alex Bennée wrote: > > Aaron Lindsay writes: > > > Hello, > > > > I have been wrestling with what might be a bug in the plugin memory > > callbacks. The immediate error is that I hit the > > `g_assert_not_reached()` in the 'default:' case in > > qemu_plugin_vcpu_mem_cb,

Re: Plugin Memory Callback Debugging

Sorry, left off the very end of my timeline: On Nov 18 16:58, Aaron Lindsay wrote: > I have, so far, discovered the following timeline: > 1. My plugin receives a instruction execution callback for a load >instruction. At this time, cpu->plugin_mem_cbs points to the same >memory which will

Re: [PATCH v4 03/11] block-backend: replace bdrv_*_above with blk_*_above

Am 16.11.2022 um 13:22 hat Emanuele Giuseppe Esposito geschrieben: > Avoid mixing bdrv_* functions with blk_*, so create blk_* counterparts > for: > - bdrv_block_status_above > - bdrv_is_allocated_above > > Signed-off-by: Emanuele Giuseppe Esposito > --- > block/block-backend.c | 21

Re: [PATCH] target/arm: build smbios 19 table

On Fri, 18 Nov 2022 at 17:37, Mihai Carabas wrote: > > Use the base_memmap to build the SMBIOS 19 table which provides the address > mapping for a Physical Memory Array (from spec [1] chapter 7.20). > > This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5 > ("SMBIOS:

Re: [PATCH v4 02/11] nbd/server.c: add missing coroutine_fn annotations

Am 16.11.2022 um 13:22 hat Emanuele Giuseppe Esposito geschrieben: > These functions end up calling bdrv_*() implemented as generated_co_wrapper > functions. > In addition, they also happen to be always called in coroutine context, > meaning all callers are coroutine_fn. > This means that the

Re: [PATCH v4 01/11] block-copy: add missing coroutine_fn annotations

Am 16.11.2022 um 13:22 hat Emanuele Giuseppe Esposito geschrieben: > These functions end up calling bdrv_common_block_status_above(), a > generated_co_wrapper function. > In addition, they also happen to be always called in coroutine context, > meaning all callers are coroutine_fn. > This means

Re: [PATCH qemu.git v2 9/9] hw/timer/imx_epit: fix compare timer handling

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > - fix #1263 > - rework compare time handling > - The compare timer has to run even if CR.OCIEN is not set, > as SR.OCIF must be updated. > - The compare timer fires exactly once when the > compare value is less

Re: [PATCH] vhost: configure all host notifiers in a single MR transaction

On Fri, 18 Nov 2022 at 09:51, Longpeng(Mike) via wrote: > > From: Longpeng > > This allows the vhost device to batch the setup of all its host notifiers. > This significantly reduces the device starting time, e.g. the vhost-vDPA > generic device [1] start time reduce from 376ms to 9.1ms for a VM

Re: [PATCH for-8.0 1/7] qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD

On 11/18/22 05:38, Alex Bennée wrote: Richard Henderson writes: Create a wrapper for locking/unlocking the iothread lock. Signed-off-by: Richard Henderson --- Cc: Paolo Bonzini (maintainer:Main loop) --- include/qemu/main-loop.h | 29 + 1 file changed, 29

Re: [PATCH v5 7/9] target/riscv: add support for Zcmt extension

On 11/18/22 04:37, Weiwei Li wrote: Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 4 ++ target/riscv/cpu_bits.h |

[PATCH v2 07/15] block: Drain invidual nodes during reopen

bdrv_reopen() and friends use subtree drains as a lazy way of covering all the nodes they touch. Turns out that this lazy way is a lot more complicated than just draining the nodes individually, even not accounting for the additional complexity in the drain mechanism itself. Simplify the code by

[PATCH v2 00/15] block: Simplify drain

I'm aware that exactly nobody has been looking forward to a series with this title, but it has to be. The way drain works means that we need to poll in bdrv_replace_child_noperm() and that makes things rather messy with Emanuele's multiqueue work because you must not poll while you hold the graph

[PATCH v2 03/15] block: Revert .bdrv_drained_begin/end to non-coroutine_fn

Polling during bdrv_drained_end() can be problematic (and in the future, we may get cases for bdrv_drained_begin() where polling is forbidden, and we don't care about already in-flight requests, but just want to prevent new requests from arriving). The .bdrv_drained_begin/end callbacks running in

[PATCH v2 15/15] block: Remove poll parameter from bdrv_parent_drained_begin_single()

All callers of bdrv_parent_drained_begin_single() pass poll=false now, so we don't need the parameter any more. Signed-off-by: Kevin Wolf --- include/block/block-io.h | 5 ++--- block.c | 4 ++-- block/io.c | 8 ++-- 3 files changed, 6 insertions(+), 11

[PATCH v2 13/15] block: Drop out of coroutine in bdrv_do_drained_begin_quiesce()

The next patch adds a parent drain to bdrv_attach_child_common(), which shouldn't be, but is currently called from coroutines in some cases (e.g. .bdrv_co_create implementations generally open new nodes). Therefore, the assertion that we're not in a coroutine doesn't hold true any more. We could

[PATCH v2 02/15] test-bdrv-drain: Don't yield in .bdrv_co_drained_begin/end()

We want to change .bdrv_co_drained_begin/end() back to be non-coroutine callbacks, so in preparation, avoid yielding in their implementation. This does almost the same as the existing logic in bdrv_drain_invoke(), by creating and entering coroutines internally. However, since the test case is by

[PATCH v2 09/15] stream: Replace subtree drain with a single node drain

The subtree drain was introduced in commit b1e1af394d9 as a way to avoid graph changes between finding the base node and changing the block graph as necessary on completion of the image streaming job. The block graph could change between these two points because bdrv_set_backing_hd() first drains

[PATCH v2 08/15] block: Don't use subtree drains in bdrv_drop_intermediate()

Instead of using a subtree drain from the top node (which also drains child nodes of base that we're not even interested in), use a normal drain for base, which automatically drains all of the parents, too. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Hanna

[PATCH v2 11/15] block: Call drain callbacks only once

We only need to call both the BlockDriver's callback and the parent callbacks when going from undrained to drained or vice versa. A second drain section doesn't make a difference for the driver or the parent, they weren't supposed to send new requests before and after the second drain. One thing

[PATCH v2 06/15] block: Fix locking for bdrv_reopen_queue_child()

Callers don't agree whether bdrv_reopen_queue_child() should be called with the AioContext lock held or not. Standardise on holding the lock (as done by QMP blockdev-reopen and the replication block driver) and fix bdrv_reopen() to do the same. Signed-off-by: Kevin Wolf --- block.c | 7 +--

[PATCH v2 14/15] block: Don't poll in bdrv_replace_child_noperm()

In order to make sure that bdrv_replace_child_noperm() doesn't have to poll any more, get rid of the bdrv_parent_drained_begin_single() call. This is possible now because we can require that the parent is already drained through the child in question when the function is called and we don't call

[PATCH v2 05/15] block: Inline bdrv_drain_invoke()

bdrv_drain_invoke() has now two entirely separate cases that share no code any more and are selected depending on a bool parameter. Each case has only one caller. Just inline the function. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Stefan Hajnoczi

[PATCH v2 10/15] block: Remove subtree drains

Subtree drains are not used any more. Remove them. After this, BdrvChildClass.attach/detach() don't poll any more. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir Sementsov-Ogievskiy Reviewed-by: Hanna Reitz --- include/block/block-io.h | 18 +-- include/block/block_int-common.h |

[PATCH v2 12/15] block: Remove ignore_bds_parents parameter from drain_begin/end.

ignore_bds_parents is now ignored during drain_begin and drain_end, so we can just remove it there. It is still a valid optimisation for drain_all in bdrv_drained_poll(), so leave it around there. Signed-off-by: Kevin Wolf --- include/block/block-io.h | 3 +-- block.c | 2 +-

[PATCH v2 01/15] qed: Don't yield in bdrv_qed_co_drain_begin()

We want to change .bdrv_co_drained_begin() back to be a non-coroutine callback, so in preparation, avoid yielding in its implementation. Because we increase bs->in_flight and bdrv_drained_begin() polls, the behaviour is unchanged. Signed-off-by: Kevin Wolf Reviewed-by: Vladimir

[PATCH v2 04/15] block: Remove drained_end_counter

drained_end_counter is unused now, nobody changes its value any more. It can be removed. In cases where we had two almost identical functions that only differed in whether the caller passes drained_end_counter, or whether they would poll for a local drained_end_counter to reach 0, these become a

[PATCH] target/arm: build smbios 19 table

Use the base_memmap to build the SMBIOS 19 table which provides the address mapping for a Physical Memory Array (from spec [1] chapter 7.20). This was present on i386 from commit c97294ec1b9e36887e119589d456557d72ab37b5 ("SMBIOS: Build aggregate smbios tables and entry point"). [1]

Re: [PATCH] tests/avocado: configure acpi-bits to use avocado timeout

On Fri, Nov 18, 2022 at 1:33 PM Thomas Huth wrote: > > On 18/11/2022 05.05, Ani Sinha wrote: > > On Wed, Nov 16, 2022 at 8:54 AM Ani Sinha wrote: > >> > >> On Wed, Nov 16, 2022 at 2:58 AM John Snow wrote: > >>> > >>> Instead of using a hardcoded timeout, just rely on Avocado's built-in > >>>

Re: [PATCH qemu.git v2 7/9] hw/timer/imx_epit: factor out register write handlers

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > Signed-off-by: Axel Heider > --- > hw/timer/imx_epit.c | 211 > 1 file changed, 115 insertions(+), 96 deletions(-) Good idea (unfortunate that git diff has not shown the

Re: [PATCH v9 3/8] KVM: Add KVM_EXIT_MEMORY_FAULT exit

On Fri, Nov 18, 2022, Alex Bennée wrote: > > Chao Peng writes: > > > On Thu, Nov 17, 2022 at 03:08:17PM +, Alex Bennée wrote: > >> >> I think this should be explicit rather than implied by the absence of > >> >> another flag. Sean suggested you might want flags for RWX failures so > >> >>

Re: [PATCH qemu.git v2 8/9] hw/timer/imx_epit: change reset handling

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > - inline software reset > - make hardware reset invoke software reset > - simplify code flow I think this patch is fixing a bug, right? We weren't previously clearing CR for the hardware reset. If so, that's worth noting

Re: [PATCH qemu.git v2 6/9] hw/timer/imx_epit: remove explicit fields cnt and freq

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > The CNT register is a read-only register. There is no need to > store it's value, it can be calculated on demand. > The calculated frequency is needed temporarily only. This patch bumps the vmstate version ID for the

Re: [PATCH qemu.git v2 5/9] hw/timer/imx_epit: do not persist CR.SWR bit

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > Signed-off-by: Axel Heider > --- > hw/timer/imx_epit.c | 7 --- > 1 file changed, 4 insertions(+), 3 deletions(-) > > diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c > index 5315d9633e..6af460946f 100644 > ---

Re: [PATCH qemu.git v2 4/9] hw/timer/imx_epit: software reset clears the interrupt

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > Signed-off-by: Axel Heider > --- > hw/timer/imx_epit.c | 4 > 1 file changed, 4 insertions(+) > > diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c > index 2e9dae0bc8..5315d9633e 100644 > ---

Re: [PATCH qemu.git v2 3/9] hw/timer/imx_epit: simplify interrupt logic

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > Signed-off-by: Axel Heider > --- > hw/timer/imx_epit.c | 27 +++ > 1 file changed, 11 insertions(+), 16 deletions(-) > > diff --git a/hw/timer/imx_epit.c b/hw/timer/imx_epit.c > index

Re: [PATCH qemu.git v2 2/9] hw/timer/imx_epit: cleanup CR defines

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > remove unused defines, add needed defines > > Signed-off-by: Axel Heider Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH qemu.git v2 1/9] hw/timer/imx_epit: improve comments

On Mon, 7 Nov 2022 at 16:42, ~axelheider wrote: > > From: Axel Heider > > Fix typos, add background information > > Signed-off-by: Axel Heider > -- Reviewed-by: Peter Maydell thanks -- PMM

Re: [PATCH 00/15] Protect the block layer with a rwlock: part 3

On Fri, Nov 18, 2022 at 4:01 PM Emanuele Giuseppe Esposito wrote: > > - generated_co_wrapper_simple -> coroutine_wrapper > > - generated_co_wrapper_blk -> coroutine_wrapper_mixed > > - generated_co_wrapper -> coroutine_wrapper_mixed_bdrv > > > > ? It is not clear to me yet if you will have

Re: [PATCH v4 6/7] target/arm: Add PMSAv8r functionality

On Sun, 23 Oct 2022 at 16:37, wrote: > > From: Tobias Röhmel > > Add PMSAv8r translation. > > Signed-off-by: Tobias Röhmel > --- > target/arm/ptw.c | 130 +++ > 1 file changed, 110 insertions(+), 20 deletions(-) > > diff --git a/target/arm/ptw.c

Re: [PATCH v4 0/7] Add ARM Cortex-R52 CPU

On Sun, 23 Oct 2022 at 16:37, wrote: > > From: Tobias Röhmel > > Thanks again for all the help! > > Here is v4: > 2. Made patch cleaner > 3. Changed commit message > 4. Replaced V8_R flag with ARM_FEATURE_PMSA|ARM_FEATURE_V8 > 5. > Reworked the code to use existing pmsav7 variables > Added

Re: [PATCH 00/15] Protect the block layer with a rwlock: part 3

Am 18/11/2022 um 11:57 schrieb Paolo Bonzini: > On 11/16/22 15:07, Emanuele Giuseppe Esposito wrote: >> Here we introduce generated_co_wrapper_simple, a simplification of >> g_c_w that >> only considers the case where the caller is not in a coroutine. >> This simplifies and clarifies a lot when

Re: [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML

On Fri, 18 Nov 2022 14:08:36 +0100 Igor Mammedov wrote: > On Thu, 17 Nov 2022 22:51:46 +0100 > Volker Rümelin wrote: [...] > > since this patch SeaBIOS no longer detects the PS/2 keyboard. This means > > there's no keyboard in SeaBIOS, GRUB or FreeDOS. OVMF and Linux detect > > the PS/2

[PATCH] vhost: configure all host notifiers in a single MR transaction

From: Longpeng This allows the vhost device to batch the setup of all its host notifiers. This significantly reduces the device starting time, e.g. the vhost-vDPA generic device [1] start time reduce from 376ms to 9.1ms for a VM with 64 vCPUs and 3 vDPA device(64vq per device). [1]

Re: [PULL v4 30/83] virtio: core: vq reset feature negotation support

On Fri, Nov 18, 2022 at 3:32 PM Stefano Garzarella wrote: > > Hi, > starting from this commit 69e1c14aa2 ("virtio: core: vq reset feature > negotation support"), vhost-user-vsock and vhost-vsock fails while > setting the device features, because VIRTIO_F_RING_RESET is not masked. vhost-vsock

Re: [PULL v4 30/83] virtio: core: vq reset feature negotation support

Hi, starting from this commit 69e1c14aa2 ("virtio: core: vq reset feature negotation support"), vhost-user-vsock and vhost-vsock fails while setting the device features, because VIRTIO_F_RING_RESET is not masked. I'm not sure vsock is the only one affected. We could fix in two ways: 1)

Re: [RFC PATCH] tests/avocado: use new rootfs for orangepi test

On 18/11/2022 12.33, Alex Bennée wrote: The old URL wasn't stable. I suspect the current URL will only be stable for a few months so maybe we need another strategy for hosting rootfs snapshots? Looking at http://storage.kernelci.org/images/rootfs/buildroot/buildroot-baseline/ there are only

Re: [PATCH for-8.0] hw: Add compat machines for 8.0

On 18/11/2022 11.14, Cornelia Huck wrote: On Fri, Nov 18 2022, Thomas Huth wrote: On 11/11/2022 13.45, Cornelia Huck wrote: Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. Signed-off-by: Cornelia Huck --- ... diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index

Re: [PATCH v4 7/7] target/arm: Add ARM Cortex-R52 CPU

On Sun, 23 Oct 2022 at 16:37, wrote: > > From: Tobias Röhmel > > All constants are taken from the ARM Cortex-R52 Processor TRM Revision: r1p3 > > Signed-off-by: Tobias Röhmel > --- > target/arm/cpu_tcg.c | 42 ++ > 1 file changed, 42 insertions(+)

Re: [PATCH v4 5/7] target/arm: Add PMSAv8r registers

On Sun, 23 Oct 2022 at 16:37, wrote: > > From: Tobias Röhmel > > Signed-off-by: Tobias Röhmel This patch is basically the right shape, but there's a big simplification you can make and then a bunch of minor tweaks. > --- > target/arm/cpu.c | 26 +++- > target/arm/cpu.h | 12 ++ >

Re: [PATCH for-8.0 1/7] qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD

Richard Henderson writes: > Create a wrapper for locking/unlocking the iothread lock. > > Signed-off-by: Richard Henderson > --- > Cc: Paolo Bonzini (maintainer:Main loop) > --- > include/qemu/main-loop.h | 29 + > 1 file changed, 29 insertions(+) > > diff --git

Re: [PATCH v2 05/19] hw/9pfs: Update 9pfs to use the new QemuFd_t type

On Friday, November 18, 2022 10:29:51 AM CET Greg Kurz wrote: > On Fri, 11 Nov 2022 12:22:11 +0800 > Bin Meng wrote: > > > With this new QemuFd_t type, it significantly reduces the number of > > I cannot find the definition of this type, nor the definition of > qemu_fd_invalid(). Missing patch

Re: [PATCH for-8.0 1/7] qemu/main-loop: Introduce QEMU_IOTHREAD_LOCK_GUARD

Richard Henderson writes: > Create a wrapper for locking/unlocking the iothread lock. > > Signed-off-by: Richard Henderson > --- > Cc: Paolo Bonzini (maintainer:Main loop) You might want to review Paolo's comments from: Subject: [RFC PATCH] main-loop: introduce WITH_QEMU_IOTHREAD_LOCK

Re: [PATCH v9 3/8] KVM: Add KVM_EXIT_MEMORY_FAULT exit

Chao Peng writes: > On Thu, Nov 17, 2022 at 03:08:17PM +, Alex Bennée wrote: >> >> >> >> > + >> >> >> > +/* KVM_EXIT_MEMORY_FAULT */ >> >> >> > +struct { >> >> >> > + #define KVM_MEMORY_EXIT_FLAG_PRIVATE (1 << 0) >> >> >> > +__u32 flags;

Re: [PATCH v2 02/19] hw/9pfs: Drop unnecessary *xattr wrapper API declarations

On Friday, November 18, 2022 9:42:26 AM CET Greg Kurz wrote: > On Fri, 11 Nov 2022 12:22:08 +0800 > Bin Meng wrote: > > > These are not used anywhere in the source tree. Drop them. > > > > Signed-off-by: Bin Meng > > --- > > > > This one could even go through the trivial tree right > away

Re: [PULL v4 46/83] acpi: pc/q35: drop ad-hoc PCI-ISA bridge AML routines and let bus ennumeration generate AML

On Thu, 17 Nov 2022 22:51:46 +0100 Volker Rümelin wrote: > > From: Igor Mammedov > > > > PCI-ISA bridges that are built in PIIX/Q35 are building its own AML > > using AcpiDevAmlIf interface. Now build_append_pci_bus_devices() > > gained AcpiDevAmlIf interface support to get AML of devices

Re: [PATCH 1/2] remove DEC 21154 PCI bridge

On Wed, 16 Nov 2022 20:39:29 +0100 (CET) BALATON Zoltan wrote: > On Wed, 16 Nov 2022, Igor Mammedov wrote: > > > Code has not been used practically since its inception (2004) > > f2aa58c6f4a20 UniNorth PCI bridge support > > or maybe even earlier, but it was consuming contributors time > > as

[PATCH v5 6/9] target/riscv: add support for Zcmp extension

Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189 +- target/riscv/translate.c

[PATCH v5 8/9] target/riscv: expose properties for Zc* extension

Expose zca,zcb,zcf,zcd,zcmp,zcmt properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Alistair Francis --- target/riscv/cpu.c | 13 + 1 file changed, 13 insertions(+) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 1ab04ab246..b9e41df96c 100644

[PATCH v5 9/9] disas/riscv.c: add disasm support for Zc*

Zcmp/Zcmt instructions will override disasm for c.fld*/c.fsd* instructions currently Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- disas/riscv.c | 287 +- 1 file changed, 286 insertions(+), 1 deletion(-) diff --git a/disas/riscv.c

[PATCH v5 1/9] target/riscv: add cfg properties for Zc* extension

Add properties for Zca,Zcb,Zcf,Zcd,Zcmp,Zcmt extension Add check for these properties Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Cc: Alistair Francis Reviewed-by: Richard Henderson --- target/riscv/cpu.c | 43 +++ target/riscv/cpu.h | 6

[PATCH v5 5/9] target/riscv: add support for Zcb extension

Add encode and trans* functions support for Zcb instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode| 24 ++ target/riscv/insn_trans/trans_rvzce.c.inc | 100 ++

[PATCH v5 2/9] target/riscv: add support for Zca extension

Modify the check for C extension to Zca (C implies Zca) Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn_trans/trans_rvi.c.inc | 4 ++-- target/riscv/translate.c| 8 ++-- 2 files changed, 8 insertions(+), 4

[PATCH v5 7/9] target/riscv: add support for Zcmt extension

Add encode, trans* functions and helper functions support for Zcmt instrutions Add support for jvt csr Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/cpu.h| 4 ++ target/riscv/cpu_bits.h | 7 +++ target/riscv/csr.c

[PATCH v5 0/9] support subsets of code size reduction extension

This patchset implements RISC-V Zc* extension v1.0.0.RC5.7 version instructions. Specification: https://github.com/riscv/riscv-code-size-reduction/tree/main/Zc-specification The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zce-upstream-v5 To test Zc* implementation,

[PATCH v5 3/9] target/riscv: add support for Zcf extension

Separate c_flw/c_fsw from flw/fsw to add check for Zcf extension Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8 target/riscv/insn_trans/trans_rvf.c.inc | 18 ++ 2 files changed, 22

[PATCH v5 4/9] target/riscv: add support for Zcd extension

Separate c_fld/c_fsd from fld/fsd to add additional check for c.fld{sp}/c.fsd{sp} which is useful for zcmp/zcmt to reuse their encodings Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang Reviewed-by: Richard Henderson --- target/riscv/insn16.decode | 8

Re: [PATCH v4 7/9] target/riscv: add support for Zcmt extension

On 2022/11/18 18:24, Richard Henderson wrote: On 11/17/22 23:17, Weiwei Li wrote: +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index, + target_ulong next_pc) +{ + +#if !defined(CONFIG_USER_ONLY) +    RISCVException ret = smstateen_acc_ok(env, 0,

[RFC PATCH] tests/avocado: use new rootfs for orangepi test

The old URL wasn't stable. I suspect the current URL will only be stable for a few months so maybe we need another strategy for hosting rootfs snapshots? Signed-off-by: Alex Bennée --- tests/avocado/boot_linux_console.py | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git

Re: [PATCH 00/15] Protect the block layer with a rwlock: part 3

On 11/16/22 15:07, Emanuele Giuseppe Esposito wrote: Here we introduce generated_co_wrapper_simple, a simplification of g_c_w that only considers the case where the caller is not in a coroutine. This simplifies and clarifies a lot when the caller is a coroutine or not, and in the future will

Re: [PATCH for-8.0 4/7] target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittb

On 11/18/22 02:13, Daniel Henrique Barboza wrote: On 11/18/22 06:18, Richard Henderson wrote: In addition, use tcg_enabled instead of !kvm_enabled. Signed-off-by: Richard Henderson --- Should we strive for this change (tcg_enabled instead of !kvm_enabled) everywhere when applicable?

Re: [PATCH v4 7/9] target/riscv: add support for Zcmt extension

On 11/17/22 23:17, Weiwei Li wrote: +target_ulong HELPER(cm_jalt)(CPURISCVState *env, target_ulong index, + target_ulong next_pc) +{ + +#if !defined(CONFIG_USER_ONLY) +RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT); +if (ret != RISCV_EXCP_NONE)

Re: [PATCH for-8.0] hw: Add compat machines for 8.0

On Fri, Nov 18 2022, Thomas Huth wrote: > On 11/11/2022 13.45, Cornelia Huck wrote: >> Add 8.0 machine types for arm/i440fx/m68k/q35/s390x/spapr. >> >> Signed-off-by: Cornelia Huck >> --- > ... >> diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c >> index 0ad0ed160387..1c0a7b83b545 100644 >>

Re: [PATCH for-8.0 6/7] hw/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_set_irq

On 11/18/22 06:18, Richard Henderson wrote: Signed-off-by: Richard Henderson --- Cc: qemu-...@nongnu.org --- Reviewed-by: Daniel Henrique Barboza hw/ppc/ppc.c | 10 +- 1 file changed, 1 insertion(+), 9 deletions(-) diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index

Re: [PATCH for-8.0 4/7] target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in cpu_interrupt_exittb

On 11/18/22 06:18, Richard Henderson wrote: In addition, use tcg_enabled instead of !kvm_enabled. Signed-off-by: Richard Henderson --- Should we strive for this change (tcg_enabled instead of !kvm_enabled) everywhere when applicable? There's a lot of places in the ppc code where this can

Re: [PATCH for-8.0 3/7] target/ppc: Use QEMU_IOTHREAD_LOCK_GUARD in ppc_maybe_interrupt

On 11/18/22 06:18, Richard Henderson wrote: Signed-off-by: Richard Henderson --- Cc: qemu-...@nongnu.org --- Reviewed-by: Daniel Henrique Barboza target/ppc/excp_helper.c | 11 +-- 1 file changed, 1 insertion(+), 10 deletions(-) diff --git a/target/ppc/excp_helper.c

Re: [PATCH v4 6/9] target/riscv: add support for Zcmp extension

On 11/17/22 23:17, Weiwei Li wrote: Add encode, trans* functions for Zcmp instructions Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang --- target/riscv/insn16.decode| 18 +++ target/riscv/insn_trans/trans_rvzce.c.inc | 189 +-

[PATCH for-8.0 26/29] tcg/i386: Examine MemOp for atomicity and alignment

No change to the ultimate load/store routines yet, so some atomicity conditions not yet honored, but plumbs the change to alignment through the adjacent functions. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 128 ++ 1 file changed, 101

[PATCH for-8.0 27/29] tcg/i386: Support 128-bit load/store with have_atomic16

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.h | 3 +- tcg/i386/tcg-target.c.inc | 325 +++--- 2 files changed, 304 insertions(+), 24 deletions(-) diff --git a/tcg/i386/tcg-target.h b/tcg/i386/tcg-target.h index 53d2cb3412..7aafd60d72 100644 ---

[PATCH for-8.0 06/29] accel/tcg: Reorg system mode store helpers

Instead of trying to unify all operations on uint64_t, use mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 399 - 1 file changed,

[PATCH for-8.0 03/29] accel/tcg: Add cpu_in_serial_context

Like cpu_in_exclusive_context, but also true if there is no other cpu against which we could race. Use it in tb_flush as a direct replacement. Use it in cpu_loop_exit_atomic to ensure that there is no loop against cpu_exec_step_atomic. Signed-off-by: Richard Henderson --- accel/tcg/internal.h

[PATCH for-8.0 22/29] tcg/i386: Introduce tcg_out_testi

Split out a helper for choosing testb vs testl. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index 79568a3981..5ddbbbaf18

Re: [PATCH v3 2/3] KVM: keep track of running ioctls

Am 17/11/2022 um 20:27 schrieb David Hildenbrand: > On 11.11.22 16:47, Emanuele Giuseppe Esposito wrote: >> Using the new accel-blocker API, mark where ioctls are being called >> in KVM. Next, we will implement the critical section that will take >> care of performing memslots modifications

[PATCH for-8.0 18/29] accel/tcg: Add aarch64 specific support in ldst_atomicity

We have code in atomic128.h noting that through GCC 8, there was no support for atomic operations on __uint128. This has been fixed in GCC 10. But we can still improve over any basic compare-and-swap loop using the ldxp/stxp instructions. Add fast paths for FEAT_LSE2, using the detection in

[PATCH for-8.0 21/29] tcg/i386: Introduce tcg_out_mov2

Create a helper for data movement minding register overlap. Use the more general xchg instruction, which consumes one extra byte, but simplifies the more general function. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 27 +-- 1 file changed, 21

[PATCH for-8.0 28/29] tcg/i386: Add vex_v argument to tcg_out_vex_modrm_pool

Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 16 1 file changed, 8 insertions(+), 8 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index f277085321..3f0cb4bc66 100644 --- a/tcg/i386/tcg-target.c.inc +++

[PATCH for-8.0 20/29] tcg: Add INDEX_op_qemu_{ld,st}_i128

Add opcodes for backend support for 128-bit memory operations. Signed-off-by: Richard Henderson --- include/tcg/tcg-opc.h| 8 + tcg/aarch64/tcg-target.h | 2 ++ tcg/arm/tcg-target.h | 2 ++ tcg/i386/tcg-target.h| 2 ++ tcg/loongarch64/tcg-target.h | 2 ++

[PATCH for-8.0 05/29] accel/tcg: Reorg system mode load helpers

Instead of trying to unify all operations on uint64_t, pull out mmu_lookup() to perform the basic tlb hit and resolution. Create individual functions to handle access by size. Signed-off-by: Richard Henderson --- accel/tcg/cputlb.c | 606 ++--- 1 file

[PATCH for-8.0 14/29] tcg/i386: Add have_atomic16

Notice when Intel has guaranteed that vmovdqa is atomic. The new variable will also be used in generated code. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 18 ++ tcg/i386/tcg-target.h | 1 + tcg/i386/tcg-target.c.inc | 27 +++ 3

[PATCH for-8.0 04/29] accel/tcg: Introduce tlb_read_idx

Instead of playing with offsetof in various places, use MMUAccessType to index an array. This is easily defined instead of the previous dummy padding array in the union. Signed-off-by: Richard Henderson --- include/exec/cpu-defs.h | 7 ++- include/exec/cpu_ldst.h | 26 --

[PATCH for-8.0 01/29] include/qemu/cpuid: Introduce xgetbv_low

Replace the two uses of asm to expand xgetbv with an inline function. Since one of the two has been using the mnemonic, assume that the comment about "older versions of the assember" is obsolete, as even that is 4 years old. Signed-off-by: Richard Henderson --- include/qemu/cpuid.h | 7

[PATCH for-8.0 11/29] accel/tcg: Implement helper_{ld, st}*_mmu for user-only

TCG backends may need to defer to a helper to implement the atomicity required by a given operation. Mirror the interface used in system mode. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 6 +- accel/tcg/user-exec.c | 392 - 2 files

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