On 28/12/22 22:09, Helge Deller wrote:
The sparc and hppa architectures provide an own output for the emulated
/proc/cpuinfo file.
Some userspace applications count (even if that's not the recommended
way) the number of lines which start with "processor:" and assume that
this number then
On December 28, 2022 6:31:07 PM PST, "Jason A. Donenfeld"
wrote:
>Hi,
>
>Read this message in a fixed width text editor with a lot of columns.
>
>On Wed, Dec 28, 2022 at 03:58:12PM -0800, H. Peter Anvin wrote:
>> Glad you asked.
>>
>> So the kernel load addresses are parameterized in the kernel
On December 28, 2022 6:31:07 PM PST, "Jason A. Donenfeld"
wrote:
>Hi,
>
>Read this message in a fixed width text editor with a lot of columns.
>
>On Wed, Dec 28, 2022 at 03:58:12PM -0800, H. Peter Anvin wrote:
>> Glad you asked.
>>
>> So the kernel load addresses are parameterized in the kernel
On 29/12/22 03:31, Jason A. Donenfeld wrote:
Hi,
Read this message in a fixed width text editor with a lot of columns.
On Wed, Dec 28, 2022 at 03:58:12PM -0800, H. Peter Anvin wrote:
Glad you asked.
So the kernel load addresses are parameterized in the kernel image
setup header. One of the
From: Yicong Yang
Currently we'll always generate a cluster node no matter user has
specified '-smp clusters=X' or not. Cluster is an optional level
and will participant the building of Linux scheduling domains and
only appears on a few platforms. It's unncessary to always build
it when it
From: Yicong Yang
Update the ACPI tables according to the acpi aml_build change, also
empty bios-tables-test-allowed-diff.h.
The disassembled differences between actual and expected PPTT:
/*
* Intel ACPI Component Architecture
* AML/ASL+ Disassembler version 20180105 (64-bit version)
From: Yicong Yang
Add *.topology tables for the aarch64's topology test and empty
bios-tables-test-allowed-diff.h
The disassembled differences between actual and expected
PPTT (the table which we actually care about):
+/*
+ * Intel ACPI Component Architecture
+ * AML/ASL+ Disassembler
From: Yicong Yang
Allow changes to test/data/acpi/virt/PPTT*, prepare to change the
building policy of the cluster topology.
Reviewed-by: Yanan Wang
Signed-off-by: Yicong Yang
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git
From: Yicong Yang
Add and whitelist *.topology blobs, prepares for the aarch64's ACPI
topology building test.
Reviewed-by: Yanan Wang
Signed-off-by: Yicong Yang
---
tests/data/acpi/virt/APIC.topology | 0
tests/data/acpi/virt/DSDT.topology | 0
From: Yicong Yang
Add test for aarch64's ACPI topology building for all the supported
levels.
Acked-by: Michael S. Tsirkin
Reviewed-by: Yanan Wang
Tested-by: Yanan Wang
Signed-off-by: Yicong Yang
---
tests/qtest/bios-tables-test.c | 19 +++
1 file changed, 19 insertions(+)
From: Yicong Yang
This series mainly change the policy for building a cluster topology node
in PPTT. Previously we'll always build a cluster node in PPTT without
asking the user, after this set the cluster node will be built only the
the user specify through "-smp clusters=X".
One problem is
> -Original Message-
> From: Christian Schoenebeck
> Sent: Wednesday, December 28, 2022 19:51
> To: Greg Kurz ; qemu-devel@nongnu.org
> Cc: Meng, Bin ; Shi, Guohuai
>
> Subject: Re: [PATCH v3 07/17] hw/9pfs: Support getting current directory
> offset for Windows
>
> CAUTION: This
在 2022/12/28 21:12, Philippe Mathieu-Daudé 写道:
On 27/12/22 18:54, Michael S. Tsirkin wrote:
On Tue, Dec 27, 2022 at 05:43:57PM +0100, Philippe Mathieu-Daudé wrote:
On 27/12/22 08:20, Longpeng(Mike) wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host
Alex,
Sorry for being late.
Yes, I'm an individual contributor (I'm working at TRASIO, a Japanese
government-funded research project using RISC-V [and the corporation
built for it] but all my QEMU contributions are not a part of TRASIO's
work).
Thanks,
Tsukasa
On 2022/12/19 21:19, Alex Bennée
I test cxl with the patch:[v11,0/2] arm/virt: CXL support via pxb_cxl.
https://patchwork.kernel.org/project/cxl/cover/20220616141950.23374-1-jonathan.came...@huawei.com/
But the qemu crashed,and showing an error:
qemu-system-aarch64: ../hw/arm/virt.c:1735: virt_get_high_memmap_enabled:
Assertion
在 2022/12/29 上午11:13, Richard Henderson 写道:
On 12/28/22 17:51, gaosong wrote:
A related question though: does the manual mention whether the fpu
instructions only modify the lower 64 bits, or do the high 64-bits
become zeroed, nanboxed, or unspecified?
Only modify the lower 64bits, the
On 12/28/22 17:51, gaosong wrote:
A related question though: does the manual mention whether the fpu instructions only
modify the lower 64 bits, or do the high 64-bits become zeroed, nanboxed, or unspecified?
Only modify the lower 64bits, the high 64-bits is unpecified.
These two options
On 2022/12/23 12:23, Jason Wang wrote:
On Thu, Dec 22, 2022 at 7:43 PM Sriram Yagnaraman
wrote:
A new attempt at adding support for Intel 82576 Gigabit Ethernet adapter
with SR-IOV support.
Start qemu with the following parameters.
qemu-system-x86_64 -enable-kvm -M q35 \
...
Hi,
Read this message in a fixed width text editor with a lot of columns.
On Wed, Dec 28, 2022 at 03:58:12PM -0800, H. Peter Anvin wrote:
> Glad you asked.
>
> So the kernel load addresses are parameterized in the kernel image
> setup header. One of the things that are so parameterized are the
On 12/28/22 15:58, H. Peter Anvin wrote:
On December 28, 2022 8:57:54 AM PST, "Jason A. Donenfeld"
wrote:
HELLO H. PETER ANVIN,
E
L
L
O
On Wed, Dec 28, 2022 at 05:30:30PM +0100, Jason A. Donenfeld wrote:
Fix looks good, glad you figured out the problem.
I mean, kind of. The solution here
在 2022/12/29 上午1:30, Richard Henderson 写道:
On 12/27/22 18:34, gaosong wrote:
The manual says "The lower 64 bits of each vector register overlap
with the floating point register of the same number. In other words
When the basic floating-point instruction is executed to update the
On December 28, 2022 8:57:54 AM PST, "Jason A. Donenfeld"
wrote:
>HELLO H. PETER ANVIN,
>E
>L
>L
>O
>
>On Wed, Dec 28, 2022 at 05:30:30PM +0100, Jason A. Donenfeld wrote:
>> > Fix looks good, glad you figured out the problem.
>>
>> I mean, kind of. The solution here sucks, especially given that
Hi Keith,
Thank you for the review and I agree with you, the issues will be addressed.
Regards,
Michael
-Original Message-
From: Keith Busch
Sent: Wednesday, December 28, 2022 12:10 PM
To: Jonathan Derrick
Cc: qemu-devel@nongnu.org; Michael Kropaczek (CW)
; qemu-bl...@nongnu.org;
We create a new generator that creates an analyze_ function for
each instruction. Currently, these functions record the writes to
R, P, and C registers by calling ctx_log_reg_write[_pair] or
ctx_log_pred_write.
During gen_start_packet, we invoke the analyze_ function for
each instruction in the
Add overrides for
SL2_jumpr31Unconditional
SL2_jumpr31_t Predicated true (old value)
SL2_jumpr31_f Predicated false (old value)
SL2_jumpr31_tnew Predicated true (new value)
SL2_jumpr31_fnew Predicated false (new value)
Signed-off-by:
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 4 ++
target/hexagon/genptr.c | 79
2 files changed, 83 insertions(+)
diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h
index 231654e6c1..1ac23b75a0 100644
---
Analyze HVX vector and predicate registers
Signed-off-by: Taylor Simpson
---
target/hexagon/translate.h | 14 --
target/hexagon/translate.c | 28
target/hexagon/gen_analyze_funcs.py | 17 ++---
The idef-parser skips the change-of-flow (COF) instructions, so add
overrides
Changes in v2
Add a new generator for analyze_ instructions. Pouplate the
DisasContext ahead of generating code.
Taylor Simpson (6):
Hexagon (target/hexagon) Add overrides for jumpr31 instructions
These instructions perform a deallocframe+return (jumpr r31)
Add overrides for
L4_return
SL2_return
L4_return_t
L4_return_f
L4_return_tnew_pt
L4_return_fnew_pt
L4_return_tnew_pnt
L4_return_fnew_pnt
SL2_return_t
SL2_return_f
SL2_return_tnew
Add overrides for
J2_callr
J2_callrt
J2_callrf
Signed-off-by: Taylor Simpson
---
target/hexagon/gen_tcg.h | 6 ++
target/hexagon/macros.h | 10 --
target/hexagon/genptr.c | 20
3 files changed, 26 insertions(+), 10 deletions(-)
diff --git
The sparc and hppa architectures provide an own output for the emulated
/proc/cpuinfo file.
Some userspace applications count (even if that's not the recommended
way) the number of lines which start with "processor:" and assume that
this number then reflects the number of online CPUs. Since those
On 12/13/22 22:26, Helge Deller wrote:
The sparc and hppa architectures provide an own output for the emulated
/proc/cpuinfo file.
Some userspace applications count (even if that's not the recommended
way) the number of lines which start with "processor:" and assume that
this number then
On Mon, Dec 26, 2022 at 11:03 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> Cubieboard now can boot directly from SD card, without the need to pass
> `-kernel` parameter. Update Avocado tests to cover this functionality.
>
> Signed-off-by: Strahinja Jankovic
>
Test looks fine
On Mon, Dec 26, 2022 at 11:03 PM Strahinja Jankovic <
strahinjapjanko...@gmail.com> wrote:
> This patch implements Allwinner TWI/I2C controller emulation. Only
> master-mode functionality is implemented.
>
> The SPL boot for Cubieboard expects AXP209 PMIC on TWI0/I2C0 bus, so this
> is
> first
On 28/12/22 16:35, Philippe Mathieu-Daudé wrote:
Various syscalls miss swapping the endiannes of the [res]uid/gid
values. Use the tswapid() helper meant to do exactly that.
Fixes: b03c60f351 ("more syscalls")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1394
This is not the correct
On 12/28/22 12:18, Bin Meng wrote:
On Wed, Dec 28, 2022 at 9:38 PM Daniel Henrique Barboza
wrote:
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit
On Wed, Dec 28, 2022 at 01:41:40PM -0600, Jonathan Derrick wrote:
> +static uint16_t nvme_ns_mgmt(NvmeCtrl *n, NvmeRequest *req)
> +{
> +NvmeCtrl *n_p = NULL; /* primary controller */
> +NvmeIdCtrl *id = >id_ctrl;
> +NvmeNamespace *ns;
> +NvmeIdNsMgmt id_ns = {};
> +uint8_t
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
create namespaces by issuing nvme create-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during
From: Michael Kropaczek
Description:
Currently namespaces could be configured as follows:
1. Legacy Namespace - just one namespace within Nvme controller's
where the back-end was specified for nvme device by -drive parameter
pointing directly to the image file.
2. Additional Namespaces -
From: Michael Kropaczek
Added support for NVMEe NameSpaces Mangement allowing the guest OS to
delete namespaces by issuing nvme delete-ns command.
It is an extension to currently implemented Qemu nvme virtual device.
Virtual devices representing namespaces will be created and/or deleted
during
On 19/12/2022 12.21, Marcel Apfelbaum wrote:
On Mon, Dec 19, 2022 at 10:57 AM Yuval Shaia wrote:
Can anyone else pick this one?
Adding Thomas,
I dropped the ball with this one, I am sorry about that, maybe it
doesn't worth a Pull Request only for it.
Why not? Pull request for single
On 12/28/22 12:51, Philippe Mathieu-Daudé wrote:
On 28/12/22 14:33, Daniel Henrique Barboza wrote:
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
On 28/12/22 19:30, Richard Henderson wrote:
On 12/28/22 10:27, Philippe Mathieu-Daudé wrote:
Oh, so you are using this variable as tri-state?
Yes. Perhaps a comment on the -1?
Or name the variable tristate_lock? And a comment :)
(No need to respin, you can keep my R-b).
On 28/12/22 17:26, Mark Burton wrote:
Is there any chance between 7.1 and 7.2 ‘something’ happened to make it
so that Qemu ‘cares more’ about e.g. when memory regions are added/removed?
I seem to get an abort because a memory region has not been completely
setup in 7.2 (while it is being
On 12/28/22 10:27, Philippe Mathieu-Daudé wrote:
Oh, so you are using this variable as tri-state?
Yes. Perhaps a comment on the -1?
r~
On 28/12/22 18:36, Richard Henderson wrote:
On 12/27/22 23:24, Philippe Mathieu-Daudé wrote:
On 24/12/22 16:18, Richard Henderson wrote:
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c |
> -Original Message-
> From: Mukilan Thiyagarajan (QUIC)
> Sent: Tuesday, December 27, 2022 9:35 AM
> To: qemu-devel@nongnu.org; Taylor Simpson ;
> laur...@vivier.eu
> Cc: Brian Cain ; richard.hender...@linaro.org;
> alex.ben...@linaro.org; Mukilan Thiyagarajan (QUIC)
>
> Subject:
> -Original Message-
> From: Mukilan Thiyagarajan (QUIC)
> Sent: Tuesday, December 27, 2022 9:35 AM
> To: qemu-devel@nongnu.org; Taylor Simpson ;
> laur...@vivier.eu
> Cc: Brian Cain ; richard.hender...@linaro.org;
> alex.ben...@linaro.org; Mukilan Thiyagarajan (QUIC)
>
> Subject:
> -Original Message-
> From: Mukilan Thiyagarajan (QUIC)
> Sent: Wednesday, December 28, 2022 9:37 AM
> To: qemu-devel@nongnu.org; Taylor Simpson
> Cc: Brian Cain ; Matheus Bernardino (QUIC)
> ; Mukilan Thiyagarajan (QUIC)
>
> Subject: [PATCH] tests/tcg/hexagon: fix underspecifed asm
On 12/27/22 23:24, Philippe Mathieu-Daudé wrote:
On 24/12/22 16:18, Richard Henderson wrote:
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 39 ---
On 12/27/22 18:34, gaosong wrote:
The manual says "The lower 64 bits of each vector register overlap with the floating point
register of the same number. In other words
When the basic floating-point instruction is executed to update the floating-point
register, the low 64 bits of the
HELLO H. PETER ANVIN,
E
L
L
O
On Wed, Dec 28, 2022 at 05:30:30PM +0100, Jason A. Donenfeld wrote:
> > Fix looks good, glad you figured out the problem.
>
> I mean, kind of. The solution here sucks, especially given that in the
> worst case, setup_data just gets dropped. I'm half inclined to
Hi, it's a good idea to update the skeleton generation. Technically
skeleton generation is not a part of Qemu building. The skeleton is
already presented in the Qemu tree, so we skip dependencies from
clang/bpftool.
It's a good idea to have an updated bpf program and simplified
Makefile with Qemu
On Wed, Dec 28, 2022 at 05:02:22PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Jason,
>
> On 28/12/22 15:38, Jason A. Donenfeld wrote:
> > The setup_data links are appended to the compressed kernel image. Since
> > the kernel image is typically loaded at 0x10, setup_data lives at
> > `0x10
Is there any chance between 7.1 and 7.2 ‘something’ happened to make it so that
Qemu ‘cares more’ about e.g. when memory regions are added/removed?
I seem to get an abort because a memory region has not been completely setup in
7.2 (while it is being flattened actually) - In 7.1 that never
Hello everyone, this is a proposal in the libtcg direction, i.e.,
enabling building a single QEMU executable featuring multiple *targets*
(i.e., TCG frontends).
This follows what we discussed in recent KVM calls and originally at
the KVM Forum Emulation BoF.
Note that our commitment to this
Hi Jason,
On 28/12/22 15:38, Jason A. Donenfeld wrote:
The setup_data links are appended to the compressed kernel image. Since
the kernel image is typically loaded at 0x10, setup_data lives at
`0x10 + compressed_size`, which does not get relocated during the
kernel's boot process.
The
On 28/12/22 14:33, Daniel Henrique Barboza wrote:
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline in the fdt
Let's fold everything inside riscv_load_kernel() to avoid
On 28/12/22 14:33, Daniel Henrique Barboza wrote:
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
There are two test cases where the inline asm doesn't
have the correct constraints causing them to fail when
using certain clang versions/optimization levels.
In mem_noshuf.c, the register r7 is written to but
not specified in the clobber list.
In misc.c, the 'result' output needs the early
Various syscalls miss swapping the endiannes of the [res]uid/gid
values. Use the tswapid() helper meant to do exactly that.
Fixes: b03c60f351 ("more syscalls")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1394
Signed-off-by: Philippe Mathieu-Daudé
---
linux-user/syscall.c | 55
On Wed, Dec 28, 2022 at 9:38 PM Daniel Henrique Barboza
wrote:
>
> This test is used to do a quick sanity check to ensure that we're able
> to run the existing QEMU FW image.
>
> 'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
> 'virt' 32 bit machines are able to run the
On Wed, Dec 28, 2022 at 04:07:13AM +0100, Jason A. Donenfeld wrote:
> On Tue, Dec 27, 2022 at 02:36:54PM +0100, Jason A. Donenfeld wrote:
> > On Mon, Dec 26, 2022 at 05:57:30PM +0100, Jason A. Donenfeld wrote:
> > > On Mon, Dec 26, 2022 at 03:43:04PM +0100, Jason A. Donenfeld wrote:
> > > > On
The setup_data links are appended to the compressed kernel image. Since
the kernel image is typically loaded at 0x10, setup_data lives at
`0x10 + compressed_size`, which does not get relocated during the
kernel's boot process.
The kernel typically decompresses the image starting at
From: Dongxue Zhang
Should be cpu->cfg.elen in range [8, 64].
Signed-off-by: Dongxue Zhang
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fe176e483..5dc51f7912 100644
--- a/target/riscv/cpu.c
+++
From: Dongxue Zhang
Should be cpu->cfg.elen in range [8, 64].
Signed-off-by: Dongxue Zhang
---
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 6fe176e483..5dc51f7912 100644
--- a/target/riscv/cpu.c
+++
On Wed, 28 Dec 2022 at 15:06, David Hildenbrand wrote:
> On 28.12.22 15:05, Philippe Mathieu-Daudé wrote:
> > On 27/10/21 14:45, David Hildenbrand wrote:
> >> It's "virtio", not "virito".
> >>
> >> Signed-off-by: David Hildenbrand
> >> ---
> >>hw/virtio/virtio-mem.c | 12 ++--
> >>
On 27/10/21 14:45, David Hildenbrand wrote:
It's "virtio", not "virito".
Signed-off-by: David Hildenbrand
---
hw/virtio/virtio-mem.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
diff --git a/hw/virtio/virtio-mem.c
On 28.12.22 15:05, Philippe Mathieu-Daudé wrote:
On 27/10/21 14:45, David Hildenbrand wrote:
It's "virtio", not "virito".
Signed-off-by: David Hildenbrand
---
hw/virtio/virtio-mem.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 28.12.22 10:03, Chenyi Qiang wrote:
It should be the variable rdl2 to revert the already-notified listeners.
Fixes: 2044969f0b ("virtio-mem: Implement RamDiscardManager interface")
Signed-off-by: Chenyi Qiang
---
hw/virtio/virtio-mem.c | 2 +-
1 file changed, 1 insertion(+), 1
On 28.12.22 14:09, Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/virtio-mem.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c
index d96bde1fab..c252027391 100644
---
On Monday, December 26, 2022 4:08:37 PM CET Volker Rümelin wrote:
> Am 21.12.22 um 12:03 schrieb Christian Schoenebeck:
> > On Sunday, December 18, 2022 6:15:38 PM CET Volker Rümelin wrote:
> >> The currently used default playback settings in the ALSA audio
> >> backend are a bit unfortunate. With
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Hi,
This new version is still rebased on top of [1]:
"[PATCH 00/12] hw/riscv: Improve Spike HTIF emulation fidelity"
from Bin Meng. All the changes made were proposed by Phil in
the v2 review.
* Patches without reviews: 1, 9
Changes from v2:
- patch 1:
- reduced code repetition with a
The only remaining caller is riscv_load_kernel_and_initrd() which
belongs to the same file.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c | 76 -
include/hw/riscv/boot.h | 1
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c| 6 --
This will make the code more in line with what the other boards are
doing. We'll also avoid an extra check to machine->kernel_filename since
we already checked that before executing riscv_load_kernel().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by:
All callers are using kernel_filename as machine->kernel_filename.
This will also simplify the changes in riscv_load_kernel() that we're
going to do next.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline in the fdt
Let's fold everything inside riscv_load_kernel() to avoid code
repetition. Every other board that uses
The sifive_u, spike and virt machines are writing the 'bootargs' FDT
node during their respective create_fdt().
Given that bootargs is written only when '-append' is used, and this
option is only allowed with the '-kernel' option, which in turn is
already being check before executing
riscv_load_initrd() returns the initrd end addr while also writing a
'start' var to mark the addr start. These informations are being used
just to write the initrd FDT node. Every existing caller of
riscv_load_initrd() is writing the FDT in the same manner.
We can simplify things by writing the
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SpikeState and use MachineState::fdt
instead.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe
On 27/12/22 18:56, Michael S. Tsirkin wrote:
On Tue, Dec 27, 2022 at 05:51:47PM +0100, Philippe Mathieu-Daudé wrote:
On 27/12/22 08:20, Longpeng(Mike) wrote:
From: Longpeng
This allows the vhost-vdpa device to batch the setup of all its MRs of
host notifiers.
This significantly reduces the
On 27/12/22 18:54, Michael S. Tsirkin wrote:
On Tue, Dec 27, 2022 at 05:43:57PM +0100, Philippe Mathieu-Daudé wrote:
On 27/12/22 08:20, Longpeng(Mike) wrote:
From: Longpeng
This allows the vhost device to batch the setup of all its host notifiers.
This significantly reduces the device
Signed-off-by: Philippe Mathieu-Daudé
---
hw/virtio/virtio-mem.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c
index d96bde1fab..c252027391 100644
--- a/hw/virtio/virtio-mem.c
+++ b/hw/virtio/virtio-mem.c
@@
When requesting the flatview output with 'info mtree -f',
the MemoryRegion priority is irrelevant and noise. Remove it.
Signed-off-by: Philippe Mathieu-Daudé
---
softmmu/memory.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/softmmu/memory.c b/softmmu/memory.c
index
On 12/28/22 09:59, Philippe Mathieu-Daudé wrote:
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit
On 12/28/22 09:56, Philippe Mathieu-Daudé wrote:
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
On 28/12/22 13:49, Philippe Mathieu-Daudé wrote:
When called from syscall(), we are not within a TB and pc == 0.
We can skip the check for invalidating the current TB.
Signed-off-by: Richard Henderson
[PMD: Split patch in 2]
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-maint.c |
On 28/12/22 13:42, Daniel Henrique Barboza wrote:
The microchip_icicle_kit, sifive_u, spike and virt boards are now doing
the same steps when '-kernel' is used:
- execute load_kernel()
- load init_rd()
- write kernel_cmdline
Let's fold everything inside riscv_load_kernel() to avoid code
On 28/12/22 08:24, Philippe Mathieu-Daudé wrote:
On 24/12/22 16:18, Richard Henderson wrote:
As in page_get_flags, we need to try again with the mmap
lock held if we fail a page lookup.
Signed-off-by: Richard Henderson
---
accel/tcg/user-exec.c | 39 ---
Signed-off-by: Richard Henderson
[PMD: Split patch in 2]
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-maint.c | 53 ++--
1 file changed, 27 insertions(+), 26 deletions(-)
diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c
index
This test is used to do a quick sanity check to ensure that we're able
to run the existing QEMU FW image.
'sifive_u', 'spike' and 'virt' riscv64 machines, and 'sifive_u' and
'virt' 32 bit machines are able to run the default RISCV64_BIOS_BIN |
RISCV32_BIOS_BIN firmware with minimal options.
The
On 28/12/22 13:49, Philippe Mathieu-Daudé wrote:
Signed-off-by: Richard Henderson
[PMD: Split patch in 2]
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-maint.c | 53 ++--
1 file changed, 27 insertions(+), 26 deletions(-)
Reviewed-by:
When called from syscall(), we are not within a TB and pc == 0.
We can skip the check for invalidating the current TB.
Signed-off-by: Richard Henderson
[PMD: Split patch in 2]
Signed-off-by: Philippe Mathieu-Daudé
---
accel/tcg/tb-maint.c | 17 -
1 file changed, 12
The MachineState object provides a 'fdt' pointer that is already being
used by other RISC-V machines, and it's also used by the 'dumpdtb' QMP
command.
Remove the 'fdt' pointer from SiFiveUState and use MachineState::fdt
instead.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
All callers are using kernel_filename as machine->kernel_filename.
This will also simplify the changes in riscv_load_kernel() that we're
going to do next.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c
'filename', 'mem_size' and 'fdt' from riscv_load_initrd() can all be
retrieved by the MachineState object for all callers.
Cc: Palmer Dabbelt
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Bin Meng
---
hw/riscv/boot.c| 6 --
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