On 2022/12/28 下午6:50, Philippe Mathieu-Daudé wrote:
On 23/12/22 15:23, Chuang Xu wrote:
Before using any flatview, sanity check we're not during a memory
region transaction or the map can be invalid.
Signed-off-by: Chuang Xu
---
include/exec/memory.h | 9 +
softmmu/memory.c |
On 2022/12/24 上午12:06, David Hildenbrand wrote:
On 23.12.22 15:23, Chuang Xu wrote:
The duration of loading non-iterable vmstate accounts for a significant
portion of downtime (starting with the timestamp of source qemu stop and
ending with the timestamp of target qemu start). Most of the time
On 3/1/23 20:45, Philippe Mathieu-Daudé wrote:
On 3/1/23 20:39, Philippe Mathieu-Daudé wrote:
On 3/1/23 18:39, BALATON Zoltan wrote:
On Tue, 3 Jan 2023, Philippe Mathieu-Daudé wrote:
When a BAR is not mapped, the displayed size is shifted by 1 byte:
(qemu) info pci
...
Bus 0, device
Hi Laszlo,
Happy new year!
On 4/1/23 08:04, Laszlo Ersek wrote:
Adding Michael. The thread started here:
https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00199.html
More below:
On 1/4/23 07:06, Laszlo Ersek wrote:
On 1/3/23 18:42, Laszlo Ersek wrote:
(resending with qemu-devel on
Adding Michael. The thread started here:
https://lists.gnu.org/archive/html/qemu-devel/2023-01/msg00199.html
More below:
On 1/4/23 07:06, Laszlo Ersek wrote:
> On 1/3/23 18:42, Laszlo Ersek wrote:
>> (resending with qemu-devel on CC; sorry!)
>>
>> Hi,
>>
>> this is with QEMU-7.2.
>
> This is a
On 1/4/23 07:06, Laszlo Ersek wrote:
> On 1/3/23 18:42, Laszlo Ersek wrote:
>> (resending with qemu-devel on CC; sorry!)
>>
>> Hi,
>>
>> this is with QEMU-7.2.
>
> This is a regression. It works fine with QEMU-5.0. The regression has
> not been fixed since QEMU-7.2, as of master @ 222059a0fccf
On 1/3/23 18:42, Laszlo Ersek wrote:
> (resending with qemu-devel on CC; sorry!)
>
> Hi,
>
> this is with QEMU-7.2.
This is a regression. It works fine with QEMU-5.0. The regression has
not been fixed since QEMU-7.2, as of master @ 222059a0fccf ("Merge tag
'pull-ppc-20221221' of
On Wed, Jan 4, 2023 at 1:30 AM Peter Xu wrote:
>
> On Mon, Dec 26, 2022 at 12:09:52PM +0800, Jason Wang wrote:
> > On Sat, Dec 24, 2022 at 12:26 AM Peter Xu wrote:
> > >
> > > On Fri, Dec 23, 2022 at 03:48:01PM +0800, Jason Wang wrote:
> > > > On Wed, Dec 7, 2022 at 6:13 AM Peter Xu wrote:
> >
This patch adds irq number property for loongarch msi interrupt
controller, and remove hard coding irq number macro.
Signed-off-by: Tianrui Zhao
Reviewed-by: Philippe Mathieu-Daud??
---
hw/intc/loongarch_pch_msi.c | 29 ++---
hw/loongarch/virt.c
Change the default irq number of pch pic to 32, so that the irq
number of pch msi is 224(256 - 32), and move the 'PCH_PIC_IRQ_NUM'
macro to pci-host/ls7a.h and add prefix 'VIRT' on it to keep standard
format.
Signed-off-by: Tianrui Zhao
Reviewed-by: Philippe Mathieu-Daud??
---
With loongarch 7A1000 manual, irq number supported can be set
in PCH_PIC_INT_ID_HI register. This patch adds irq number property
for loongarch_pch_pic, so that virt machine can set different
irq number when pch_pic intc is added.
Signed-off-by: Tianrui Zhao
---
hw/intc/loongarch_pch_pic.c
This series add irq number property for loongarch pch_msi
and pch_pic interrupt controller.
Changes for v5:
(1) Remove unreachable check after using g_new() to alloc msi irq.
(2) Use deposit32() to generate the value of pch pic irq info.
Changes for v4:
(1) Change the default irq number of pch
On 1/3/23 10:16, Richard Henderson wrote:
Richard Henderson (40):
target/arm: Remove aarch64_cpu_finalizefn
target/arm: Create arm_cpu_register_parent
target/arm: Remove AArch64CPUClass
target/arm: Create TYPE_ARM_V7M_CPU
...
target/arm: Utilize arm-cpu instance_post_init hook
Am 3. Januar 2023 17:25:35 UTC schrieb Chuck Zmudzinski :
>On 1/3/2023 8:38 AM, Bernhard Beschow wrote:
>>
>>
>> On Tue, Jan 3, 2023 at 2:17 PM Philippe Mathieu-Daudé
>> wrote:
>>
>> Hi Chuck,
>>
>> On 3/1/23 04:15, Chuck Zmudzinski wrote:
>> > On 1/2/23 4:34 PM, Bernhard Beschow
On Tue, Jan 03, 2023, Wang, Wei W wrote:
> On Tuesday, January 3, 2023 9:40 AM, Chao Peng wrote:
> > > Because guest memory defaults to private, and now this patch stores
> > > the attributes with KVM_MEMORY_ATTRIBUTE_PRIVATE instead of
> > _SHARED,
> > > it would bring more KVM_EXIT_MEMORY_FAULT
On 1/3/2023 4:50 PM, Chuck Zmudzinski wrote:
> On 1/3/2023 10:14 AM, Alex Williamson wrote:
> > On Mon, 2 Jan 2023 18:10:24 -0500
> > Chuck Zmudzinski wrote:
> >
> > > On 1/2/23 12:46 PM, Michael S. Tsirkin wrote:
> > > > On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote:
> > > >
It should be possible to reuse cache built by previous iteration
processing next executables. Already processed dependencies are
already skipped later based on dll name.
Signed-off-by: Arthur Sengileyev
---
scripts/nsis.py | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git
On 1/3/2023 10:14 AM, Alex Williamson wrote:
> On Mon, 2 Jan 2023 18:10:24 -0500
> Chuck Zmudzinski wrote:
>
> > On 1/2/23 12:46 PM, Michael S. Tsirkin wrote:
> > > On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote:
> > > > Intel specifies that the Intel IGD must occupy slot 2 on
On Wed, Dec 28, 2022 at 02:04:39PM +0100, Philippe Mathieu-Daudé wrote:
> When requesting the flatview output with 'info mtree -f',
> the MemoryRegion priority is irrelevant and noise. Remove it.
It is in many cases still helpful debugging information to me.
Maybe it's because it can cause
On 3/1/23 20:39, Philippe Mathieu-Daudé wrote:
On 3/1/23 18:39, BALATON Zoltan wrote:
On Tue, 3 Jan 2023, Philippe Mathieu-Daudé wrote:
When a BAR is not mapped, the displayed size is shifted by 1 byte:
(qemu) info pci
...
Bus 0, device 11, function 0:
Ethernet controller: PCI
On 3/1/23 18:39, BALATON Zoltan wrote:
On Tue, 3 Jan 2023, Philippe Mathieu-Daudé wrote:
When a BAR is not mapped, the displayed size is shifted by 1 byte:
(qemu) info pci
...
Bus 0, device 11, function 0:
Ethernet controller: PCI device 1022:2000
PCI subsystem :
On Tue, 3 Jan 2023 at 12:31, Peter Maydell wrote:
>
> On Tue, 3 Jan 2023 at 16:12, Alessandro Di Federico wrote:
> >
> > On Tue, 3 Jan 2023 10:51:36 -0500
> > Stefan Hajnoczi wrote:
> >
> > > QEMU's Makefile used to a use a technique where it generated
> > > "timestamp" files and used cmp(1) to
Hi Peter,
On 03.01.23 18:41, Peter Maydell wrote:
On Fri, 23 Dec 2022 at 08:50, Alexander Graf wrote:
While trying to make Windows work with GICv3 emulation, I stumbled over
the fact that it only supports ITT entry sizes that are power of 2 sized.
While the spec allows arbitrary sizes, in
On 3/1/23 19:16, Richard Henderson wrote:
These were previously left 'misnamed' to minimize the size
of the patch. Rename them all in bulk with no other change.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 858 ++--
target/arm/cpu_tcg.c | 1260
On 1/2/2023 12:46 PM, Michael S. Tsirkin wrote:
> On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote:
> > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> > as noted in docs/igd-assign.txt in the Qemu source code.
> >
> > Currently, when the xl toolstack is
Only qdev_prop_register_global requires a non-null array.
The other instances can simply exit early.
Signed-off-by: Richard Henderson
---
hw/core/qdev-properties.c | 43 ---
1 file changed, 27 insertions(+), 16 deletions(-)
diff --git
Create a features member in ARMCPUClass and copy to the instance in
arm_cpu_init. Settings of this value will come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 18 ++
target/arm/cpu.c | 1 +
2 files changed, 19 insertions(+)
diff --git
Create a new class initialization hook, to be called immediately
before creation of the first instance. Most class initialization
happens quite early, which makes interaction between classes
difficult. E.g. cpu objects often depend on the accellerator,
or the global properties coming from the
Create an arm cpu class with a specific abstract parent class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 7 ++-
target/arm/cpu.c | 4 ++--
2 files changed, 8 insertions(+), 3 deletions(-)
diff --git a/target/arm/cpu-qom.h b/target/arm/cpu-qom.h
index
Create a block of cpregs in ARMCPUClass and copy to the instance in
arm_cpu_init. Settings of these values will come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 98
target/arm/cpu.h | 43 ++-
Since kvm32 was removed, all kvm hosts support aarch64.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 6 ++
1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 28b5a07244..668e979a24 100644
--- a/target/arm/cpu64.c
+++
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Properly detect support in kvm_arm_get_host_cpu_features
rather than adjust much later in kvm_arch_init_vcpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 2 ++
The class structure is a plain wrapper around ARMCPUClass. We really
only need the QOM class, TYPE_AARCH64_CPU. The instance init and
fallback class init functions are identical to the same ones over
in cpu.c. Make arm_cpu_post_init static.
Signed-off-by: Richard Henderson
---
Use two intermediate functions to share code between
the 13 variants of pxa*_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 81 +---
1 file changed, 23 insertions(+), 58 deletions(-)
diff --git a/target/arm/cpu_tcg.c
Use an offsetof vs ARMCPUClass, which means that the regs[]
array may be static const, and we can include midr in the list.
Signed-off-by: Richard Henderson
---
target/arm/hvf/hvf.c | 38 --
1 file changed, 24 insertions(+), 14 deletions(-)
diff --git
Create a hash table of cpregs in ARMCPUClass and copy to the
instance in arm_cpu_init. Population of this new table will
come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 3 +++
target/arm/cpu.c | 23 +--
2 files changed, 24
Use an intermediate function to share code between
sa1100_class_init and sa1110_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu_tcg.c | 15 +--
1 file changed, 9 insertions(+), 6 deletions(-)
diff --git a/target/arm/cpu_tcg.c b/target/arm/cpu_tcg.c
index
If the instance_finalize hook is NULL, the hook is not called.
There is no need to install an empty function.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 2cf2ca4ce5..611b233d23
Streamline new instances of this hook, so that we always go
through arm_cpu_leaf_class_init first, performing common tasks,
and have resolved the ARMCPUClass.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 2 +-
target/arm/cpu.c | 10 +++---
2 files changed, 8
We can now store these values into ARMCPUClass instead of into
a temporary ARMHostCPUFeatures structure.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 14 ++---
target/arm/cpu64.c | 18 +--
target/arm/kvm.c | 119 +--
3 files
These settings are generic and identical between the two
host accelerators.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 23 ++-
target/arm/hvf/hvf.c | 13 +
target/arm/kvm.c | 29 ++---
3 files changed, 25
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h| 3 +++
target/arm/cpu.h| 3 ---
hw/arm/aspeed_ast2600.c | 6 +++--
target/arm/cpu.c| 50
These were previously left 'misnamed' to minimize the size
of the patch. Rename them all in bulk with no other change.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 858 ++--
target/arm/cpu_tcg.c | 1260 +-
2 files
We can now store these values into ARMCPUClass instead of into
a temporary ARMHostCPUFeatures structure.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5
target/arm/hvf_arm.h | 2 +-
target/arm/cpu.c | 13 --
target/arm/cpu64.c | 4 +--
target/arm/hvf/hvf.c |
Replace ARMCPU.mp_affinity with CPUARMState.cp15.mpidr_el1,
setting the additional bits as required. In particular,
always set the U bit when there is only one cpu in the system.
Remove the mp_is_up bit which attempted to do the same thing.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h
Wrapper to return the mp affinity bits from the cpu.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 5 +
hw/arm/virt-acpi-build.c | 2 +-
hw/arm/virt.c | 6 +++---
hw/arm/xlnx-versal-virt.c | 3 ++-
hw/misc/xlnx-versal-crl.c | 4 ++--
target/arm/arm-powerctl.c
Quite a lot of the cpu definition is constant, and can be initialized
once with the type, rather than for each object instance. For now,
leave the "host" cpu with the object init.
Note that the "max" class (and even a converted "host") must be delayed
until accellerator init, which itself is
With appropriate sorting of functions, this allows quite a
number of prototypes to be removed from kvm_arm.h, and the
corresponding functions made static.
Signed-off-by: Richard Henderson
---
target/arm/kvm_arm.h | 190
target/arm/kvm.c | 2048
Remove the cfgend variable entirely and reuse the property
accessor functions created for reset-hivecs. This removes
the last setting of cpu->reset_sctlr, to we can remove that
as well, using only the class value.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 8
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 2 ++
target/arm/cpu.h | 2 --
hw/arm/allwinner-h3.c | 5 ++-
hw/arm/exynos4210.c | 18 +-
hw/arm/integratorcp.c
Replace the properties with separate cpu classes that have
these features disabled. These stand in the way of moving
all id-register properties to the cpu class level, because
of the case of SSE200, which has one cortex-m33 with dsp+vfp
and one without.
Create the full set of m-profile cpus with
Create a new intermediate abstract class for v7m, like we do for
aarch64. The initialization of ARMCPUClass.info follows the
concrete class, so remove that init from arm_v7m_class_init.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 6 ++
target/arm/cpu_tcg.c | 36
There was even a TODO comment that we ought to be using a cpu
property, but we failed to update when the property was added.
Use ARM_AFF1_SHIFT instead of the bare constant 8.
Signed-off-by: Richard Henderson
---
hw/arm/bcm2836.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
Remove the reset_hivecs variable entirely and create
property accessor functions that directly read/write
a bit of the reset value of SCTLR.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 -
hw/arm/digic.c | 11 -
hw/arm/npcm7xx.c | 9
Setting is not actually functional here, because it is always done
after the creation of the first object, and so will generate an error.
But at least it's a different error than 'Property not found'.
Signed-off-by: Richard Henderson
---
target/arm/monitor.c | 21 -
1 file
Move the default initialization of dtb_compatible to arm_cpu_class_init,
and copy back to the instance in arm_cpu_init. Further class overrides
will come in a future patch.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 3 +++
target/arm/cpu.c | 15 ++-
2 files
With the movement of the property, we can remove the field from the
cpu entirely, using only the class. However, late initialization
of the "max" cpu, due to its interaction with "host", means that we
cannot leave the class property undefined when EL2 is not supported.
Adjust the class field to
With the movement of the properties, we can remove the fields
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h| 4 +
target/arm/cpu.h| 4 -
hw/arm/aspeed_ast2600.c | 3 +-
target/arm/cpu.c| 340
This will allow registration of cpregs at the class level.
Signed-off-by: Richard Henderson
---
target/arm/cpregs.h | 33 +++
target/arm/helper.c | 47 +
2 files changed, 55 insertions(+), 25 deletions(-)
diff --git
With the movement of the property, we can remove the field
from the cpu entirely, using only the class.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 -
hw/arm/xilinx_zynq.c | 9 ++---
hw/intc/armv7m_nvic.c | 2 +-
target/arm/cpu.c | 18 --
With the introduction of aarch64_host_class_init, we have
enough feature bits set to do propagation early. Move the
tcg consistency checks to class_late_init, after we have
populated all of the id registers.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 162
Rename to arm_build_mp_affinity. This frees up the name for
other usage, and emphasizes that the cpu object is not involved.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 2 +-
hw/arm/npcm7xx.c | 2 +-
hw/arm/sbsa-ref.c | 2 +-
hw/arm/virt.c | 2 +-
target/arm/cpu.c | 6 +++---
Rather than call arm_cpu_post_init ourselves from the
object instance_init, let QOM handle this.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 11 ++-
1 file changed, 2 insertions(+), 9 deletions(-)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index b16d9bbe47..a6c6916f36
With the movement of the properties, we can remove the has_mpu field
from the cpu entirely, using only the class. The pmsav7_dregion field
must stay in the cpu to handle the usage with VMSTATE_VARRAY_UINT32.
Signed-off-by: Richard Henderson
---
target/arm/cpu-qom.h | 3 ++
target/arm/cpu.h
These properties apply to the class itself, as opposed to
object_class_property_* in which the property is attached
to the class but applies to each object instance.
Apply global properties via a class_late_init on DeviceClass.
Signed-off-by: Richard Henderson
---
hw/core/qdev-prop-internal.h
The specific problem I'm trying to solve is the location and
representation of the coprocessor register hash table for ARM cpus,
but in the process affects how cpu initialization might be done for
all targets.
At present, each cpu (for all targets) is initialized separately.
For some, like ARM,
On Tue, 3 Jan 2023 11:02:31 -0500
Gregory Price wrote:
> The fine grained control would be a precursor to an emulated pooling
> device. If you can demonstrate it with a singleton attached device, you
> could just implement an exclusivity table in a shared file, and set the
> shared memory to a
* David Woodhouse (dw...@infradead.org) wrote:
> From: Joao Martins
>
> Handle the hypercall to set a per vcpu info, and also wire up the default
> vcpu_info in the shared_info page for the first 32 vCPUs.
>
> To avoid deadlock within KVM a vCPU thread must set its *own* vcpu_info
> rather than
On Wed, 21 Dec 2022 20:24:38 -0800
Ira Weiny wrote:
> To facilitate testing provide a QMP command to inject a general media
> event. The event can be added to the log specified.
>
> Signed-off-by: Ira Weiny
Hi Ira,
Suggestion inline on how to more neatly handle optional arguments using
QMPs
* David Woodhouse (dw...@infradead.org) wrote:
> From: David Woodhouse
>
> For the shared info page and for grant tables, Xen shares its own pages
> from the "Xen heap" to the guest. The guest requests that a given page
> from a certain address space (XENMAPSPACE_shared_info, etc.) be mapped
>
Peter Maydell writes:
> On Fri, 23 Dec 2022 at 17:21, Alex Bennée wrote:
>>
>> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
>>
>> Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu
>> into staging (2022-12-21 18:08:09 +)
>>
>> are available
Hi, Paolo,
On Wed, Dec 28, 2022 at 09:27:50AM +0100, Paolo Bonzini wrote:
> Il ven 23 dic 2022, 16:54 Peter Xu ha scritto:
>
> > > This is not valid because the transaction could happen in *another*
> > thread.
> > > In that case memory_region_transaction_depth() will be > 0, but RCU is
> > >
On Thu, 22 Dec 2022 at 21:55, Philippe Mathieu-Daudé wrote:
>
> ARM CPUs fetch instructions in little-endian.
>
> smpboot[] encoded instructions are written in little-endian.
>
> We call tswap32() on the array. tswap32 function swap a 32-bit
> value if the target endianness doesn't match the host
(resending with qemu-devel on CC; sorry!)
Hi,
this is with QEMU-7.2.
"docs/specs/acpi_cpu_hotplug.rst" writes:
> Legacy ACPI CPU hotplug interface registers
> ---
> ...
> - The first DWORD in bitmap is used in write mode to switch from legacy
> to
On Tue, 3 Jan 2023, Philippe Mathieu-Daudé wrote:
When a BAR is not mapped, the displayed size is shifted by 1 byte:
(qemu) info pci
...
Bus 0, device 11, function 0:
Ethernet controller: PCI device 1022:2000
PCI subsystem :
IRQ 10, pin A
BAR0: I/O at
On Fri, 23 Dec 2022 at 08:50, Alexander Graf wrote:
>
> While trying to make Windows work with GICv3 emulation, I stumbled over
> the fact that it only supports ITT entry sizes that are power of 2 sized.
>
> While the spec allows arbitrary sizes, in practice hardware will always
> expose power of
On Thu, 22 Dec 2022 at 21:56, Philippe Mathieu-Daudé wrote:
>
> ARM CPUs fetch instructions in little-endian.
>
> smpboot[] encoded instructions are written in little-endian.
> This is fine on little-endian host, but on big-endian ones
> the smpboot[] array ends swapped. Use the const_le32()
>
On Tue, 3 Jan 2023 at 16:12, Alessandro Di Federico wrote:
>
> On Tue, 3 Jan 2023 10:51:36 -0500
> Stefan Hajnoczi wrote:
>
> > QEMU's Makefile used to a use a technique where it generated
> > "timestamp" files and used cmp(1) to check if rebuilding was
> > necessary:
> > 1. Always generate
On Mon, Dec 26, 2022 at 12:09:52PM +0800, Jason Wang wrote:
> On Sat, Dec 24, 2022 at 12:26 AM Peter Xu wrote:
> >
> > On Fri, Dec 23, 2022 at 03:48:01PM +0800, Jason Wang wrote:
> > > On Wed, Dec 7, 2022 at 6:13 AM Peter Xu wrote:
> > > >
> > > > It seems not super clear on when iova_tree is
On 1/3/2023 8:38 AM, Bernhard Beschow wrote:
>
>
> On Tue, Jan 3, 2023 at 2:17 PM Philippe Mathieu-Daudé
> wrote:
>
> Hi Chuck,
>
> On 3/1/23 04:15, Chuck Zmudzinski wrote:
> > On 1/2/23 4:34 PM, Bernhard Beschow wrote:
> >> This series first renders TYPE_PIIX3_XEN_DEVICE
On Wed, 21 Dec 2022 20:24:37 -0800
Ira Weiny wrote:
> CXL has 24 bit unaligned fields which need to be stored to. CXL is
> specified as little endian.
>
> Define st24_le_p() and the supporting functions to store such a field
> from a 32 bit host native value.
>
> The use of b, w, l, q as the
When a BAR is not mapped, the displayed size is shifted by 1 byte:
(qemu) info pci
...
Bus 0, device 11, function 0:
Ethernet controller: PCI device 1022:2000
PCI subsystem :
IRQ 10, pin A
BAR0: I/O at 0x [0x001e].
BAR1: 32
On Wed, 21 Dec 2022 20:24:34 -0800
Ira Weiny wrote:
> The device status register block was defined. However, there were no
> individual registers nor any data wired up.
>
> Define the event status register [CXL 3.0; 8.2.8.3.1] as part of the
> device status register block. Wire up the
On Wed, 21 Dec 2022 20:24:33 -0800
Ira Weiny wrote:
> The cel_uuid was programatically generated previously because there was
> no static initializer for network order UUIDs.
>
> Use the new network order initializer for cel_uuid. Adjust
> cxl_initialize_mailbox() because it can't fail now.
>
Hi Alistair,
On Wed, Dec 28, 2022 at 11:08 AM Alistair Francis wrote:
>
> On Fri, Dec 23, 2022 at 11:14 PM Anup Patel wrote:
> >
> > On Thu, Dec 15, 2022 at 8:55 AM Alistair Francis
> > wrote:
> > >
> > > On Mon, Dec 12, 2022 at 9:12 PM Anup Patel
> > > wrote:
> > > >
> > > > On Mon, Dec
On Tue, 3 Jan 2023 10:51:36 -0500
Stefan Hajnoczi wrote:
> QEMU's Makefile used to a use a technique where it generated
> "timestamp" files and used cmp(1) to check if rebuilding was
> necessary:
> 1. Always generate meson-buildoptions.sh-timestamp.
`meson-buildoptions.sh-timestamp` would be
On Fri, 23 Dec 2022 at 17:21, Alex Bennée wrote:
>
> The following changes since commit 222059a0fccf4af3be776fe35a5ea2d6a68f9a0b:
>
> Merge tag 'pull-ppc-20221221' of https://gitlab.com/danielhb/qemu into
> staging (2022-12-21 18:08:09 +)
>
> are available in the Git repository at:
>
>
The fine grained control would be a precursor to an emulated pooling
device. If you can demonstrate it with a singleton attached device, you
could just implement an exclusivity table in a shared file, and set the
shared memory to a file backend as well. Boom, shared memory pool across
qemu
On Tue, 20 Dec 2022 14:27:31 -0500
Gregory Price wrote:
> On Tue, Dec 20, 2022 at 03:34:53PM +, Jonathan Cameron wrote:
> > > However I don't think this is successful in creating the dax devices,
> > > and therefore the reconfiguring into ram.
> >
> > Sure. I only bothered testing the it
On 03/01/2023 13:13, Dr. David Alan Gilbert wrote:
External email: Use caution opening links or attachments
* Avihai Horon (avih...@nvidia.com) wrote:
As part of its error flow, vfio_vmstate_change() accesses
MigrationState->to_dst_file without any checks. This can cause a NULL
pointer
On Tue, Jan 03, 2023 at 04:48:14PM +0100, Cédric Le Goater wrote:
> On 1/3/23 16:31, Peter Delevoryas wrote:
> > On Mon, Jan 02, 2023 at 02:31:31PM +0100, Cédric Le Goater wrote:
> > > On 12/31/22 23:52, Dong, Eddie wrote:
> > > > > When booting the Zephyr demo in [1] we get:
> > > > >
> > > > >
On Tue, 3 Jan 2023 at 10:26, Alessandro Di Federico wrote:
>
> On Tue, 3 Jan 2023 09:37:51 -0500
> Stefan Hajnoczi wrote:
>
> > I don't understand the issue. Can you describe the steps that cause
> > meson-buildoptions.sh to become out-of-sync with meson_options.txt?
> >
> > This will continue
On 1/3/23 16:31, Peter Delevoryas wrote:
On Mon, Jan 02, 2023 at 02:31:31PM +0100, Cédric Le Goater wrote:
On 12/31/22 23:52, Dong, Eddie wrote:
When booting the Zephyr demo in [1] we get:
aspeed.io: unimplemented device write (size 4, offset 0x185128, value
0x030f1ff1) <--
aspeed.io:
Makes sense to me.
Reviewed-by: Alessandro Di Federico
On Tue, 3 Jan 2023 10:47:58 +
Alex Bennée wrote:
> +"Templates" and generated code
> +==
> +
> +We make heavy use of C's macro facilities combined with multiple
> +inclusion to generate code. This tends to
On Mon, Jan 02, 2023 at 02:31:31PM +0100, Cédric Le Goater wrote:
> On 12/31/22 23:52, Dong, Eddie wrote:
> > > When booting the Zephyr demo in [1] we get:
> > >
> > >aspeed.io: unimplemented device write (size 4, offset 0x185128, value
> > > 0x030f1ff1) <--
> > >aspeed.io: unimplemented
On Tue, 3 Jan 2023 09:37:51 -0500
Stefan Hajnoczi wrote:
> I don't understand the issue. Can you describe the steps that cause
> meson-buildoptions.sh to become out-of-sync with meson_options.txt?
>
> This will continue to be a problem in the future. Is there a way to
> fix it permanently?
In
On Fri, Dec 30, 2022 at 12:34:54PM +0100, Philippe Mathieu-Daudé wrote:
> Avoid confusing two different things:
> - the WDT I/O region size ('iosize')
> - at which offset the SoC map the WDT ('offset')
> While it is often the same, we can map smaller region sizes
> at larger offsets.
>
> Here we
On Mon, 2 Jan 2023 18:10:24 -0500
Chuck Zmudzinski wrote:
> On 1/2/23 12:46 PM, Michael S. Tsirkin wrote:
> > On Sun, Jan 01, 2023 at 06:52:03PM -0500, Chuck Zmudzinski wrote:
> > > Intel specifies that the Intel IGD must occupy slot 2 on the PCI bus,
> > > as noted in docs/igd-assign.txt in
Am 3. Januar 2023 08:47:59 UTC schrieb Thomas Huth :
>We want to get rid of the "#ifdef TARGET_I386" statements in the mc146818
>code, so we need a different way to decide whether the slew tick policy
>is available or not. Introduce a new property "slew-tick-policy-available"
>which can be set
On 1/3/23 15:08, Thomas Huth wrote:
On 03/01/2023 12.00, Laurent Vivier wrote:
Signed-off-by: Laurent Vivier
Acked-by: Michael S. Tsirkin
---
Notes:
v4:
- rework EXPECT_STATE()
- use g_dir_make_tmp()
v3:
- Add "-M none" to avoid error:
"No machine
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