On 27/02/2023 21.25, Richard Henderson wrote:
On 2/27/23 01:50, Daniel P. Berrangé wrote:
On Mon, Feb 27, 2023 at 12:10:49PM +0100, Thomas Huth wrote:
Hardly anybody still uses 32-bit x86 hosts today, so we should
start deprecating them to finally have less test efforts.
With regards to 32-bit
On 27/02/2023 21.12, Michael S. Tsirkin wrote:
On Mon, Feb 27, 2023 at 11:50:07AM +, Daniel P. Berrangé wrote:
I feel like we should have separate deprecation entries for the
i686 host support, and for qemu-system-i386 emulator binary, as
although they're related they are independant feature
Move the dtb load bits outside of create_fdt(), and put it explicitly
in sifive_u_machine_init() and virt_machine_init(). With such change
create_fdt() does exactly what its function name tells us.
Suggested-by: Daniel Henrique Barboza
Signed-off-by: Bin Meng
---
Changes in v2:
- new patch: Mov
Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt'
machines, QEMU complains:
qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS
The whole DT generation logic should be skipped when a given DTB is
present.
Fixes: b1f19f238cae ("hw/riscv: write bootargs 'chose
Hi, Richard
在 2023/2/25 上午7:01, Richard Henderson 写道:
On 2/23/23 21:24, gaosong wrote:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_w_h,
.opt_opc = vecop_list,
.vece = MO_32
},
{
.fniv = gen_vaddwe
On 27/02/2023 23.32, Philippe Mathieu-Daudé wrote:
On 27/2/23 21:12, Michael S. Tsirkin wrote:
On Mon, Feb 27, 2023 at 11:50:07AM +, Daniel P. Berrangé wrote:
I feel like we should have separate deprecation entries for the
i686 host support, and for qemu-system-i386 emulator binary, as
alth
On 27/02/2023 19.38, Daniel P. Berrangé wrote:
On Mon, Feb 27, 2023 at 12:10:48PM +0100, Thomas Huth wrote:
We're struggling quite badly with our CI minutes on the shared
gitlab runners, so we urgently need to think of ways to cut down
our supported build and target environments. qemu-system-i38
On Mon, Feb 27, 2023 at 04:41:21PM +0100, Igor Mammedov wrote:
> On Fri, 24 Feb 2023 19:56:58 +0530
> Sunil V L wrote:
>
> > Hi Igor,
> >
> > On Fri, Feb 24, 2023 at 01:53:43PM +0100, Igor Mammedov wrote:
> > > On Fri, 24 Feb 2023 14:06:58 +0530
> > > Sunil V L wrote:
> > >
> > > > Add Multi
Hi ,
Can I know when this patch will be integrated to upstream?
Thank you,
Siddhi Katage
-Original Message-
From: Philippe Mathieu-Daudé
Sent: Wednesday, January 25, 2023 5:52 AM
To: Siddhi Katage ; qemu-devel@nongnu.org
Cc: Joe Jin ; Dongli Zhang ;
christian.ehrha...@canonical.com; be
On Mon, Feb 06, 2023 at 05:28:16PM +, Jonathan Cameron wrote:
> From: Ira Weiny
>
> The cel_uuid was programatically generated previously because there was
> no static initializer for network order UUIDs.
>
> Use the new network order initializer for cel_uuid. Adjust
> cxl_initialize_mailbo
On Mon, Feb 06, 2023 at 05:28:15PM +, Jonathan Cameron wrote:
> From: Ira Weiny
>
> UUID's are defined as network byte order fields. No static initializer
> was available for UUID's in their standard big endian format.
>
> Define a big endian initializer for UUIDs.
>
> Reviewed-by: Gregory
On Mon, Feb 06, 2023 at 05:28:14PM +, Jonathan Cameron wrote:
> From: Ira Weiny
>
> Gcc requires constant versions of cpu_to_le* calls.
>
> Add a 64 bit version.
>
> Reviewed-by: Peter Maydell
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
On Mon, Feb 06, 2023 at 05:28:13PM +, Jonathan Cameron wrote:
> Dropping the ID effects this table in trivial fashion.
>
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> tests/data/acpi/q35/DSDT.cxl| Bi
On Mon, Feb 06, 2023 at 05:28:12PM +, Jonathan Cameron wrote:
> Noticed as this prevents iASL disasembling the DSDT table.
>
> Reviewed-by: Ira Weiny
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
> hw/i386/acpi-build
On Mon, Feb 06, 2023 at 05:28:11PM +, Jonathan Cameron wrote:
> Next patch will drop duplicate _UID entry so allow update.
>
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
Reviewed-by: Fan Ni
> ---
> tests/qtest/bios-tables-test-allowed-diff.h
On Mon, Feb 06, 2023 at 05:28:10PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> Remove usage of magic numbers when accessing capacity fields and replace
> with CXL_CAPACITY_MULTIPLIER, matching the kernel definition.
>
> Signed-off-by: Gregory Price
> Reviewed-by: Davidlohr Bueso
>
On Mon, Feb 06, 2023 at 05:28:09PM +, Jonathan Cameron wrote:
> From: Gregory Price
>
> Current code sets to STORAGE_EXPRESS and then overrides it.
>
> Reviewed-by: Davidlohr Bueso
> Reviewed-by: Ira Weiny
> Signed-off-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-b
On Mon, Feb 06, 2023 at 05:28:07PM +, Jonathan Cameron wrote:
> msix_init_exclusive_bar() can fail, so if it does cleanup the address space.
>
> Reviewed-by: Ira Weiny
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Signed-off-by: Jonathan Cameron
> ---
Reviewed-by: Fan Ni
>
On Mon, Feb 06, 2023 at 05:28:08PM +, Jonathan Cameron wrote:
> Fix capitalization difference between struct name and typedef.
>
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Philippe Mathieu-Daudé
> Reviewed-by: Ira Weiny
> Reviewed-by: Gregory Price
> Tested-by: Gregory Price
> Sig
在 2023/2/28 上午2:40, Richard Henderson 写道:
On 2/27/23 02:55, gaosong wrote:
在 2023/2/25 上午3:24, Richard Henderson 写道:
{
.fniv = gen_vaddwev_s,
.fno = gen_helper_vaddwev_q_d,
.opt_opc = vecop_list,
.vece = MO_128
},
There
> > Optimize the virtio-balloon feature on the ARM platform by adding a
> > variable to keep track of the current hot-plugged pc-dimm size,
> > instead of traversing the virtual machine's memory modules to count
> > the current RAM size during the balloon inflation or deflation
> > process. This va
Hi,
On Mon, Feb 27, 2023, at 1:40 AM, Marc-André Lureau wrote:
> Hi
>
> On Fri, Feb 24, 2023 at 8:31 AM Daniel Xu wrote:
>>
>> This commit adds a test to ensure `merge-output` functions as expected.
>> We also add a negative test to ensure we haven't regressed previous
>> functionality.
>>
>> Sig
Hi,
On Mon, Feb 27, 2023, at 1:22 AM, Marc-André Lureau wrote:
> Hi
>
> On Fri, Feb 24, 2023 at 8:31 AM Daniel Xu wrote:
>>
>> Currently, the captured output (via `capture-output`) is segregated into
>> separate GuestExecStatus fields (`out-data` and `err-data`). This means
>> that downstream con
Hi Marc-André,
Thanks for reviewing the series.
On Mon, Feb 27, 2023, at 1:16 AM, Marc-André Lureau wrote:
> Hi
>
> On Fri, Feb 24, 2023 at 8:31 AM Daniel Xu wrote:
>>
>> It looks like qga's working directory is in a tempdir. So the relative
>> path that the test case gives qga through the QGA_O
在 2023/2/28 上午3:37, Richard Henderson 写道:
On 2/26/23 21:10, Song Gao wrote:
According to the 3A5000 manual 4.1 implement Chip Configuration
Version Register(0x). The manual does not state that 0x0018 is
reserved for the vendor name and 0x0028 is reserved for the chip name.
Signed-off-by:
Allow the line length to extend to 548 columns. While annoyingly wide,
it's still less confusing than the continuations we print. Also, the
default VL used by Linux (and max for A64FX) uses only 140 columns.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 36 ++-
Always print each matrix row whole, one per line, so that we
get the entire matrix in the proper shape.
Signed-off-by: Richard Henderson
---
target/arm/cpu.c | 18 ++
1 file changed, 18 insertions(+)
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index f1f454e7a0..0e54e19b05 1
Based-on: 20230227213329.793795-1-richard.hender...@linaro.org
("[PATCH v3 00/14] target/arm: gdbstub cleanups and additions")
Support SME by the same method as currently used by SVE. While I'm
sure proper gdb support for dynamically sizing SME will require changes,
this is good enough to examine
Mirror the existing support for SVE.
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 +
target/arm/internals.h | 3 ++
target/arm/gdbstub.c | 8
target/arm/gdbstub64.c | 88 ++
4 files changed, 100 insertions(+)
diff --git a/targ
On 2/26/23 17:59, Song Gao wrote:
+Note: build release bios need set --buildtarget=RELEASE,
Note: To build the release version of the bios, set...
Otherwise,
Reviewed-by: Richard Henderson
r~
On 2/26/23 17:59, Song Gao wrote:
LoongArch has enabled CONFIG_SMBIOS, but didn't enable CLI '-smbios'.
Fixes: 3efa6fa1e629 ("hw/loongarch: Add smbios support")
Acked-by: Michael S. Tsirkin
Reviewed-by: Markus Armbruster
Signed-off-by: Song Gao
Message-Id: <20230208094133.2945979-2-gaos...@lo
> -Original Message-
> From: Anton Johansson
> Sent: Friday, February 24, 2023 6:06 AM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain
> ; Matheus Bernardino (QUIC)
>
> Subject: Re: [PATCH v5 12/14] Hexagon (tar
Gah! I didn't mean to tag this one with for-8.0.
r~
On 2/27/23 13:05, Palmer Dabbelt wrote:
On Mon, 27 Feb 2023 05:51:52 PST (-0800), a...@rev.ng wrote:
Signed-off-by: Anton Johansson
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target
On Mon, 27 Feb 2023 05:51:52 PST (-0800), a...@rev.ng wrote:
Signed-off-by: Anton Johansson
Reviewed-by: Philippe Mathieu-Daudé
---
target/riscv/cpu.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 93b52b826c..9eb748a283
Do not provide a fast-path for physical addresses,
as those will need to be validated for GPC.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 35 ++-
1 file changed, 14 insertions(+), 21 deletions(-)
diff --git a/target/arm/pt
Add a cpu property to set GPCCR_EL3.L0GPTSZ, for testing
various possible configurations.
Signed-off-by: Richard Henderson
---
target/arm/cpu64.c | 37 +
1 file changed, 37 insertions(+)
diff --git a/target/arm/cpu64.c b/target/arm/cpu64.c
index 4066950da1..7
The function takes the fields as filled in by
the Arm ARM pseudocode for TakeGPCException.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index d2
With RME, SEL2 must also be present to support secure state.
The NS bit is RES1 if SEL2 is not present.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 66c5
This fixes a bug in which we failed to initialize
the result attributes properly after the memset.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 11 +--
1 file changed, 1 insertion(+), 10 deletions(-)
diff --git
Add input and output space members to S1Translate.
Set and adjust them in S1_ptw_translate, and the
various points at which we drop secure state.
Initialize the space in get_phys_addr; for now
leave get_phys_addr_with_secure considering only
secure vs non-secure spaces.
Reviewed-by: Peter Maydell
Place the check at the end of get_phys_addr_with_struct,
so that we check all physical results.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 249 +++
1 file changed, 232 insertions(+), 17 deletions(-)
diff --git
With FEAT_RME, there are four physical address spaces.
For now, just define the symbols, and mention them in
the same spots as the other Phys indexes in ptw.c.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu-param.h | 2 +-
ta
Handle GPC Fault types in arm_deliver_fault, reporting as
either a GPC exception at EL3, or falling through to insn
or data aborts at various exception levels.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 1 +
target/arm/internals.h | 27 ++
While Root and Realm may read and write data from other spaces,
neither may execute from other pa spaces.
This happens for Stage1 EL3, EL2, EL2&0, and Stage2 EL1&0.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 52 ++-
Test in_space instead of in_secure so that we don't switch
out of Root space. Handle the output space change immediately,
rather than try and combine the NSTable and NS bits later.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 27 ++-
This was added in 7e98e21c098 as part of a reorg in which
one of the argument had been legally NULL, and this caught
actual instances. Now that the reorg is complete, this
serves little purpose.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
With Realm security state, bit 55 of a block or page descriptor during
the stage2 walk becomes the NS bit; during the stage1 walk the bit 5
NS bit is RES0. With Root security state, bit 11 of the block or page
descriptor during the stage1 walk becomes the NSE bit.
Rather than collecting an NS bit
This is arbitrary, but used by the Huawei TF-A test code.
Signed-off-by: Richard Henderson
---
include/hw/arm/virt.h | 2 ++
hw/arm/virt.c | 43 +++
2 files changed, 45 insertions(+)
diff --git a/include/hw/arm/virt.h b/include/hw/arm/virt.h
inde
It will be helpful to have ARMMMUIdx_Phys_* to be in the same
relative order as ARMSecuritySpace enumerators. This requires
the adjustment to the nstable check. While there, check for being
in secure state rather than rely on clearing the low bit making
no change to non-secure state.
Reviewed-by:
Instead of passing this to get_phys_addr_lpae, stash it
in the S1Translate structure.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 27 ---
1 file changed, 12 insertions(+), 15 deletions(-)
diff -
We will need 2 bits to represent ARMSecurityState.
Do not attempt to replace or widen secure, even though it
logically overlaps the new field -- there are uses within
e.g. hw/block/pflash_cfi01.c, which don't know anything
specific about ARM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Hen
Add the missing field for ID_AA64PFR0, and the predicate.
Disable it if EL3 is forced off by the board or command-line.
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ++
target/arm/cpu.c | 4
2 files changed, 1
This includes GPCCR, GPTBR, MFAR, the TLB flush insns PAALL, PAALLOS,
RPALOS, RPAOS, and the cache flush insns CIPAPA and CIGDPAPA.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 19 +++
target/arm/helper.c | 83
Introduce both the enumeration and functions to retrieve
the current state, and state outside of EL3.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 89 ++---
target/arm/helper.c | 60 ++
Based-on: 20230227225832.816605-1-richard.hender...@linaro.org
("[PATCH for-8.0 v4 0/4] target/arm: pre-FEAT_RME fixes")
This is based on mainline, without any extra ARMv9-A dependencies
which are still under development. This is good enough to pass
all of the tests within
https://github.com
Define the missing SCR and HCR bits, allow SCR_NSE and {SCR,HCR}_GPF
to be set, and invalidate TLBs when NSE changes.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 5 +++--
target/arm/helper.c | 10 --
2 files changed, 11 insertions(+), 4 deletio
These were part of the v3 RME patch set, but are bug fixes
that should not be deferred until all of RME is ready.
r~
Richard Henderson (4):
target/arm: Handle m-profile in arm_is_secure
target/arm: Stub arm_hcr_el2_eff for m-profile
target/arm: Diagnose incorrect usage of arm_is_secure subr
In several places we use arm_is_secure_below_el3 and
arm_is_el3_or_mon separately from arm_is_secure.
These functions make no sense for m-profile, and
would indicate prior incorrect feature testing.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1421
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/arm/cpu.h b/target/arm/cpu.h
index 12b1082537..7a2f804aeb 100644
--- a/target/arm/cpu.h
+++
M-profile doesn't have HCR_EL2. While we could test features
before each call, zero is a generally safe return value to
disable the code in the caller. This test is required to
avoid an assert in arm_is_secure_below_el3.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/a
Integrate neighboring code from get_phys_addr_lpae which computed
starting level, as it is easier to validate when doing both at the
same time. Mirror the checks at the start of AArch{64,32}.S2Walk,
especially S2InvalidSL and S2InconsistentSL.
This reverts 49ba115bb74, which was incorrect -- ther
> -Original Message-
> From: Richard Henderson
> Sent: Monday, February 27, 2023 3:01 PM
> To: Taylor Simpson ; qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys.
On 27/2/23 15:52, Erico Nunes wrote:
The URL listed previously is no longer valid and that caused the test
to skip.
Signed-off-by: Erico Nunes
---
tests/avocado/virtio-gpu.py | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tests/avocado/virtio-gpu.py b/tests/avocado/v
On 27/2/23 15:28, David Woodhouse wrote:
From: David Woodhouse
The xen_overlay device (and later similar devices for event channels and
grant tables) need to be instantiated. Do this from a kvm_type method on
the PC machine derivatives, since KVM is only way to support Xen emulation
for now.
S
On 27/2/23 21:12, Michael S. Tsirkin wrote:
On Mon, Feb 27, 2023 at 11:50:07AM +, Daniel P. Berrangé wrote:
I feel like we should have separate deprecation entries for the
i686 host support, and for qemu-system-i386 emulator binary, as
although they're related they are independant features w
On 20/2/23 10:52, Philippe Mathieu-Daudé wrote:
On 20/2/23 10:10, Gerd Hoffmann wrote:
On Mon, Feb 20, 2023 at 09:00:44AM +0100, Philippe Mathieu-Daudé wrote:
In order to allow Frankenstein uses such plugging a PIIX3
IDE function on a ICH9 chipset (which already exposes AHCI
ports...) as:
$
On 27/2/23 18:47, BALATON Zoltan wrote:
On Mon, 27 Feb 2023, Bernhard Beschow wrote:
Unfortunately my patches had changes merged in. This now makes it hard to
show what really changed (spoiler: nothing that affects behavior).
As you probably noticed in the "resend" version of this iteration I s
On 27/2/23 18:40, Richard W.M. Jones wrote:
These two tests were failing with this error:
stderr:
TAP parsing error: version number must be on the first line
[...]
Unknown TAP version. The first line MUST be `TAP version `. Assuming
version 12.
This can be fixed by ensuring we alwa
On 2/27/23 11:55, Taylor Simpson wrote:
-HexValue mask = gen_tmp_value(c, locp, mask_str,
- dst_width, UNSIGNED);
+HexValue mask = gen_constant(c, locp, "-1", dst_width,
+ UNSIGNED);
OUT(c, locp, "tcg_gen_shr_i", &dst_width, "(",
-
This commit adds a new audiodev backend to allow QEMU to use Pipewire as
both an audio sink and source. This backend is available on most systems
Add Pipewire entry points for QEMU Pipewire audio backend
Add wrappers for QEMU Pipewire audio backend in qpw_pcm_ops()
qpw_write function returns the c
Hi Alex,
On 27/2/23 17:34, Alex Williamson wrote:
On Mon, 27 Feb 2023 16:04:16 +
Peter Maydell wrote:
On Mon, 27 Feb 2023 at 15:46, Alex Williamson
wrote:
On Mon, 27 Feb 2023 11:32:57 +0100
Philippe Mathieu-Daudé wrote:
Signed-off-by: Philippe Mathieu-Daudé
Empty commit logs ar
> -Original Message-
> From: Richard Henderson
> Sent: Sunday, February 26, 2023 10:42 PM
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys...@users.source
> -Original Message-
> From: Richard Henderson
> Sent: Sunday, February 26, 2023 10:42 PM
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys...@users.source
> -Original Message-
> From: Richard Henderson
> Sent: Sunday, February 26, 2023 10:42 PM
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys...@users.source
> -Original Message-
> From: Richard Henderson
> Sent: Sunday, February 26, 2023 10:42 PM
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys...@users.source
> -Original Message-
> From: Richard Henderson
> Sent: Sunday, February 26, 2023 10:42 PM
> To: qemu-devel@nongnu.org
> Cc: qemu-...@nongnu.org; qemu-...@nongnu.org; qemu-
> ri...@nongnu.org; qemu-s3...@nongnu.org; jcmvb...@gmail.com;
> kbast...@mail.uni-paderborn.de; ys...@users.sourcef
On Mon, Feb 27, 2023 at 03:31:26PM +, Jonathan Cameron wrote:
> v2:
> - Rebase and pick up tags.
> - State prereq patche sets more clearly.
>
> Mostly sending out again because some of the precursors have been updated
> and to fix a typo in a tag given on v1.
>
> Until now, testing using CXL
ion" patch
The following changes since commit e1f9f73ba15e0356ce1aa3317d7bd294f587ab58:
Merge tag 'pull-target-arm-20230227' of
https://git.linaro.org/people/pmaydell/qemu-arm into staging (2023-02-27
14:46:00 +)
are available in the Git repository at:
https://github
From: David Reiss
Allow the function to be used outside of m_helper.c.
Rename with an "arm_" prefix.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Reiss
[rth: Split out of a larger patch]
Signed-off-by: Richard Henderson
---
target/arm/internals.h|
This function is not used outside gdbstub.c.
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 1 -
target/arm/gdbstub.c | 2 +-
2 files changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/arm/cpu.h b/target/arm/
This is my pauth enhancements from last year, the corresponding gdb
patches for which are nearing merge. If lore and patchew are to be
believed, I never posted this to the list, only pushed a branch so
that issue #1105 could see it.
Since the cleanups there conflict with the recent m-profile gdbs
The extension is primarily defined by the Linux kernel NT_ARM_PAC_MASK
ptrace register set.
The original gdb feature consists of two masks, data and code, which are
used to mask out the authentication code within a pointer. Following
discussion with Luis Machado, add two more masks in order to su
It looks like the author didn't include a "Signed off" in their patch draft
and it doesn't look like Debian qemu-kvm maintainers ever merged it.
Does this change the patch adoption process?
Thanks,
-Dinah
On Mon, Feb 27, 2023 at 4:23 PM Dinah B wrote:
> Thanks, here's the original patch:
> http
Create a subroutine for creating the union of unions
of the various type sizes that a vector may contain.
Reviewed-by: Fabiano Rosas
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 83 +++---
1 file changed, 45 insert
Keep the logic for pauth within pauth_helper.c, and expose
a helper function for use with the gdbstub pac extension.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/internals.h| 10 ++
target/arm/tcg/pauth_helper.c | 26 ++
2 fi
This will make the function usable between SVE and SME.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 28 ++--
1 file changed, 14 insertions(+), 14 deletions(-)
diff --git a/target/arm/gdbst
Make the form of the function names between fp and sve the same:
- arm_gdb_*_svereg -> aarch64_gdb_*_sve_reg.
- aarch64_fpu_gdb_*_reg -> aarch64_gdb_*_fpu_reg.
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/internals.h | 8 +++
Order suf[] by the log8 of the width.
Use ARRAY_SIZE instead of hard-coding 128.
This changes the order of the union definitions,
but retains the order of the union-of-union members.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 10 ++
1 file
The function is only used for aarch64, so move it to the
file that has the other aarch64 gdbstub stuff. Move the
declaration to internals.h.
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/cpu.h | 6 ---
target/arm/interna
Define svep based on the size of the predicates,
not the primary vector registers.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 895
Reviewed-by: Fabiano Rosas
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c
index 070ba20d99..895e19f084 100644
--- a/target/ar
Rather than increment base_reg and num, compute num from the change
to base_reg at the end. Clean up some nearby comments.
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: Richard Henderson
---
target/arm/gdbstub64.c | 27 ---
1 file changed, 16 insertions(+), 11 dele
From: David Reiss
Allow the function to be used outside of m_helper.c.
Move to be outside of ifndef CONFIG_USER_ONLY block.
Rename from get_v7m_sp_ptr.
Reviewed-by: Peter Maydell
Reviewed-by: Philippe Mathieu-Daudé
Signed-off-by: David Reiss
[rth: Split out of a larger patch]
Signed-off-by: R
The upstream gdb xml only implements {MSP,PSP}{,_NS,S}, but
go ahead and implement the other system registers as well.
Since there is significant overlap between the two, implement
them with common code. The only exception is the systemreg
view of CONTROL, which merges the banked bits as per MRS.
On 27/2/23 19:22, Peter Maydell wrote:
On Mon, 27 Feb 2023 at 14:08, Philippe Mathieu-Daudé wrote:
- buildsys
- Various header cleaned up (removing pointless headers)
- Mark various files/code user/system specific
- Mak
Thanks, here's the original patch:
https://bugs.debian.org/cgi-bin/bugreport.cgi?att=2;bug=621529;filename=multiboot2.patch;msg=15
On Mon, Feb 27, 2023 at 4:59 AM Alex Bennée wrote:
>
> Dinah B writes:
>
> > Hi,
> >
> > I'm looking to get more involved in contributing to QEMU. I noticed that
>
Fabiano Rosas writes:
> Alex Bennée writes:
>
>> Fabiano Rosas writes:
>>
>>> Our dockerfiles no longer reference layers from other qemu images so
>>> we can now use 'docker build' on them.
>>>
>>> Also reinstate the caching that was disabled due to bad interactions
>>> with certain runners. Se
Alex Bennée writes:
> Fabiano Rosas writes:
>
>> Our dockerfiles no longer reference layers from other qemu images so
>> we can now use 'docker build' on them.
>>
>> Also reinstate the caching that was disabled due to bad interactions
>> with certain runners. See commit 6ddc3dc7a8 ("tests/docker
The CoQueue API offers thread-safety via the lock argument that
qemu_co_queue_wait() and qemu_co_enter_next() take. BlockBackend
currently does not make use of the lock argument. This means that
multiple threads submitting I/O requests can corrupt the CoQueue's
QSIMPLEQ.
Add a QemuMutex and pass i
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