Bug in master branch: IbmPrep40pMachine.test_factory_firmware_and_netbsd broken

Hi all, seems like we've got another bug that sneaked in during the CI minutes blackout: The avocado test IbmPrep40pMachine.test_factory_firmware_and_netbsd is now broken reliably, see: https://gitlab.com/qemu-project/qemu/-/jobs/3858833617#L300 https://gitlab.com/thuth/qemu/-/jobs/38587

Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble

Hello, Palmer! Thanks for your reviewing I'm sorry, I sent V2 patch, but forgot to add the appropriate tag. Please see https://lists.nongnu.org/archive/html/qemu-devel/2023-02/msg05278.html It was also reviewed by Daniel Henrique Barboza and weiwei 02.03.2023 3:32, Palmer Dabbelt пишет: On

[PATCH] tests/data/acpi/virt: drop (most) duplicate files.

When virt ACPI files were added, lots of duplicates were created because we forgot that there's a no-prefix fallback: e.g. if tests/data/acpi/virt/APIC.memhp is not there then test will use tests/data/acpi/virt/APIC. Drop these. These were found with $find tests/data/acpi/ -type f -exec sha256sum

Re: [PATCH 6/6] monitor: convert monitor_cleanup() to AIO_WAIT_WHILE_UNLOCKED()

Stefan Hajnoczi writes: > monitor_cleanup() is called from the main loop thread. Calling Correct. > AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is > equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks > the AioContext and the latter's assertion tha

Re: [PATCH 5/6] hmp: convert handle_hmp_command() to AIO_WAIT_WHILE_UNLOCKED()

Stefan Hajnoczi writes: > The HMP monitor runs in the main loop thread. Calling Correct. > AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is > equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks > the AioContext and the latter's assertion that we're i

[PULL 5/5] target/ppc: Restrict 'qapi-commands-machine.h' to system emulation

From: Philippe Mathieu-Daudé Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Move the QMP functions from cpu_init.c (which is always compiled) to monitor.c (which is only

[PULL 0/5] Monitor patches for 2023-03-02

The following changes since commit 627634031092e1514f363fd8659a579398de0f0e: Merge tag 'buildsys-qom-qdev-ui-20230227' of https://github.com/philmd/qemu into staging (2023-02-28 15:09:18 +) are available in the Git repository at: https://repo.or.cz/qemu/armbru.git tags/pull-monitor-2023

[PULL 3/5] target/i386: Restrict 'qapi-commands-machine.h' to system emulation

From: Philippe Mathieu-Daudé Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Guard qmp_query_cpu_definitions() within CONFIG_USER_ONLY; move x86_cpu_class_check_missing_f

[PULL 2/5] target/arm: Restrict 'qapi-commands-machine.h' to system emulation

From: Philippe Mathieu-Daudé Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Move the QMP functions from helper.c (which is always compiled) to monitor.c (which is only c

[PULL 1/5] readline: fix hmp completion issue

From: Dongli Zhang The auto completion does not work in some cases. Case 1. 1. (qemu) info reg 2. Press 'Tab'. 3. It does not auto complete. Case 2. 1. (qemu) block_resize flo 2. Press 'Tab'. 3. It does not auto complete 'floppy0'. Since the readline_add_completion_of() may add any completio

[PULL 4/5] target/loongarch: Restrict 'qapi-commands-machine.h' to system emulation

From: Philippe Mathieu-Daudé Since commit a0e61807a3 ("qapi: Remove QMP events and commands from user-mode builds") we don't generate the "qapi-commands-machine.h" header in a user-emulation-only build. Extract the QMP functions from cpu.c (which is always compiled) to the new 'loongarch-qmp-cmd

Re: [PATCH] virtio: fix reachable assertion due to stale value of cached region size

On Thu, Feb 16, 2023 at 6:23 AM Carlos López wrote: > > In virtqueue_{split,packed}_get_avail_bytes() descriptors are read > in a loop via MemoryRegionCache regions and calls to > vring_{split,packed}_desc_read() - these take a region cache and the > index of the descriptor to be read. > > For dir

Re: [PATCH v3 07/10] qapi: implement conditional command arguments

Marc-André Lureau writes: > Hi > > On Wed, Mar 1, 2023 at 5:16 PM Markus Armbruster wrote: >> What about 3. have an additional command conditional on CONFIG_WIN32? >> Existing getfd stays the same: always fails when QEMU runs on a Windows >> host. The new command exists only when QEMU runs on a

Re: [PATCH v3 7/7] hw/cxl/events: Add injection of Memory Module Events

Jonathan Cameron wrote: > These events include a copy of the device health information at the > time of the event. Actually using the emulated device health would > require a lot of controls to manipulate that state. Given the aim > of this injection code is to just test the flows when events occu

duplicate acpi files

Hi guys, I got annoyed that whenever I run ./tests/data/acpi/rebuild-expected-aml.sh then my tree gets polluted with duplicate acpi files. If I forget to blow them away then later they become stale and bios table test fails. So wrote a script to find these hoping to teach rebuild-expected-aml.sh n

Re: [PATCH v3 6/7] hw/cxl/events: Add injection of DRAM events

Jonathan Cameron wrote: > Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event > provides information related to DRAM devices. > > Example injection command in QMP: > > { "execute": "cxl-inject-dram-event", > "arguments": { > "path": "/machine/peripheral/cxl-mem0", >

RE: [PATCH v5 05/14] Hexagon (target/hexagon) Analyze packet before generating TCG

> -Original Message- > From: Anton Johansson > Sent: Thursday, February 23, 2023 10:02 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: Re: [PATCH v5 05/14] Hexagon (

RE: [PATCH v5 13/14] Hexagon (target/hexagon) Reduce manipulation of slot_cancelled

> -Original Message- > From: Anton Johansson > Sent: Friday, February 24, 2023 7:24 AM > To: Taylor Simpson ; qemu-devel@nongnu.org > Cc: richard.hender...@linaro.org; phi...@linaro.org; a...@rev.ng; Brian Cain > ; Matheus Bernardino (QUIC) > > Subject: Re: [PATCH v5 13/14] Hexagon (tar

Re: [PATCH v2 03/18] target/riscv: Use g_assert() for the predicate() NULL check

On 2023/2/28 18:40, Bin Meng wrote: At present riscv_csrrw_check() checks the CSR predicate() against NULL and throws RISCV_EXCP_ILLEGAL_INST if it is NULL. But this is a pure software check, and has nothing to do with the emulation of the hardware behavior, thus it is inappropriate to return i

Re: [PATCH v2 02/18] target/riscv: Add some comments to clarify the priority policy of riscv_csrrw_check()

On 2023/2/28 18:40, Bin Meng wrote: The priority policy of riscv_csrrw_check() was once adjusted in commit eacaf4401956 ("target/riscv: Fix priority of csr related check in riscv_csrrw_check") whose commit message says the CSR existence check should come before the access control check, but th

Re: [PATCH v2 18/18] target/riscv: Group all predicate() routines together

On 2023/2/28 21:45, Bin Meng wrote: From: Bin Meng Move sstc()/sstc32() to where all predicate() routines live, and smstateen_acc_ok() to near {read,write}_xenvcfg(). Signed-off-by: Bin Meng Reviewed-by: Weiwei Li --- Changes in v2: - move smstateen_acc_ok() to near {read,write}_xenvcfg()

Re: [PATCH v2 17/18] target/riscv: Drop priv level check in mseccfg predicate()

On 2023/2/28 21:45, Bin Meng wrote: From: Bin Meng riscv_csrrw_check() already does the generic privilege level check hence there is no need to do the specific M-mode access check in the mseccfg predicate(). With this change debugger can access the mseccfg CSR anytime. Signed-off-by: Bin Me

Re: [PATCH v2 16/18] target/riscv: Allow debugger to access sstc CSRs

On 2023/2/28 21:45, Bin Meng wrote: From: Bin Meng At present with a debugger attached sstc CSRs can only be accssed when CPU is in M-mode, or configured correctly. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as

Re: [PATCH v2 15/18] target/riscv: Allow debugger to access {h,s}stateen CSRs

On 2023/2/28 21:45, Bin Meng wrote: From: Bin Meng At present {h,s}stateen CSRs are not reported in the CSR XML hence gdb cannot access them. Fix it by adjusting their predicate() routine logic so that the static config check comes before the run-time check, as well as adding a debugger chec

Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

On 2023/3/2 8:30, Bin Meng wrote: On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt wrote: On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote: On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei wrote: On 2023/2/28 18:40, Bin Meng wrote: There is no need to generate the CSR XML if the Zicsr exte

Re: [PATCH 0/2] target/riscv: some vector_helper.c cleanups

On Sun, 26 Feb 2023 09:05:12 PST (-0800), dbarb...@ventanamicro.com wrote: Based-on: 20230222185205.355361-2-dbarb...@ventanamicro.com ("[PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg()") Hi, This is a re-send of patch 1, which is already reviewed, with a follow-up that uses riscv_cpu_c

Re: [PATCH 0/2] Fix the OpenSBI CI job and bump to v1.2

On Fri, 24 Feb 2023 13:25:41 PST (-0800), Palmer Dabbelt wrote: The OpenSBI version bump found a CI failure, which appears to actually have been related to the Docker version as opposed to the Ubuntu version -- at least assuming my local CI run

Re: [PATCH 0/4] RISCVCPUConfig related cleanups

Hi Palmer, On Thu, Mar 2, 2023 at 10:08 AM Palmer Dabbelt wrote: > > On Fri, 24 Feb 2023 09:45:16 PST (-0800), dbarb...@ventanamicro.com wrote: > > Hi, > > > > These cleanups were suggested by LIU Zhiwei during the review of the > > RISCV_FEATURE_* cleanups, currently on version 7 [1]. > > > > Th

Re: [PATCH v3 4/8] hw/isa/vt82c686: Implement PCI IRQ routing

On Wed, 1 Mar 2023, Mark Cave-Ayland wrote: On 27/02/2023 16:52, Bernhard Beschow wrote: On Mon, Feb 27, 2023 at 1:57 PM BALATON Zoltan > wrote: in. So if >> fuloon2e needs to do that then it should. I'll check that as I was focusing > > fuloong2e

Re: [PATCH 1/2] target/riscv/vector_helper.c: create vext_set_tail_elems_1s()

On Sun, 26 Feb 2023 10:23:01 PST (-0800), phi...@linaro.org wrote: On 26/2/23 18:05, Daniel Henrique Barboza wrote: Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector load / store instructions") added code to set the tail elements to 1 in the end of vext_ldst_stride(), vext_ld

Re: [PATCH 0/4] RISCVCPUConfig related cleanups

On Fri, 24 Feb 2023 09:45:16 PST (-0800), dbarb...@ventanamicro.com wrote: Hi, These cleanups were suggested by LIU Zhiwei during the review of the RISCV_FEATURE_* cleanups, currently on version 7 [1]. These are dependent on the patch "[PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg()" f

Re: [RFC] CXL: TCG/KVM instruction alignment issue discussion default

On Tue, Feb 28, 2023 at 4:54 PM Jonathan Cameron wrote: > > On Mon, 27 Feb 2023 11:06:47 + > Jørgen Hansen wrote: > > > On 2/18/23 11:22, Gregory Price wrote: > > > Breaking this off into a separate thread for archival sake. > > > > > > There's a bug with handling execution of instructions he

Re: [PATCH 2/6] target/riscv: Fix the relationship of PBMTE/STCE fields between menvcfg and henvcfg

On Fri, 24 Feb 2023 04:36:43 PST (-0800), liwei...@iscas.ac.cn wrote: On 2023/2/24 20:19, Andrew Jones wrote: On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote: henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero. Signed-off-by: Weiwei Li Signed-off-by: Junqiang Wang

Re: [PATCH 0/6] target/riscv: Add support for Svadu extension

On Thu, 23 Feb 2023 20:08:46 PST (-0800), liwei...@iscas.ac.cn wrote: This patchset adds support svadu extension. It also fixes some relationship between *envcfg fields and Svpbmt/Sstc extensions. Specification for Svadu extension can be found in: https://github.com/riscv/riscv-svadu The port

Re: [PATCH v2 4/6] hw/cxl: QMP based poison injection support

On Mon, Feb 27, 2023 at 05:03:09PM +, Jonathan Cameron wrote: > Inject poison using qmp command cxl-inject-poison to add an entry to the > poison list. > > For now, the poison is not returned CXL.mem reads, but only via the > mailbox command Get Poison List. > > See CXL rev 3.0, sec 8.2.9.8.4

Re: [PATCH v2 1/2] hw/riscv: Skip re-generating DT nodes for a given DTB

On Mon, 27 Feb 2023 23:45:21 PST (-0800), bm...@tinylab.org wrote: Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt' machines, QEMU complains: qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS The whole DT generation logic should be skipped when a given D

Re: [PATCH] target/riscv: Add support for Zicond extension

On Tue, 21 Feb 2023 01:10:09 PST (-0800), liwei...@iscas.ac.cn wrote: The spec can be found in https://github.com/riscv/riscv-zicond. Two instructions are added: - czero.eqz: Moves zero to a register rd, if the condition rs2 is equal to zero, otherwise moves rs1 to rd. - czero.nez: Moves zer

Re: [PATCH v2 0/6] hw/cxl: Poison get, inject, clear

On Mon, Feb 27, 2023 at 05:03:05PM +, Jonathan Cameron wrote: Hi Jonathan, Can you share your repo with this support? How about your qemu cmdline? I'm more of a 'try it out' type of a reviewer for qemu changes. Thanks, Alison > v2: Thanks to Ira for review and also to Philippe as some of the

Re: [PATCH] target/riscv: Fix checking of whether instruciton at 'pc_next' spans pages

On Sun, 19 Feb 2023 23:27:32 PST (-0800), songsha...@eswincomputing.com wrote: This bug has a noticeable behavior of falling back to the main loop and respawning a redundant translation block including a single instruction when the end address of the compressive instruction is exactly on a page b

Re: [PATCH] RISC-V: XTheadMemPair: Remove register restrictions for store-pair

On Mon, 20 Feb 2023 01:56:12 PST (-0800), christoph.muell...@vrull.eu wrote: From: Christoph Müllner The XTheadMemPair does not define any restrictions for store-pair instructions (th.sdd or th.swd). However, the current code enforces the restrictions that are required for load-pair instruction

Re: Re: [PATCH v5 07/12] hmp: add cryptodev info command

On 3/1/23 18:47, Dr. David Alan Gilbert wrote: * zhenwei pi (pizhen...@bytedance.com) wrote: Example of this command: # virsh qemu-monitor-command vm --hmp info cryptodev cryptodev1: service=[akcipher|mac|hash|cipher] queue 0: type=builtin cryptodev0: service=[akcipher] queue 0: t

Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

On Wed, 01 Mar 2023 16:30:52 PST (-0800), Bin Meng wrote: On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt wrote: On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote: > On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei wrote: >> >> >> On 2023/2/28 18:40, Bin Meng wrote: >> > There is no need to ge

Re: [PATCH 14/33] tests: acpi: update expected blobs

On Fri, Feb 24, 2023 at 04:37:53PM +0100, Igor Mammedov wrote: > only following context change: > - Local1 = Zero > If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device > Labeling Interface */)) > { > Return (Local0) > ... > Return (Local0) > } > >

Re: [PATCH] [PATCH] disas/riscv Fix ctzw disassemble

On Fri, 17 Feb 2023 07:45:14 PST (-0800), dbarb...@ventanamicro.com wrote: On 2/17/23 12:14, Ivan Klokov wrote: Due to typo in opcode list, ctzw is disassembled as clzw instruction. The code was added by 02c1b569a15b4b06a so I believe a "Fixes:" tag is in order: Fixes: 02c1b569a15b ("disas

Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt wrote: > > On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote: > > On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei > > wrote: > >> > >> > >> On 2023/2/28 18:40, Bin Meng wrote: > >> > There is no need to generate the CSR XML if the Zicsr extension >

Re: [PATCH 14/33] tests: acpi: update expected blobs

On Fri, Feb 24, 2023 at 04:37:53PM +0100, Igor Mammedov wrote: > only following context change: > - Local1 = Zero > If ((Arg0 != ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device > Labeling Interface */)) > { > Return (Local0) > ... > Return (Local0) > } > >

Re: [PATCH v2 10/20] vfio/common: Record DMA mapped IOVA ranges

On 02/03/2023 00:07, Joao Martins wrote: > On 28/02/2023 20:36, Alex Williamson wrote: [...] >> Can we make the same argument that the overhead is negligible if a VM >> makes use of 10s of GB of virtio-mem with 2MB block size? >> >> But then on a 4KB host we're limited to 256 tracking entries, so

Re: [PATCH v2 10/20] vfio/common: Record DMA mapped IOVA ranges

On 28/02/2023 20:36, Alex Williamson wrote: > On Tue, 28 Feb 2023 12:11:06 + > Joao Martins wrote: >> On 23/02/2023 21:50, Alex Williamson wrote: >>> On Thu, 23 Feb 2023 21:19:12 + >>> Joao Martins wrote: On 23/02/2023 21:05, Alex Williamson wrote: > On Thu, 23 Feb 2023 10:37

Re: [RFC 22/52] riscv: Replace MachineState.smp access with topology helpers

On Tue, 14 Feb 2023 18:57:35 PST (-0800), zhao1@linux.intel.com wrote: On Tue, Feb 14, 2023 at 10:17:45AM +0800, Mi, Dapeng1 wrote: Date: Tue, 14 Feb 2023 10:17:45 +0800 From: "Mi, Dapeng1" Subject: RE: [RFC 22/52] riscv: Replace MachineState.smp access with topology helpers > From: Zhao

Re: [PATCH v7 00/10] make write_misa a no-op and FEATURE_* cleanups

On Wed, 22 Feb 2023 10:51:55 PST (-0800), dbarb...@ventanamicro.com wrote: Hi, In this version we gave up removing all the write_misa() body and, instead, we went back to something closer to what we were doing in v2. write_misa() is now gated behind an experimental x-misa-w cfg option, defaulted

Re: [PATCH v2 00/14] target/riscv: Some updates to float point related extensions

On Tue, 14 Feb 2023 18:05:25 PST (-0800), liwei...@iscas.ac.cn wrote: Specification for Zv* extensions can be found in: https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc The port is available here: https://github.com/plctlab/plct-qemu/tree/plct-zvfh-upstream-v2 v2: * improve the e

Re: [PATCH v2 05/18] target/riscv: gdbstub: Do not generate CSR XML if Zicsr is disabled

On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote: On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei wrote: On 2023/2/28 18:40, Bin Meng wrote: > There is no need to generate the CSR XML if the Zicsr extension > is not enabled. Should we generate the FPU XML or Vector XML when Zicsr is not en

Re: [PATCH v2 3/6] bswap: Add the ability to store to an unaligned 24 bit field

On Mon, Feb 27, 2023 at 05:03:08PM +, Jonathan Cameron wrote: > From: Ira Weiny > > CXL has 24 bit unaligned fields which need to be stored to. CXL is > specified as little endian. > > Define st24_le_p() and the supporting functions to store such a field > from a 32 bit host native value. >

Re: [PATCH v2 2/6] hw/cxl: Introduce cxl_device_get_timestamp() utility function

On Mon, Feb 27, 2023 at 05:03:07PM +, Jonathan Cameron wrote: > From: Ira Weiny > > There are new users of this functionality coming shortly so factor > it out from the GET_TIMESTAMP mailbox command handling. > > Signed-off-by: Ira Weiny > Signed-off-by: Jonathan Cameron Reviewed-by: Fan

Re: [PATCH v2 1/6] hw/cxl: rename mailbox return code type from ret_code to CXLRetCode

On Mon, Feb 27, 2023 at 05:03:06PM +, Jonathan Cameron wrote: > Given the increasing usage of this mailbox return code type, now > is a good time to switch to QEMU style naming. > > Reviewed-by: Ira Weiny > Signed-off-by: Jonathan Cameron > Reviewed-by: Fan Ni > -- > v7: (thanks to Ira W

Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive irq in i8259 model

On Wed, 1 Mar 2023, David Woodhouse wrote: On Wed, 2023-03-01 at 19:01 +0100, BALATON Zoltan wrote: It isn't a *correct* fix without a little bit more typing, but does this make it work? diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c index 17910f3bcb..36ebcff025 100644 --- a/hw/intc/i8259.c +

Re: [PATCH 3/5] qmp: Added the helper stamp check.

Daniel P. Berrangé writes: > On Wed, Mar 01, 2023 at 03:53:47PM +0100, Toke Høiland-Jørgensen wrote: >> Daniel P. Berrangé writes: >> >> > On Tue, Feb 28, 2023 at 11:21:56PM +0100, Toke Høiland-Jørgensen wrote: >> >> Daniel P. Berrangé writes: >> >> >> >> > On Tue, Feb 28, 2023 at 08:01:51PM

Re: [PATCH v2 03/20] vfio/migration: Add VFIO migration pre-copy support

On Wed, 1 Mar 2023 17:12:51 -0400 Jason Gunthorpe wrote: > On Wed, Mar 01, 2023 at 12:55:59PM -0700, Alex Williamson wrote: > > > So it seems like what we need here is both a preface buffer size and a > > target device latency. The QEMU pre-copy algorithm should factor both > > the remaining da

RE: [PATCH] tcg: `reachable_code_pass()` remove empty else-branch

> -Original Message- > From: Anton Johansson > Sent: Wednesday, March 1, 2023 7:22 AM > To: qemu-devel@nongnu.org > Cc: a...@rev.ng; richard.hender...@linaro.org; Taylor Simpson > > Subject: [PATCH] tcg: `reachable_code_pass()` remove empty else-branch > > This patch extends reachable

Re: [PATCH v7 00/23] Consolidate PIIX south bridges

On Thu, Feb 23, 2023 at 05:25:23PM +, Bernhard Beschow wrote: > Ping > > Can we queue the piix3 part already? Now that the series doesn't introduce a > PIC proxy any more the piix3 part is essentially QOM cleanup. > > Note that I cautiously dropped some Reviewed-by tags in the piix3 part as

Re: [PATCH][RESEND v3 1/3] hapvdimm: add a virtual DIMM device for memory hot-add protocols

On 1.03.2023 18:24, David Hildenbrand wrote: (...) With virtio-mem one can simply have per-node virtio-mem devices. 2) I'm not sure what's the overhead of having, let's say, 1 TiB backing memory device mostly marked madvise(MADV_DONTNEED). Like, how much memory + swap this setup would actually c

Re: [PATCH] virtio: fix reachable assertion due to stale value of cached region size

On Wed, Feb 15, 2023 at 11:14:46PM +0100, Carlos López wrote: > In virtqueue_{split,packed}_get_avail_bytes() descriptors are read > in a loop via MemoryRegionCache regions and calls to > vring_{split,packed}_desc_read() - these take a region cache and the > index of the descriptor to be read. > >

Re: [PATCH 2/5] hw/isa/vt82c686: Implement PCI IRQ routing

Am 1. März 2023 14:20:54 UTC schrieb Mark Cave-Ayland : >On 23/02/2023 20:20, Bernhard Beschow wrote: > >> The real VIA south bridges implement a PCI IRQ router which is configured >> by the BIOS or the OS. In order to respect these configurations, QEMU >> needs to implement it as well. >> >>

[PATCH 1/1] hw/riscv/virt.c: add cbom-block-size fdt property

From: Anup Patel The cbom-block-size fdt property property is used to inform the OS about the blocksize in bytes for the Zicbom cache operations. Linux documents it in Documentation/devicetree/bindings/riscv/cpus.yaml as: riscv,cbom-block-size: $ref: /schemas/types.yaml#/definitions/uint3

[PATCH 0/1] hw/riscv/virt.c: add cbom-block-size fdt property

Hi, I'm sending this almost last minute patch as part of the work done in: [PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions It turns out that the Linux kernel expects a 'cbom-block-size' FDT prop to be able to determine the cbom-block-size. Without this patch the kernel will misbe

Re: [PATCH 0/5] hw/timer/i8254: Un-inline and simplify IRQs

On Wed, Feb 15, 2023 at 06:43:48PM +0100, Philippe Mathieu-Daudé wrote: > i8254_pit_init() uses a odd pattern of "use this IRQ output > line if non-NULL, otherwise use the ISA IRQ #number as output". > > Rework as simply "Use this IRQ output". Acked-by: Michael S. Tsirkin Given it also affect

Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive irq in i8259 model

On Wed, 2023-03-01 at 19:01 +0100, BALATON Zoltan wrote: > > > It isn't a *correct* fix without a little bit more typing, but does > > this make it work? > > > > diff --git a/hw/intc/i8259.c b/hw/intc/i8259.c > > index 17910f3bcb..36ebcff025 100644 > > --- a/hw/intc/i8259.c > > +++ b/hw/intc/i825

Re: [PATCH 00/12] Q35 PCI host fixes and QOM cleanup

On Tue, Feb 14, 2023 at 02:14:29PM +0100, Bernhard Beschow wrote: > This series mostly cleans up QOM-related initialization code. It also performs > some modernization and fixing. > > The first patch originates from "PC and ICH9 clanups" series [1] which has > been > dropped in v3 in favor of ano

Re: [PATCH 00/12] Q35 PCI host fixes and QOM cleanup

On Tue, Feb 21, 2023 at 03:39:28PM +, Bernhard Beschow wrote: > > > Am 14. Februar 2023 13:14:29 UTC schrieb Bernhard Beschow : > >This series mostly cleans up QOM-related initialization code. It also > >performs > > > >some modernization and fixing. > > > > > > > >The first patch originates

Re: [PATCH 06/12] hw/pci-host/q35: Initialize properties just once

On Tue, Feb 14, 2023 at 02:14:35PM +0100, Bernhard Beschow wrote: > Although not used there, the attributes for Q35's "pci-hole64-size" and > "short_root_bus" properties currently reside in its child device. This > causes the default values to be overwritten during the child's > object_initialize()

Re: [PATCH 05/12] hw/pci-host/q35: Initialize "bypass-iommu" property from board code

On Tue, Feb 14, 2023 at 02:14:34PM +0100, Bernhard Beschow wrote: > The Q35 PCI host already has a "bypass-iommu" property. However, the > host initializes this property itself by accessing global machine state, > thereby assuming it to be a PC machine. Avoid this by having board code > set this pr

Re: [PATCH 03/12] hw/pci-host/q35: Use memory_region_set_address() also for tseg_blackhole

On Tue, Feb 14, 2023 at 02:14:32PM +0100, Bernhard Beschow wrote: > Deleting from and adding to the parent memory region seems to be the old > way of changing a memory region's address which is superseeded by > memory_region_set_address(). Moreover, memory_region_set_address() is > already used for

Re: [PATCH 02/12] hw/pci-host/q35: Fix contradicting .endianness assignment

On Tue, Feb 14, 2023 at 02:14:31PM +0100, Bernhard Beschow wrote: > Settle on little endian which is consistent with using > pci_host_conf_le_ops. > > Fixes: bafc90bdc594 'q35: implement TSEG' > Signed-off-by: Bernhard Beschow I think it's native because native is a bit cheaper and it's just 0xf

Re: [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions

Hi Palmer, On 3/1/23 18:35, Palmer Dabbelt wrote: On Thu, 23 Feb 2023 15:44:23 PST (-0800), dbarb...@ventanamicro.com wrote: Hi, This new version has changes based on feedbacks of both v5 and v6. Patch 1 was revamped. We're modifying probe_access_flags() to accept a 'size' parameter to allow

Re: [PATCH 02/12] hw/pci-host/q35: Fix contradicting .endianness assignment

On Tue, Feb 14, 2023 at 02:14:31PM +0100, Bernhard Beschow wrote: > Settle on little endian which is consistent with using > pci_host_conf_le_ops. > > Fixes: bafc90bdc594 'q35: implement TSEG' incorrect formatting for the fixes tag > Signed-off-by: Bernhard Beschow > --- > hw/pci-host/q35.c |

seeking advice for configuring usb_desc in ccid / dev-smartcard-reader.c

Hello in he/usb/dev-smartcard-reader.c: we need a slightly differing version of the "Athena Smart Card Reader" as of qemu_ccid_descriptor with two bytes changed to fixed "extended" values, 14 for max slot and 4 in feature 2. This data is shared by all ccid devices through a chain down to usb_desc

Re: [PATCH] vhost: accept VIRTIO_F_ORDER_PLATFORM as a valid SVQ feature

On Tue, Feb 14, 2023 at 09:36:01AM +0100, Eugenio Perez Martin wrote: > On Tue, Feb 14, 2023 at 8:51 AM Michael S. Tsirkin wrote: > > > > On Tue, Feb 14, 2023 at 08:02:08AM +0100, Eugenio Perez Martin wrote: > > > On Tue, Feb 14, 2023 at 7:31 AM Jason Wang wrote: > > > > > > > > On Tue, Feb 14, 2

Re: [PATCH v7 0/4] riscv: Add support for Zicbo[m,z,p] instructions

On Thu, 23 Feb 2023 15:44:23 PST (-0800), dbarb...@ventanamicro.com wrote: Hi, This new version has changes based on feedbacks of both v5 and v6. Patch 1 was revamped. We're modifying probe_access_flags() to accept a 'size' parameter to allow for RISC-V usage with PMP. Changes in the existing c

Re: [PATCH v7 1/4] tcg: add 'size' param to probe_access_flags()

On Thu, 23 Feb 2023 16:10:59 PST (-0800), Richard Henderson wrote: On 2/23/23 13:44, Daniel Henrique Barboza wrote: probe_access_flags() as it is today uses probe_access_full(), which in turn uses probe_access_internal() with size = 0. probe_access_internal() then uses the size to call the tlb_f

Re: [PATCH 12/12] hw: Move ich9.h to southbridge/

On Mon, Feb 27, 2023 at 01:22:37PM +0100, Philippe Mathieu-Daudé wrote: > On 13/2/23 18:30, Bernhard Beschow wrote: > > ICH9 is a south bridge which doesn't necessarily depend on x86, so move > > it into the southbridge folder, analoguous to PIIX. > > However it is still tied to it due to: > > hw

Re: [PATCH v5 3/7] hw/isa/vt82c686: Implement PCI IRQ routing

On Wed, 1 Mar 2023, Bernhard Beschow wrote: Am 1. März 2023 11:15:02 UTC schrieb BALATON Zoltan : On Wed, 1 Mar 2023, Bernhard Beschow wrote: Am 1. März 2023 00:17:09 UTC schrieb BALATON Zoltan : The real VIA south bridges implement a PCI IRQ router which is configured by the BIOS or the OS. I

Re: [PATCH v2 03/20] vfio/migration: Add VFIO migration pre-copy support

On Wed, Mar 01, 2023 at 12:55:59PM -0700, Alex Williamson wrote: > So it seems like what we need here is both a preface buffer size and a > target device latency. The QEMU pre-copy algorithm should factor both > the remaining data size and the device latency into deciding when to > transition to

Re: [PATCH v5 00/18] pci hotplug tracking

On Thu, Feb 16, 2023 at 09:03:38PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Hi all! > > v5: - don't deprecate IDs and return to ID & QOM scheme > - split complicated HOTPLUG_STATE patch into several ones picked up 1-12 new events and commands need more review, in particular by qapi main

Re: [PATCH v3 4/8] hw/isa/vt82c686: Implement PCI IRQ routing

On Wed, 1 Mar 2023, Mark Cave-Ayland wrote: On 27/02/2023 16:52, Bernhard Beschow wrote: On Mon, Feb 27, 2023 at 1:57 PM BALATON Zoltan > wrote: On Mon, 27 Feb 2023, BALATON Zoltan wrote: > On Mon, 27 Feb 2023, BALATON Zoltan wrote: >> On Mon, 27 Feb 202

Re: [PATCH v5 00/18] pci hotplug tracking

On Thu, Feb 16, 2023 at 09:03:38PM +0300, Vladimir Sementsov-Ogievskiy wrote: > Hi all! > > v5: - don't deprecate IDs and return to ID & QOM scheme > - split complicated HOTPLUG_STATE patch into several ones One small point: when you change patchset subject, that is ok, but pls reply to old

Re: [PATCH v2 07/10] hw/ide/piix: Require an ISABus only for user-created instances

Am 1. März 2023 16:42:16 UTC schrieb Mark Cave-Ayland : >On 23/02/2023 20:46, Bernhard Beschow wrote: >> >> >> Am 7. Februar 2023 20:52:02 UTC schrieb Mark Cave-Ayland >> : >>> On 06/02/2023 23:40, Bernhard Beschow wrote: >>> Am 5. Februar 2023 22:32:03 UTC schrieb Mark Cave-Ayland >>

Re: [PATCH v5 13/18] pci: introduce pci_find_the_only_child()

On Thu, Feb 16, 2023 at 09:03:51PM +0300, Vladimir Sementsov-Ogievskiy wrote: > To be used in further patch to identify the device hot-plugged into > pcie-root-port. > > Signed-off-by: Vladimir Sementsov-Ogievskiy > Reviewed-by: Anton Kuchin Wait a second does this work for multifunction device

Re: [PATCH v5 3/7] hw/isa/vt82c686: Implement PCI IRQ routing

Am 1. März 2023 11:15:02 UTC schrieb BALATON Zoltan : >On Wed, 1 Mar 2023, Bernhard Beschow wrote: >> Am 1. März 2023 00:17:09 UTC schrieb BALATON Zoltan : >>> The real VIA south bridges implement a PCI IRQ router which is configured >>> by the BIOS or the OS. In order to respect these configura

Re: [PATCH v5 14/18] qapi/qdev.json: unite DEVICE_* event data into single structure

On Thu, Feb 16, 2023 at 09:03:52PM +0300, Vladimir Sementsov-Ogievskiy wrote: > DEVICE_DELETED and DEVICE_UNPLUG_GUEST_ERROR has equal data, let's > refactor it to one structure. That also helps to add new events > consistently. > > Signed-off-by: Vladimir Sementsov-Ogievskiy Needs ack from QAPI

Re: [PATCH v5 18/18] qapi: introduce DEVICE_ON event

On Thu, Feb 16, 2023 at 09:03:56PM +0300, Vladimir Sementsov-Ogievskiy wrote: > We have DEVICE_DELETED event, that signals that device_del command is > actually completed. But we don't have a counter-part for device_add. > Still it's sensible for SHPC and PCIe-native hotplug, as there are time > wh

Re: [PATCH 0/5] Pegasos2 fixes and audio output support

On Wed, 1 Mar 2023, Bernhard Beschow wrote: Am 1. März 2023 19:24:20 UTC schrieb BALATON Zoltan : On Wed, 1 Mar 2023, Mark Cave-Ayland wrote: On 23/02/2023 09:13, Bernhard Beschow wrote: Am 22. Februar 2023 23:00:02 UTC schrieb BALATON Zoltan : On Wed, 22 Feb 2023, Bernhard Beschow wrote: Am

Re: [PATCH v3 4/8] hw/isa/vt82c686: Implement PCI IRQ routing

On 27/02/2023 16:52, Bernhard Beschow wrote: On Mon, Feb 27, 2023 at 1:57 PM BALATON Zoltan > wrote: On Mon, 27 Feb 2023, BALATON Zoltan wrote: > On Mon, 27 Feb 2023, BALATON Zoltan wrote: >> On Mon, 27 Feb 2023, Bernhard Beschow wrote: >>> Am 26. F

[PATCH 5/6] hmp: convert handle_hmp_command() to AIO_WAIT_WHILE_UNLOCKED()

The HMP monitor runs in the main loop thread. Calling AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks the AioContext and the latter's assertion that we're in the main loop succeeds. Signed-off-by: Ste

Re: [PATCH v5 5/7] hw/isa/vt82c686: Work around missing level sensitive irq in i8259 model

Am 1. März 2023 14:05:31 UTC schrieb David Woodhouse : >On Wed, 2023-03-01 at 14:18 +0100, BALATON Zoltan wrote: >> > Are you sure the PIC ELCR is actually set for the lines you're having >> > trouble with? Is that something the Pegasos SmartFirmware would have >> > done, and MorphOS is expectin

[PATCH 3/6] block: convert bdrv_graph_wrlock() to AIO_WAIT_WHILE_UNLOCKED()

The following conversion is safe and does not change behavior: GLOBAL_STATE_CODE(); ... - AIO_WAIT_WHILE(qemu_get_aio_context(), ...); + AIO_WAIT_WHILE_UNLOCKED(NULL, ...); Since we're in GLOBAL_STATE_CODE(), qemu_get_aio_context() is our home thread's AioContext. Thus AIO_WAIT_WH

[PATCH 4/6] block: convert bdrv_drain_all_begin() to AIO_WAIT_WHILE_UNLOCKED()

Since the AioContext argument was already NULL, AIO_WAIT_WHILE() was never going to unlock the AioContext. Therefore it is possible to replace AIO_WAIT_WHILE() with AIO_WAIT_WHILE_UNLOCKED(). Signed-off-by: Stefan Hajnoczi --- block/io.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) dif

[PATCH 6/6] monitor: convert monitor_cleanup() to AIO_WAIT_WHILE_UNLOCKED()

monitor_cleanup() is called from the main loop thread. Calling AIO_WAIT_WHILE(qemu_get_aio_context(), ...) from the main loop thread is equivalent to AIO_WAIT_WHILE_UNLOCKED(NULL, ...) because neither unlocks the AioContext and the latter's assertion that we're in the main loop succeeds. Signed-of

[PATCH 1/6] block: don't acquire AioContext lock in bdrv_drain_all()

There is no need for the AioContext lock in bdrv_drain_all() because nothing in AIO_WAIT_WHILE() needs the lock and the condition is atomic. Note that the NULL AioContext argument to AIO_WAIT_WHILE() is odd. In the future it can be removed. There is an assertion in AIO_WAIT_WHILE() that checks tha

[PATCH 2/6] block: convert blk_exp_close_all_type() to AIO_WAIT_WHILE_UNLOCKED()

There is no change in behavior. Switch to AIO_WAIT_WHILE_UNLOCKED() instead of AIO_WAIT_WHILE() to document that this code has already been audited and converted. The AioContext argument is already NULL so aio_context_release() is never called anyway. Signed-off-by: Stefan Hajnoczi --- block/exp

[PATCH 0/6] block: switch to AIO_WAIT_WHILE_UNLOCKED() where possible

AIO_WAIT_WHILE_UNLOCKED() is the future replacement for AIO_WAIT_WHILE(). Most callers haven't been converted yet because they rely on the AioContext lock. I looked through the code and found the easy cases that can be converted today. Stefan Hajnoczi (6): block: don't acquire AioContext lock in

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