[PATCH v3 27/57] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza

[PATCH v3 40/57] tcg/i386: Convert tcg_out_qemu_st_slow_path

Use tcg_out_st_helper_args. This eliminates the use of a tail call to the store helper. This may or may not be an improvement, depending on the call/return branch prediction of the host microarchitecture. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 57

[PATCH v3 20/57] tcg/loongarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_out_zext_addr_if_32_bit, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson ---

[PATCH v3 54/57] tcg/ppc: Remove unused constraints A, B, C, D

These constraints have not been used for quite some time. Fixes: 77b73de67632 ("Use rem/div[u]_i32 drop div[u]2_i32") Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-str.h | 4 1 file changed, 4 deletions(-) diff --git

Re: [PATCH v2 6/6] tests/migration: Only run auto_converge in slow mode

"Zhang, Chen" wrote: >> -Original Message- >> From: Daniel P. Berrangé >> Sent: Saturday, April 22, 2023 1:14 AM >> To: qemu-devel@nongnu.org >> Cc: qemu-bl...@nongnu.org; Paolo Bonzini ; >> Thomas Huth ; John Snow ; Li >> Zhijian ; Juan Quintela ; >> Stefan Hajnoczi ; Zhang, Chen >> ;

[PATCH v3 55/57] tcg/riscv: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target-con-set.h | 2 --

[PATCH v3 31/57] tcg/s390x: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, tcg_prepare_user_ldst, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson ---

[PATCH v3 48/57] tcg/loongarch64: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-2], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 2 --

[PATCH v3 29/57] tcg/s390x: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 22 ++ 1 file changed, 14 insertions(+), 8 deletions(-) diff --git

[PATCH v3 36/57] tcg: Introduce arg_slot_stk_ofs

Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg.c | 29 +

[PATCH v3 32/57] tcg/sparc64: Drop is_64 test from tcg_out_qemu_ld data return

In tcg_canonicalize_memop, we remove MO_SIGN from MO_32 operations with TCG_TYPE_I32. Thus this is never set. We already have an identical test just above which does not include is_64 Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 2 +-

[PATCH v3 42/57] tcg/arm: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 140 +-- 1 file changed, 18 insertions(+), 122

[PATCH v3 33/57] tcg/sparc64: Pass TCGType to tcg_out_qemu_{ld,st}

We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/sparc64/tcg-target.c.inc | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git

[PATCH v3 39/57] tcg/i386: Convert tcg_out_qemu_ld_slow_path

Use tcg_out_ld_helper_args and tcg_out_ld_helper_ret. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 71 +++ 1 file changed, 28 insertions(+), 43 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index

[PATCH v3 56/57] tcg/s390x: Use ALGFR in constructing softmmu host address

Rather than zero-extend the guest address into a register, use an add instruction which zero-extends the second input. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 8 +--- 1 file changed, 5 insertions(+), 3 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc

[PATCH v3 22/57] tcg/mips: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 404

[PATCH v3 41/57] tcg/aarch64: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 40 +++- 1 file changed, 16 insertions(+), 24 deletions(-) diff --git a/tcg/aarch64/tcg-target.c.inc

[PATCH v3 44/57] tcg/mips: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. This allows our local tcg_out_arg_* infrastructure to be removed. We are no longer filling the call or return branch delay slots, nor are we tail-calling for the store, but this seems a small price to pay.

[PATCH v3 35/57] tcg: Replace REG_P with arg_loc_reg_p

An inline function is safer than a macro, and REG_P was rather too generic. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 tcg/tcg.c | 16 +--- 2 files changed, 13 insertions(+), 7 deletions(-) diff --git

[PATCH v3 46/57] tcg/riscv: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 37 ++--- 1 file changed, 10 insertions(+), 27 deletions(-) diff --git

[PATCH v3 47/57] tcg/s390x: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 35 ++- 1 file changed, 10 insertions(+), 25 deletions(-) diff --git a/tcg/s390x/tcg-target.c.inc

[PATCH v3 51/57] tcg/mips: Simplify constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_TMP[0-3], not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, and have eliminated use of A0, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target-con-set.h | 13

[PATCH v3 11/57] tcg/i386: Use indexed addressing for softmmu fast path

Since tcg_out_{ld,st}_helper_args, the slow path no longer requires the address argument to be set up by the tlb load sequence. Use a plain load for the addend and indexed addressing with the original input address register. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 25

[PATCH v3 45/57] tcg/ppc: Convert tcg_out_qemu_{ld,st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 88 1 file changed, 26 insertions(+), 62 deletions(-) diff --git

Re: [RFC PATCH v3 03/44] target/loongarch: Add CHECK_SXE maccro for check LSX enable

On 4/20/23 09:06, Song Gao wrote: Signed-off-by: Song Gao --- target/loongarch/cpu.c | 2 ++ target/loongarch/cpu.h | 2 ++ target/loongarch/insn_trans/trans_lsx.c.inc | 11 +++ 3 files changed, 15 insertions(+) Reviewed-by: Richard

[PATCH v3 49/57] tcg/mips: Remove MO_BSWAP handling

While performing the load in the delay slot of the call to the common bswap helper function is cute, it is not worth the added complexity. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.h | 4 +- tcg/mips/tcg-target.c.inc | 284 ++ 2 files

[PATCH v3 57/57] tcg/s390x: Simplify constraints on qemu_ld/st

Adjust the softmmu tlb to use R0+R1, not any of the normally available registers. Since we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target-con-set.h | 2 -- tcg/s390x/tcg-target-con-str.h | 1 -

[PATCH v3 17/57] tcg/arm: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 351

[PATCH v3 53/57] tcg/ppc: Adjust constraints on qemu_ld/st

The softmmu tlb uses TCG_REG_{TMP1,TMP2,R0}, not any of the normally available registers. Now that we handle overlap betwen inputs and helper arguments, we can allow any allocatable reg. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target-con-set.h |

Re: [PATCH] hw/riscv/virt: Add a second UART for secure world

On 2023/4/24 10:42, LIU Zhiwei wrote: On 2023/4/24 9:01, Yong Li wrote: The virt machine can have two UARTs and the second UART can be used when host secure-mode support is enabled. Signed-off-by: Yong Li Cc: "Zhiwei Liu" Should  cc other Maintainers and Reviewers. Get the list by running

[PATCH v3 37/57] tcg: Widen helper_*_st[bw]_mmu val arguments

While the old type was correct in the ideal sense, some ABIs require the argument to be zero-extended. Using uint32_t for all such values is a decent compromise. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 10 +++--- accel/tcg/cputlb.c

[PATCH v3 16/57] tcg/arm: Introduce HostAddress

Collect the parts of the host address, and condition, into a struct. Merge tcg_out_qemu_*_{index,direct} and use it. Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 248 ++- 1 file changed, 115 insertions(+), 133 deletions(-) diff --git

[PATCH v3 07/57] tcg/i386: Introduce HostAddress

Collect the 4 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Reorg guest_base handling to use it. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 165 +- 1 file changed, 90 insertions(+), 75

[PATCH v3 52/57] tcg/ppc: Reorg tcg_out_tlb_read

Allocate TCG_REG_TMP2. Use R0, TMP1, TMP2 instead of any of the normally allocated registers for the tlb load. Reviewed-by: Daniel Henrique Barboza Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 84 1 file changed, 51 insertions(+), 33

[PATCH v3 23/57] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Reviewed-by: Daniel Henrique Barboza

[PATCH v3 10/57] tcg/i386: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 344

[PATCH v3 14/57] tcg/aarch64: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 313

[PATCH v3 13/57] tcg/aarch64: Introduce HostAddress

Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc | 86 +--- 1 file changed, 59 insertions(+), 27 deletions(-) diff --git

[PATCH v3 21/57] tcg/mips: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. There are several places where we already convert back from bool to type. Clean things up by using type throughout. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 186 +++--- 1 file

[PATCH v3 24/57] tcg/ppc: Introduce HostAddress

Collect the parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st} to use it. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 90 +--- 1 file changed, 47 insertions(+), 43 deletions(-) diff --git a/tcg/ppc/tcg-target.c.inc

[PATCH v3 50/57] tcg/mips: Reorg tlb load within prepare_host_addr

Compare the address vs the tlb entry with sign-extended values. This simplifies the page+alignment mask constant, and the generation of the last byte address for the misaligned test. Move the tlb addend load up, and the zero-extension down. This frees up a register, which allows us use TMP3 as

[PATCH v3 43/57] tcg/loongarch64: Convert tcg_out_qemu_{ld, st}_slow_path

Use tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 37 ++-- 1 file changed, 11 insertions(+), 26 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc

[PATCH v3 38/57] tcg: Add routines for calling slow-path helpers

Add tcg_out_ld_helper_args, tcg_out_ld_helper_ret, and tcg_out_st_helper_args. These and their subroutines use the existing knowledge of the host function call abi to load the function call arguments and return results. These will be used to simplify the backends in turn. Signed-off-by: Richard

[PATCH v3 25/57] tcg/ppc: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns HostAddress and TCGLabelQemuLdst structures. Signed-off-by: Richard Henderson --- tcg/ppc/tcg-target.c.inc | 377

[PATCH v3 12/57] tcg/aarch64: Rationalize args to tcg_out_qemu_{ld, st}

Rename the 'ext' parameter 'data_type' to make the use clearer; pass it to tcg_out_qemu_st as well to even out the interfaces. Rename the 'otype' local 'addr_type' to make the use clearer. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/aarch64/tcg-target.c.inc |

[PATCH v3 34/57] tcg: Move TCGLabelQemuLdst to tcg.c

Signed-off-by: Richard Henderson --- tcg/tcg.c | 13 + tcg/tcg-ldst.c.inc | 14 -- 2 files changed, 13 insertions(+), 14 deletions(-) diff --git a/tcg/tcg.c b/tcg/tcg.c index cfd3262a4a..6f5daaee5f 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -94,6 +94,19 @@

[PATCH v3 01/57] tcg/loongarch64: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, via ".w" instructions, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1

[PATCH v3 19/57] tcg/loongarch64: Introduce HostAddress

Collect the 2 parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 55 +--- 1 file changed, 30 insertions(+), 25 deletions(-) diff --git

[PATCH v3 30/57] tcg/s390x: Introduce HostAddress

Collect the 3 potential parts of the host address into a struct. Reorg tcg_out_qemu_{ld,st}_direct to use it. Signed-off-by: Richard Henderson --- tcg/s390x/tcg-target.c.inc | 109 - 1 file changed, 60 insertions(+), 49 deletions(-) diff --git

[PATCH v3 02/57] tcg/mips: Conditionalize tcg_out_exts_i32_i64

Since TCG_TYPE_I32 values are kept sign-extended in registers, we need not extend if the register matches. This is already relied upon by comparisons. Signed-off-by: Richard Henderson --- tcg/mips/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git

[PATCH v3 28/57] tcg/riscv: Introduce prepare_host_addr

Merge tcg_out_tlb_load, add_qemu_ldst_label, tcg_out_test_alignment, and some code that lived in both tcg_out_qemu_ld and tcg_out_qemu_st into one function that returns TCGReg and TCGLabelQemuLdst. Signed-off-by: Richard Henderson --- tcg/riscv/tcg-target.c.inc | 253

[PATCH v3 04/57] tcg: Introduce tcg_out_movext2

This is common code in most qemu_{ld,st} slow paths, moving two registers when there may be overlap between sources and destinations. At present, this is only used by 32-bit hosts for 64-bit data, but will shortly be used for more than that. Signed-off-by: Richard Henderson --- tcg/tcg.c

[PATCH v3 05/57] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is64 -- there are several places where we already convert back from bool to type. Clean things up by using type throughout. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson ---

[PATCH v3 15/57] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}

Interpret the variable argument placement in the caller. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the way through from tcg_out_op. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/arm/tcg-target.c.inc | 113

[PATCH v3 26/57] tcg/riscv: Require TCG_TARGET_REG_BITS == 64

The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64 not riscv32, this is not much of a restriction

[PATCH v3 08/57] tcg/i386: Drop r0+r1 local variables from tcg_out_tlb_load

Use TCG_REG_L[01] constants directly. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 32 1 file changed, 16 insertions(+), 16 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc b/tcg/i386/tcg-target.c.inc index b6750c364a..7a02f79f1b 100644

[PATCH v3 09/57] tcg/i386: Introduce tcg_out_testi

Split out a helper for choosing testb vs testl. Reviewed-by: Philippe Mathieu-Daudé Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 30 ++ 1 file changed, 18 insertions(+), 12 deletions(-) diff --git a/tcg/i386/tcg-target.c.inc

[PATCH v3 06/57] tcg/i386: Generalize multi-part load overlap test

Test for both base and index; use datahi as a temporary, overwritten by the final load. Always perform the loads in ascending order, so that any (user-only) fault sees the correct address. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 31 +++ 1

[PATCH v3 03/57] tcg/i386: Conditionalize tcg_out_extu_i32_i64

Since TCG_TYPE_I32 values are kept zero-extended in registers, via omission of the REXW bit, we need not extend if the register matches. This is already relied upon by qemu_{ld,st}. Signed-off-by: Richard Henderson --- tcg/i386/tcg-target.c.inc | 4 +++- 1 file changed, 3 insertions(+), 1

[PATCH v3 18/57] tcg/loongarch64: Rationalize args to tcg_out_qemu_{ld, st}

Interpret the variable argument placement in the caller. Shift some code around slightly to share more between softmmu and user-only. Signed-off-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 100 +-- 1 file changed, 42 insertions(+), 58 deletions(-)

[PATCH v3 00/57] tcg: Simplify calls to load/store helpers

v1: https://lore.kernel.org/qemu-devel/20230408024314.3357414-1-richard.hender...@linaro.org/ v2: https://lore.kernel.org/qemu-devel/20230411010512.5375-1-richard.hender...@linaro.org/ There are several changes to the load/store helpers coming, and making sure that those changes are properly

Re: [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs

On 4/23/23 19:55, Philippe Mathieu-Daudé wrote: On 11/4/23 03:04, Richard Henderson wrote: Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Signed-off-by: Richard

Re: [PATCH v4 0/2] Improve code coverage for ppc64

On 2023-04-21 14:29:38, Alex Bennée wrote: > > Kautuk Consul writes: > > > Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the > > boot_linux.py test-case due to which the code coverage for ppc > > decreased by around 2%. As per the discussion on > >

[PATCH v5] tests/avocado/tuxrun_baselines.py: improve code coverage for ppc64

Commit c0c8687ef0fd990db8db1655a8a6c5a5e35dd4bb disabled the boot_linux.py test-case due to which the code coverage for ppc decreased by around 2%. As per the discussion on https://lore.kernel.org/qemu-devel/87sfdpqcy4@linaro.org/ it was mentioned that the baseline test for ppc64 could be

Re: [PATCH v2 1/1] ui/sdl2: disable SDL_HINT_GRAB_KEYBOARD on Windows

Am 18.04.23 um 08:56 schrieb Volker Rümelin: Windows sends an extra left control key up/down input event for every right alt key up/down input event for keyboards with international layout. Since commit 830473455f ("ui/sdl2: fix handling of AltGr key on Windows") QEMU uses a Windows low level

Re: [PATCH] hw/riscv/virt: Add a second UART for secure world

On 2023/4/24 9:01, Yong Li wrote: The virt machine can have two UARTs and the second UART can be used when host secure-mode support is enabled. Signed-off-by: Yong Li Cc: "Zhiwei Liu" Should  cc other Maintainers and Reviewers. Get the list by running the script

[PATCH] hw/riscv/virt: Add a second UART for secure world

The virt machine can have two UARTs and the second UART can be used when host secure-mode support is enabled. Signed-off-by: Yong Li Cc: "Zhiwei Liu" --- hw/riscv/virt.c | 4 include/hw/riscv/virt.h | 2 ++ 2 files changed, 6 insertions(+) diff --git a/hw/riscv/virt.c

Re: [PATCH 11/13] hw/ide/sii3112: Reuse PCIIDEState::{cmd,data}_ops

On Sun, 23 Apr 2023, Bernhard Beschow wrote: Am 22. April 2023 21:10:14 UTC schrieb BALATON Zoltan : On Sat, 22 Apr 2023, Bernhard Beschow wrote: Allows to unexport pci_ide_{cmd,data}_le_ops and models TYPE_SII3112_PCI as a standard-compliant PCI IDE device. Signed-off-by: Bernhard Beschow

Re: [PATCH 05/13] hw/ide: Extract pci_ide_class_init()

On Sun, 23 Apr 2023, Bernhard Beschow wrote: Am 23. April 2023 17:41:33 UTC schrieb "Philippe Mathieu-Daudé" : On 22/4/23 17:07, Bernhard Beschow wrote: Resolves redundant code in every PCI IDE device model. --- include/hw/ide/pci.h | 1 - hw/ide/cmd646.c | 15 ---

Re: [PATCH 11/13] hw/ide/sii3112: Reuse PCIIDEState::{cmd,data}_ops

Am 22. April 2023 21:10:14 UTC schrieb BALATON Zoltan : >On Sat, 22 Apr 2023, Bernhard Beschow wrote: >> Allows to unexport pci_ide_{cmd,data}_le_ops and models TYPE_SII3112_PCI as a >> standard-compliant PCI IDE device. >> >> Signed-off-by: Bernhard Beschow >> --- >> include/hw/ide/pci.h |

Re: [PATCH 05/13] hw/ide: Extract pci_ide_class_init()

Am 23. April 2023 17:41:33 UTC schrieb "Philippe Mathieu-Daudé" : >On 22/4/23 17:07, Bernhard Beschow wrote: >> Resolves redundant code in every PCI IDE device model. >> --- >> include/hw/ide/pci.h | 1 - >> hw/ide/cmd646.c | 15 --- >> hw/ide/pci.c | 25

Re: [PATCH 13/13] hw/ide: Extract bmdma_clear_status()

Am 23. April 2023 10:40:50 UTC schrieb BALATON Zoltan : >On Sun, 23 Apr 2023, Bernhard Beschow wrote: >> Am 22. April 2023 21:26:00 UTC schrieb BALATON Zoltan : >>> On Sat, 22 Apr 2023, Bernhard Beschow wrote: Extract bmdma_clear_status() mirroring bmdma_cmd_writeb(). >>> >>> Is adding a

Re: [PATCH 06/13] hw/ide: Extract bmdma_init_ops()

Am 23. April 2023 17:43:22 UTC schrieb "Philippe Mathieu-Daudé" : >On 22/4/23 17:07, Bernhard Beschow wrote: >> There are three private copies of bmdma_setup_bar() with small adaptions. >> Consolidate them into one public implementation. >> >> While at it rename the function to

Re: [PATCH 7/8] cpu: Replace target_ulong with vaddr in tb_invalidate_phys_addr()

On 4/23/23 20:35, Alex Bennée wrote: Richard Henderson writes: On 4/23/23 18:29, Philippe Mathieu-Daudé wrote: On 23/4/23 11:14, Richard Henderson wrote: On 4/20/23 22:28, Anton Johansson wrote: -void tb_invalidate_phys_addr(target_ulong addr) +void tb_invalidate_phys_addr(vaddr addr)

Re: [RFC PATCH v3 01/44] target/loongarch: Add LSX data type VReg

On 4/20/23 09:06, Song Gao wrote: diff --git a/target/loongarch/machine.c b/target/loongarch/machine.c index b1e523ea72..a67b735a32 100644 --- a/target/loongarch/machine.c +++ b/target/loongarch/machine.c @@ -10,6 +10,112 @@ #include "migration/cpu.h" #include "internals.h" +/* FPU state

Re: [PATCH 7/8] cpu: Replace target_ulong with vaddr in tb_invalidate_phys_addr()

Richard Henderson writes: > On 4/23/23 18:29, Philippe Mathieu-Daudé wrote: >> On 23/4/23 11:14, Richard Henderson wrote: >>> On 4/20/23 22:28, Anton Johansson wrote: -void tb_invalidate_phys_addr(target_ulong addr) +void tb_invalidate_phys_addr(vaddr addr) >>> >>> Hmm.  This isn't a

Re: [PATCH v2 25/54] tcg/ppc: Rationalize args to tcg_out_qemu_{ld,st}

On 11/4/23 03:04, Richard Henderson wrote: Interpret the variable argument placement in the caller. Mark the argument register const, because they must be passed to add_qemu_ldst_label unmodified. This requires a bit of local variable renaming, because addrlo was being modified. Pass data_type

Re: [PATCH v2 28/54] tcg/riscv: Rationalize args to tcg_out_qemu_{ld,st}

On 11/4/23 03:04, Richard Henderson wrote: Interpret the variable argument placement in the caller. Mark the argument registers const, because they must be passed to add_qemu_ldst_label unmodified. Pass data_type instead of is64 -- there are several places where we already convert back from

Re: [PATCH v2 32/54] tcg: Replace REG_P with arg_loc_reg_p

On 11/4/23 03:04, Richard Henderson wrote: An inline function is safer than a macro, and REG_P was rather too generic. Signed-off-by: Richard Henderson --- tcg/tcg-internal.h | 4 tcg/tcg.c | 16 +--- 2 files changed, 13 insertions(+), 7 deletions(-)

Re: [PATCH v2 27/54] tcg/riscv: Require TCG_TARGET_REG_BITS == 64

On 11/4/23 03:04, Richard Henderson wrote: The port currently does not support "oversize" guests, which means riscv32 can only target 32-bit guests. We will soon be building TCG once for all guests. This implies that we can only support riscv64. Since all Linux distributions target riscv64

Re: [PATCH v2 22/54] tcg/arm: Rationalize args to tcg_out_qemu_{ld,st}

On 11/4/23 03:04, Richard Henderson wrote: Interpret the variable argument placement in the caller. Mark the argument registers const, because they must be passed to add_qemu_ldst_label unmodified. Pass data_type instead of is_64. We need to set this in TCGLabelQemuLdst, so plumb this all the

Re: [PATCH v2 20/54] tcg/i386: Rationalize args to tcg_out_qemu_{ld,st}

On 11/4/23 03:04, Richard Henderson wrote: Interpret the variable argument placement in the caller. Mark the argument register const, because they must be passed to add_qemu_ldst_label unmodified. Pass data_type instead of is64 -- there are several places where we already convert back from bool

Re: [PATCH v2 33/54] tcg: Introduce arg_slot_stk_ofs

On 11/4/23 03:04, Richard Henderson wrote: Unify all computation of argument stack offset in one function. This requires that we adjust ref_slot to be in the same units, by adding max_reg_slots during init_call_layout. Signed-off-by: Richard Henderson --- tcg/tcg.c | 29

Re: [PATCH v2 34/54] tcg: Widen helper_*_st[bw]_mmu val arguments

On 11/4/23 03:04, Richard Henderson wrote: While the old type was correct in the ideal sense, some ABIs require the argument to be zero-extended. Using uint32_t for all such values is a decent compromise. Signed-off-by: Richard Henderson --- include/tcg/tcg-ldst.h | 10 +++---

Re: [PATCH 7/8] cpu: Replace target_ulong with vaddr in tb_invalidate_phys_addr()

On 4/23/23 18:29, Philippe Mathieu-Daudé wrote: On 23/4/23 11:14, Richard Henderson wrote: On 4/20/23 22:28, Anton Johansson wrote: -void tb_invalidate_phys_addr(target_ulong addr) +void tb_invalidate_phys_addr(vaddr addr) Hmm.  This isn't a virtual address, so 'vaddr' isn't right. I'm sure

Re: get_relocated_path: the configured paths are not looked for?

On 2023/04/24 3:37, Michael Tokarev wrote: 23.04.2023 21:33, Michael Tokarev пишет: $ cd /tmp; printf '#include \nint main(){puts("Hello!");return 0;}' > hello.c; cp /usr/bin/gcc .; ./gcc hello.c; ./a.out ; ./gcc --version; ls -l gcc; cd /tmp Hello!

Re: get_relocated_path: the configured paths are not looked for?

23.04.2023 21:33, Michael Tokarev пишет: $ cd /tmp; printf '#include \nint main(){puts("Hello!");return 0;}' > hello.c; cp /usr/bin/gcc .; ./gcc hello.c; ./a.out ; ./gcc --version; ls -l gcc; cd /tmp Hello! execve("/tmp/../lib/gcc/x86_64-linux-gnu/12/cc1", [...]) Since this is merged-usr

Re: get_relocated_path: the configured paths are not looked for?

23.04.2023 21:24, Akihiko Odaki wrote: The output ends with: gcc: fatal error: cannot execute 'cc1': execvp: No such file or directory compilation terminated. $ cd /tmp; printf '#include \nint main(){puts("Hello!");return 0;}' > hello.c; cp /usr/bin/gcc .; ./gcc hello.c; ./a.out ; ./gcc

Re: get_relocated_path: the configured paths are not looked for?

On 2023/04/24 3:10, Michael Tokarev wrote: 23.04.2023 20:39, Akihiko Odaki пишет: On 2023/04/23 22:22, Michael Tokarev wrote: 23.04.2023 14:47, Akihiko Odaki пишет: https://salsa.debian.org/qemu-team/qemu/-/commit/e017f53a8550d0bcaaca81c6dacac8ec34295cf0 fwiw. I seriously think you better

Re: get_relocated_path: the configured paths are not looked for?

23.04.2023 20:39, Akihiko Odaki пишет: On 2023/04/23 22:22, Michael Tokarev wrote: 23.04.2023 14:47, Akihiko Odaki пишет: https://salsa.debian.org/qemu-team/qemu/-/commit/e017f53a8550d0bcaaca81c6dacac8ec34295cf0 fwiw. I seriously think you better consult GCC and other package maintainers to

Re: [PATCH 07/13] hw/ide: Extract pci_ide_{cmd,data}_le_ops initialization into base class constructor

On 22/4/23 17:07, Bernhard Beschow wrote: There is redundant code in cmd646 and via which can be extracted into the base class. In case of piix and sii3112 this is currently unneccessary but shouldn't interfere since the memory regions aren't mapped by those devices. In few commits later this

Re: [PATCH 06/13] hw/ide: Extract bmdma_init_ops()

On 22/4/23 17:07, Bernhard Beschow wrote: There are three private copies of bmdma_setup_bar() with small adaptions. Consolidate them into one public implementation. While at it rename the function to bmdma_init_ops() to reflect that the memory regions being initialized represent BMDMA

Re: [PATCH 05/13] hw/ide: Extract pci_ide_class_init()

On 22/4/23 17:07, Bernhard Beschow wrote: Resolves redundant code in every PCI IDE device model. --- include/hw/ide/pci.h | 1 - hw/ide/cmd646.c | 15 --- hw/ide/pci.c | 25 - hw/ide/piix.c| 19 --- hw/ide/sii3112.c

Re: get_relocated_path: the configured paths are not looked for?

On 2023/04/23 22:22, Michael Tokarev wrote: 23.04.2023 14:47, Akihiko Odaki пишет: https://salsa.debian.org/qemu-team/qemu/-/commit/e017f53a8550d0bcaaca81c6dacac8ec34295cf0 fwiw. I seriously think you better consult GCC and other package maintainers to have consensus on handling this kind of

Re: [PATCH 04/13] hw/ide: Extract IDEBus assignment into bmdma_init()

On 22/4/23 17:07, Bernhard Beschow wrote: Every invocation of bmdma_init() is followed by `d->bmdma[i].bus = >bus[i]`. Resolve this redundancy by extracting it into bmdma_init(). Signed-off-by: Bernhard Beschow --- hw/ide/cmd646.c | 1 - hw/ide/pci.c | 1 + hw/ide/piix.c| 1 -

Re: [PATCH 7/8] cpu: Replace target_ulong with vaddr in tb_invalidate_phys_addr()

On 23/4/23 11:14, Richard Henderson wrote: On 4/20/23 22:28, Anton Johansson wrote: -void tb_invalidate_phys_addr(target_ulong addr) +void tb_invalidate_phys_addr(vaddr addr) Hmm.  This isn't a virtual address, so 'vaddr' isn't right. I'm sure we have something more appropriate.

Re: [PATCH v2 0/2] linux-user: Fix mincore() with PROT_NONE

On 22/4/23 12:03, Thomas Weißschuh wrote: The kernel does not require PROT_READ for addresses passed to mincore. v1: https://lore.kernel.org/qemu-devel/20230416195103.607948-1-tho...@t-8ch.de/ v1 -> v2: * Introduce symbolic flag VERIFY_NONE instead of hardcoding "0" Thomas Weißschuh (2):

[PATCH v5 7/7] hw/cxl/events: Add injection of Memory Module Events

These events include a copy of the device health information at the time of the event. Actually using the emulated device health would require a lot of controls to manipulate that state. Given the aim of this injection code is to just test the flows when events occur, inject the contents of the

[PATCH v5 6/7] hw/cxl/events: Add injection of DRAM events

Defined in CXL r3.0 8.2.9.2.1.2 DRAM Event Record, this event provides information related to DRAM devices. Example injection command in QMP: { "execute": "cxl-inject-dram-event", "arguments": { "path": "/machine/peripheral/cxl-mem0", "log": "informational", "flags":

[PATCH v5 5/7] hw/cxl/events: Add injection of General Media Events

From: Ira Weiny To facilitate testing provide a QMP command to inject a general media event. The event can be added to the log specified. Signed-off-by: Ira Weiny Signed-off-by: Jonathan Cameron --- v5: * Rebase * Update QMP Since entries to 8.1 --- hw/mem/cxl_type3.c | 111

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