On Tue, 20 Jun 2023 at 17:28, Richard Henderson
wrote:
>
> On 6/20/23 17:57, Peter Maydell wrote:
> > On Tue, 20 Jun 2023 at 13:46, Richard Henderson
> > wrote:
> >>
> >> Changes for v5:
> >>* Enabled only by cpu property x-rme=on, not -cpu max.
> >>* Rebase vs SecEL2 fixes, now in
This will be of small comfort to sparc64, because both
sun4u and sun4v board models force max_cpus = 1.
But it does enable actual smp for sparc32 sun4m.
Signed-off-by: Richard Henderson
---
configs/targets/sparc-softmmu.mak | 1 +
configs/targets/sparc64-softmmu.mak | 1 +
2 files changed, 2
Always use TSO, per the Oracle 2015 manual.
This is slightly less restrictive than the TCG_MO_ALL default,
and happens to match the i386 model, which will eliminate a few
extra barriers on that host.
Signed-off-by: Richard Henderson
---
target/sparc/cpu.h | 23 +++
1 file
With the addition of TCG_GUEST_DEFAULT_MO, there's nothing in
the cpu emulation preventing this from working. There is some
board model work to be done for sparc64, where max_cpus = 1.
r~
Richard Henderson (2):
target/sparc: Set TCG_GUEST_DEFAULT_MO
configs: Enable MTTCG for sparc,
On 6/20/23 17:57, Peter Maydell wrote:
On Tue, 20 Jun 2023 at 13:46, Richard Henderson
wrote:
Changes for v5:
* Enabled only by cpu property x-rme=on, not -cpu max.
* Rebase vs SecEL2 fixes, now in master.
This doesn't have the magic RMM memory, which previous patch sets
included for
On Tue, Jun 20, 2023 at 6:23 PM Richard Henderson
wrote:
>
> On 6/20/23 17:16, Paolo Bonzini wrote:
> > TCG reports the SEP feature (SYSENTER/SYSEXIT) in user mode emulation,
> > but does not plumb it into the linux-user run loop. Split the helper into
> > system emulation and user-mode
On 6/20/23 18:20, Peter Maydell wrote:
The xkb official name for the Arabic keyboard layout is 'ara'.
However xkb has for at least the past 15 years also permitted it to
be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
synoynm was removed, which breaks compilation of QEMU:
On 6/20/23 17:16, Paolo Bonzini wrote:
TCG implements RDSEED, and in fact uses qcrypto_random_bytes which is
secure enough to match hardware behavior. Expose it to guests.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 5 ++---
1 file changed, 2
On 6/20/23 17:16, Paolo Bonzini wrote:
RDPID corresponds to a RDMSR(TSC_AUX); however, it is unprivileged
so for user-mode emulation we must provide the value that the kernel
places in the MSR. For Linux, it is a combination of the current CPU
and the current NUMA node, both of which can be
On 6/20/23 17:16, Paolo Bonzini wrote:
TCG reports the SEP feature (SYSENTER/SYSEXIT) in user mode emulation,
but does not plumb it into the linux-user run loop. Split the helper into
system emulation and user-mode emulation cases and implement the latter.
SYSENTER does not have the best
The xkb official name for the Arabic keyboard layout is 'ara'.
However xkb has for at least the past 15 years also permitted it to
be named via the legacy synonym 'ar'. In xkeyboard-config 2.39 this
synoynm was removed, which breaks compilation of QEMU:
FAILED: pc-bios/keymaps/ar
On Tue, 20 Jun 2023 at 16:55, Richard Henderson
wrote:
>
> On 6/20/23 17:37, Alex Bennée wrote:
> > ar maybe? it only got flagged in clang-system once fedora was updated (I
> > assume with better sanitizers):
> >
> >[2773/3696] Generating pc-bios/keymaps/ar with a custom command
> >
On 6/20/23 17:16, Paolo Bonzini wrote:
@@ -211,6 +211,9 @@ void cpu_loop(CPUX86State *env)
switch(trapnr) {
case 0x80:
+#ifdef TARGET_ABI32
+case EXCP_SYSCALL:
+#endif
/* linux syscall from int $0x80 */
ABI32 includes x32.
I think you want TARGET_I386.
From: Lakshmi Bai Raja Subramanian
Signed-off-by: Lakshmi Bai Raja Subramanian
---
hw/riscv/virt.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 95708d890e..c348529ac0 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1244,7
On Tue, 20 Jun 2023 at 13:46, Richard Henderson
wrote:
>
> Changes for v5:
> * Enabled only by cpu property x-rme=on, not -cpu max.
> * Rebase vs SecEL2 fixes, now in master.
>
> This doesn't have the magic RMM memory, which previous patch sets
> included for booting Huawei's forked TF-A.
On 6/20/23 17:16, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 6/20/23 17:16, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4
target/i386/tcg/translate.c | 5 -
2 files changed, 8 insertions(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 6/20/23 17:37, Alex Bennée wrote:
ar maybe? it only got flagged in clang-system once fedora was updated (I
assume with better sanitizers):
[2773/3696] Generating pc-bios/keymaps/ar with a custom command
FAILED: pc-bios/keymaps/ar
/builds/stsquad/qemu/build/qemu-keymap -f
On Fri, Jun 09, 2023 at 12:49:17AM +0200, Juan Quintela wrote:
> We called migrate_qmp() in lot of places. And there are tricks like
> changing tcp address with the right port.
>
> Only two callers remaining:
> - postcopy resume: It needs to play with the qmp.
> - baddest: We want to do a
On Mon, Jun 19, 2023 at 7:15 PM Alex Bennée wrote:
>
> Using QOM correctly is increasingly important to maintaining a modern
> code base. However the current documentation skips some important
> concepts before launching into a simple example. Lets:
>
> - at least mention properties
> -
On 6/20/23 17:41, Philippe Mathieu-Daudé wrote:
On 19/6/23 16:23, Richard Henderson wrote:
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling
On Tue, 20 Jun 2023 at 16:38, Alex Bennée wrote:
>
>
> Peter Maydell writes:
>
> > On Tue, 20 Jun 2023 at 16:04, Alex Bennée wrote:
> >>
> >> We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
> >> as an overly wide shift attempt.
> >>
> >> Signed-off-by: Alex Bennée
> >>
On 19/6/23 16:23, Richard Henderson wrote:
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Cc: Alistair Francis
Cc: Edgar E. Iglesias
From: Marc-André Lureau
Rename build directory to "build", like most other CI builds.
Signed-off-by: Marc-André Lureau
---
.gitlab-ci.d/windows.yml | 13 +
1 file changed, 9 insertions(+), 4 deletions(-)
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index
From: Marc-André Lureau
Signed-off-by: Marc-André Lureau
---
.gitlab-ci.d/windows.yml | 2 ++
1 file changed, 2 insertions(+)
diff --git a/.gitlab-ci.d/windows.yml b/.gitlab-ci.d/windows.yml
index d45794463a..f889a468b5 100644
--- a/.gitlab-ci.d/windows.yml
+++ b/.gitlab-ci.d/windows.yml
@@
Peter Maydell writes:
> On Tue, 20 Jun 2023 at 16:04, Alex Bennée wrote:
>>
>> We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
>> as an overly wide shift attempt.
>>
>> Signed-off-by: Alex Bennée
>> ---
>> qemu-keymap.c | 24
>> 1 file
From: Marc-André Lureau
Hi,
Submitting again this small series from last year.
Marc-André Lureau (2):
gitlab-ci: grab msys2 meson-logs as artifacts
gitlab-ci: add msys2 meson test to junit report
.gitlab-ci.d/windows.yml | 15 +++
1 file changed, 11 insertions(+), 4
On Mon, 19 Jun 2023 at 18:14, Alex Bennée wrote:
>
> Give an overview of the most useful bits of the devel documentation to
> read depending on what the developer wants to do.
>
> Signed-off-by: Alex Bennée
Reviewed-by: Peter Maydell
thanks
-- PMM
On Fri, Jun 09, 2023 at 12:49:15AM +0200, Juan Quintela wrote:
> So make it return void instead and adjust all callers.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jun 09, 2023 at 12:49:16AM +0200, Juan Quintela wrote:
> So make it return void.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jun 09, 2023 at 12:49:14AM +0200, Juan Quintela wrote:
> Makes things easier and cleaner.
>
> Signed-off-by: Juan Quintela
> ---
> tests/qtest/migration-test.c | 20
> 1 file changed, 12 insertions(+), 8 deletions(-)
>
> diff --git a/tests/qtest/migration-test.c
On Fri, Jun 09, 2023 at 12:49:13AM +0200, Juan Quintela wrote:
> It failed on aarch64 tcg, lets see if that is still the case.
>
> Signed-off-by: Juan Quintela
According to the history:
https://lore.kernel.org/all/20190305180635.GA3803@work-vm/
It's never enabled, and not sure whether Yury
On 20/6/23 16:48, Greg Kurz wrote:
On Tue, 20 Jun 2023 09:55:49 +0200
Claudio Fontana wrote:
On 6/20/23 09:48, Philippe Mathieu-Daudé wrote:
Although the PPC target only supports the TCG and KVM
accelerators, QEMU supports more. We can no assume that
'!kvm == tcg', so test for the correct
Commit 7f0bdfb5bfc2 ("target/riscv/cpu.c: remove cfg setup from
riscv_cpu_init()") removed code that was enabling mmu, pmp, ext_ifencei
and ext_icsr from riscv_cpu_init(), the init() function of
TYPE_RISCV_CPU, parent type of all RISC-V CPUss. This was done to force
CPUs to explictly enable all
On Fri, 2023-06-02 at 23:04 +0800, Weiwei Li wrote:
>
> On 2023/6/2 20:16, Rob Bradford wrote:
> > This commit adds support for the the amocas.{w,d,q} instructions
> > behind
> > a new property to enable that instruction.
> >
> > Signed-off-by: Rob Bradford
> > ---
>
> I also implemented an
On Fri, Jun 09, 2023 at 12:49:12AM +0200, Juan Quintela wrote:
> It missed this treatment:
>
> commit 11f1a4ce14803f15d59cff42a4cfb7ac50d36bd0
> Author: Juan Quintela
> Date: Mon Nov 29 18:57:51 2021 +0100
>
> migration-test: Check for shared memory like for everything else
>
>
On Fri, Jun 09, 2023 at 12:49:09AM +0200, Juan Quintela wrote:
> So just make it a global variable.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 9aec7ec8288..c58f5f24ab3 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
RDPID corresponds to a RDMSR(TSC_AUX); however, it is unprivileged
so for user-mode emulation we must provide the value that the kernel
places in the MSR. For Linux, it is a combination of the current CPU
and the current NUMA node, both of which can be retrieved with getcpu(2).
For BSD, just
TCG implements RDSEED, and in fact uses qcrypto_random_bytes which is
secure enough to match hardware behavior. Expose it to guests.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
On Tue, 20 Jun 2023 at 16:04, Alex Bennée wrote:
>
> We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
> as an overly wide shift attempt.
>
> Signed-off-by: Alex Bennée
> ---
> qemu-keymap.c | 24
> 1 file changed, 16 insertions(+), 8 deletions(-)
Due to a typo or perhaps a brain fart, the INVD vmexit was never generated.
Fix it (but not that fixing just the typo would break both INVD and WBINVD,
due to a case of two wrongs making a right).
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2
WBNOINVD is the same as INVD or WBINVD as far as TCG is concerned,
since there is no cache in TCG and therefore no invalidation side effect
in WBNOINVD.
With respect to SVM emulation, processors that do not support WBNOINVD
will ignore the prefix and treat it as WBINVD, while those that support
On Fri, Jun 09, 2023 at 12:49:11AM +0200, Juan Quintela wrote:
> So no need to assert we are in x86_64.
> Once there, refactor the function to remove useless variables.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
XSAVEERPTR is actually a fix for an errata; TCG does not have the issue.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index fc4246223d4..bce0cb73e85
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c | 4
target/i386/tcg/translate.c | 5 -
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 695e01582bf..978d24b5ec7 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
On Fri, Jun 09, 2023 at 12:49:10AM +0200, Juan Quintela wrote:
> The bootsector code is read only from the guest (otherwise we are
> going to have problems with it being read from both source and
> destination).
>
> Create a single copy for all the tests.
>
> Signed-off-by: Juan Quintela
TCG reports the SEP feature (SYSENTER/SYSEXIT) in user mode emulation,
but does not plumb it into the linux-user run loop. Split the helper into
system emulation and user-mode emulation cases and implement the latter.
SYSENTER does not have the best design for a kernel-mode entry
instruction,
The AMD prefetch(w) instructions have not been deprecated together with the rest
of 3DNow!, and in fact are even supported by newer Intel processor. Mark them
as supported by TCG, as it supports all of 3DNow!.
Reviewed-by: Richard Henderson
Signed-off-by: Paolo Bonzini
---
target/i386/cpu.c |
TCG is not reporting a few features that are actually already implemented,
or that are easy to implement. Add them.
Paolo
v1->v2:
- fix WBNOINVD vmexit
- correctly implement 32-bit SYSCALL and SYSENTER
- do not include linux-user/ from target/
Paolo Bonzini (10):
target/i386: fix INVD vmexit
TCG supports both 32-bit and 64-bit SYSCALL, but the linux-user
code only exposes it for 64-bit. The ABI is the same as "int $80",
so expose it even for 32-bit emulators, where it can be used if the
vendor is specified as AMD.
Signed-off-by: Paolo Bonzini
---
linux-user/i386/cpu_loop.c
On Fri, Jun 09, 2023 at 12:49:08AM +0200, Juan Quintela wrote:
> So arch_dirty_ring option becomes one option like the others.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
Stefan Hajnoczi 于2023年6月20日周二 22:48写道：
>
> On Mon, Jun 19, 2023 at 10:50:31PM +0800, Sam Li wrote:
> > Stefan Hajnoczi 于2023年6月19日周一 22:42写道：
> > >
> > > On Mon, Jun 19, 2023 at 06:32:52PM +0800, Sam Li wrote:
> > > > Stefan Hajnoczi 于2023年6月19日周一 18:10写道：
> > > > > On Mon, Jun 05, 2023 at
On Fri, Jun 09, 2023 at 12:49:07AM +0200, Juan Quintela wrote:
> And it needs to be in both source and target, so put it on arch_opts.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jun 09, 2023 at 12:49:06AM +0200, Juan Quintela wrote:
> This will contain the options needed for both source and target.
>
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jun 09, 2023 at 12:49:05AM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
Reviewed-by: Peter Xu
--
Peter Xu
On Fri, Jun 09, 2023 at 12:49:04AM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> tests/qtest/migration-test.c | 9 -
> 1 file changed, 4 insertions(+), 5 deletions(-)
>
> diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> index
We can return XKB_MOD_INVALID which rightly gets flagged by sanitisers
as an overly wide shift attempt.
Signed-off-by: Alex Bennée
---
qemu-keymap.c | 24
1 file changed, 16 insertions(+), 8 deletions(-)
diff --git a/qemu-keymap.c b/qemu-keymap.c
index
On Fri, Jun 09, 2023 at 12:49:03AM +0200, Juan Quintela wrote:
> Signed-off-by: Juan Quintela
> ---
> tests/qtest/migration-test.c | 10 --
> 1 file changed, 4 insertions(+), 6 deletions(-)
>
> diff --git a/tests/qtest/migration-test.c b/tests/qtest/migration-test.c
> index
On 6/20/23 16:31, Frederic Barrat wrote:
On 20/06/2023 13:20, Cédric Le Goater wrote:
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports,
On Fri, Jun 09, 2023 at 12:49:02AM +0200, Juan Quintela wrote:
> It makes no sense that we don't have the same configuration on both sides.
I hope Laurent can see this one out of 40s.
Makes sense to me, but does it mean that the devices are not matching
before on ppc? Confused how did it work
On Mon, Jun 19, 2023 at 10:50:31PM +0800, Sam Li wrote:
> Stefan Hajnoczi 于2023年6月19日周一 22:42写道：
> >
> > On Mon, Jun 19, 2023 at 06:32:52PM +0800, Sam Li wrote:
> > > Stefan Hajnoczi 于2023年6月19日周一 18:10写道：
> > > > On Mon, Jun 05, 2023 at 06:41:06PM +0800, Sam Li wrote:
> > > > > diff --git
On Tue, 20 Jun 2023 09:55:49 +0200
Claudio Fontana wrote:
> On 6/20/23 09:48, Philippe Mathieu-Daudé wrote:
> > Although the PPC target only supports the TCG and KVM
> > accelerators, QEMU supports more. We can no assume that
> > '!kvm == tcg', so test for the correct accelerator. This
> > also
On 19/6/23 16:23, Richard Henderson wrote:
The microblaze architecture does not reorder instructions.
While there is an MBAR wait-for-data-access instruction,
this concerns synchronizing with DMA.
This should have been defined when enabling MTTCG.
Cc: Alistair Francis
Cc: Edgar E. Iglesias
On Tue, Jun 20, 2023 at 01:10:55PM +0100, Daniel P. Berrangé wrote:
> In some cases it is worth having a convenience option for user friendliness.
>
> In this case, however, users are already needing to use QMP/HMP on the
> source side to set migration parameters. I think it is reasonable to say
Hello Shameer,
On 6/13/23 16:09, Shameer Kolothum wrote:
When vfio_enable_vectors() returns with less than requested nr_vectors
we retry with what kernel reported back. But the retry path doesn't
call vfio_prepare_kvm_msi_virq_batch() and this results in,
qemu-system-aarch64: vfio: Error:
On Wed, Jun 14, 2023 at 10:56:22PM +, Alexander Graf wrote:
> diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c
> index 39e7f23fab..76b85bb3cb 100644
> --- a/hw/block/virtio-blk.c
> +++ b/hw/block/virtio-blk.c
> @@ -1120,6 +1120,20 @@ static int
On Mon, Jun 19, 2023 at 9:40 AM Richard Henderson
wrote:
> What is our minimum glibc version? This requires 2.29.
Ok, I'll add a test to meson.build.
> Also, not especially fond of the placement. target/ including linux-user/
> header isn't
> nice. Might as well just place these 3 lines in
On 20/06/2023 13:20, Cédric Le Goater wrote:
On 6/20/23 12:45, Peter Maydell wrote:
On Sat, 10 Jun 2023 at 14:31, Daniel Henrique Barboza
wrote:
From: Frederic Barrat
The Thread Interrupt Management Area (TIMA) can be accessed through 4
ports, targeted by the address. The base address
This change is cosmetic. A comment is added explaining why we need to check for
the availability of function 0 when we hotplug a device.
CC: m...@redhat.com
Signed-off-by: Ani Sinha
---
hw/pci/pci.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index
On Tue, 20 Jun 2023, Nicholas Piggin wrote:
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
On 19/6/23 16:23, Richard Henderson wrote:
Bring the helpers into line with the rest of tcg in respecting
guest memory ordering.
Signed-off-by: Richard Henderson
---
accel/tcg/internal.h | 34 ++
accel/tcg/cputlb.c| 10 ++
accel/tcg/user-exec.c
On Mon, Jun 19, 2023 at 06:14:34PM +0100, Alex Bennée wrote:
> Mention that QOM-ified devices already have support for registering
> the description.
>
> Signed-off-by: Alex Bennée
Acked-by: Peter Xu
--
Peter Xu
On 6/20/23 15:52, Peter Maydell wrote:
On Tue, 20 Jun 2023 at 13:46, Richard Henderson
wrote:
Add an x-rme cpu property to enable FEAT_RME.
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
for testing various possible configurations.
Looks OK to me, but I think we should document these
On Tue, 20 Jun 2023, Michael S. Tsirkin wrote:
On Tue, Jun 20, 2023 at 02:50:55AM +0200, BALATON Zoltan wrote:
On Thu, 8 Jun 2023, BALATON Zoltan wrote:
On Thu, 8 Jun 2023, Michael S. Tsirkin wrote:
On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote:
On 07/06/2023 21:01,
On Tue, 20 Jun 2023 at 13:46, Richard Henderson
wrote:
>
> Add an x-rme cpu property to enable FEAT_RME.
> Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
> for testing various possible configurations.
Looks OK to me, but I think we should document these
(including that they're experimental
On 6/20/23 15:46, Richard Henderson wrote:
Brown bag time: store instead of load results in uninitialized temp.
Reported-by: Mark Rutland
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld,
st}r")
Tested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
Brown bag time: store instead of load results in uninitialized temp.
Reported-by: Mark Rutland
Fixes: e6dd5e782be ("target/arm: Use tcg_gen_qemu_{ld, st}_i128 in gen_sve_{ld,
st}r")
Tested-by: Alex Bennée
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-sve.c | 2 +-
1 file
On 20.06.23 15:06, Michael S. Tsirkin wrote:
On Tue, Jun 20, 2023 at 03:03:54PM +0200, David Hildenbrand wrote:
To achieve desired "x-ignore-shared" functionality, we should not
discard all RAM when realizing the device and not mess with
preallocation/postcopy when loading device state. In
On Thu, Jun 08, 2023 at 05:20:37PM +0200, BALATON Zoltan wrote:
> On Thu, 8 Jun 2023, Michael S. Tsirkin wrote:
> > On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote:
> > > On 07/06/2023 21:01, BALATON Zoltan wrote:
> > >
> > > > On pegasos2 which has ACPI as part of VT8231 south
Ping.
On 5/24/23 07:46, Richard Henderson wrote:
The beginning of the structure, with pretaddr, should be just below
16-byte alignment. Disconnect fpstate from sigframe, just like the
kernel does.
Signed-off-by: Richard Henderson
---
linux-user/i386/signal.c | 104
On Tue, Jun 20, 2023 at 02:50:55AM +0200, BALATON Zoltan wrote:
> On Thu, 8 Jun 2023, BALATON Zoltan wrote:
> > On Thu, 8 Jun 2023, Michael S. Tsirkin wrote:
> > > On Thu, Jun 08, 2023 at 12:37:08PM +0100, Mark Cave-Ayland wrote:
> > > > On 07/06/2023 21:01, BALATON Zoltan wrote:
> > > >
> > > >
The CTRL register is able to write the bit in the RUN field, which gets
reflected into the TS field which is read-only and contains the state of
the RUN field for all threads in the core.
TCG does not implement SMT, so the correct implementation just requires
mirroring the RUN bit into the first
System call interrupts in ISA v3.1 CPUs add a LEV indication in SRR1
that corresponds with the LEV field of the instruction that caused the
interrupt.
Signed-off-by: Nicholas Piggin
---
This is unchanged, just taken out of the bigger series since it is
independent.
Thanks,
Nick
The hypervisor emulation assistance interrupt modifies HEIR to
contain the value of the instruction which caused the exception.
Only TCG raises HEAI interrupts so this can be made TCG-only.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
target/ppc/cpu_init.c| 23
Rather than always performing partition scope page table translation
with access type of 0 (MMU_DATA_LOAD), pass through the processor
access type which first initiated the translation sequence. Process-
scoped page table loads are then set to MMU_DATA_LOAD access type in
the xlate function.
This
Because they got more complexities than I first thought, these patches
are broken out from the bigger series here:
https://lists.gnu.org/archive/html/qemu-ppc/2023-05/msg00425.html
Since then I fixed the --disable-tcg compile bug reported by Anushree
hopefully. Also added a workaround for KVM so
powerpc ifetch endianness depends on MSR[LE] so it has to byteswap
after cpu_ldl_code(). This corrects DSISR bits in alignment
interrupts when running in little endian mode.
Reviewed-by: Fabiano Rosas
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 22 +-
1
ISA v3.1 introduced prefix instructions. Among the changes, various
synchronous interrupts report whether they were caused by a prefix
instruction in (H)SRR1.
The case of instruction fetch that causes an HDSI due to access of a
process-scoped table faulting on the partition scoped translation is
On Tue, Jun 20, 2023 at 03:03:54PM +0200, David Hildenbrand wrote:
> To achieve desired "x-ignore-shared" functionality, we should not
> discard all RAM when realizing the device and not mess with
> preallocation/postcopy when loading device state. In essence, we should
> not touch RAM content.
>
ram_block_discard_range() cannot possibly do the right thing in
MAP_PRIVATE file mappings in the general case.
To achieve the documented semantics, we also have to punch a hole into
the file, possibly messing with other MAP_PRIVATE/MAP_SHARED mappings
of such a file.
For example, using VM
Already when starting QEMU we perform one system reset that ends up
triggering virtio_mem_unplug_all() with no actual memory plugged yet.
That, in turn will trigger ram_block_discard_range() and perform some
other actions that are not required in that case.
Let's optimize virtio_mem_unplug_all()
To achieve desired "x-ignore-shared" functionality, we should not
discard all RAM when realizing the device and not mess with
preallocation/postcopy when loading device state. In essence, we should
not touch RAM content.
As "x-ignore-shared" gets set after realizing the device, we cannot
rely on
virtio-mem wants to know whether it should not mess with the RAMBlock
content (e.g., discard RAM, preallocate memory) on incoming migration.
So let's expose that function as migrate_ram_is_ignored() in
migration/misc.h
Signed-off-by: David Hildenbrand
---
include/migration/misc.h | 1 +
Stumbling over "x-ignore-shared" migration support for virtio-mem on
my todo list, I remember talking to Dave G. a while ago about how
ram_block_discard_range() in MAP_PIRVATE file mappings is possibly
harmful when the file is used somewhere else -- for example, with VM
templating in multiple VMs.
Introduce both the enumeration and functions to retrieve
the current state, and state outside of EL3.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/cpu.h| 89 ++---
target/arm/helper.c | 60 ++
Add input and output space members to S1Translate. Set and adjust
them in S1_ptw_translate, and the various points at which we drop
secure state. Initialize the space in get_phys_addr; for now leave
get_phys_addr_with_secure considering only secure vs non-secure spaces.
Reviewed-by: Peter
The function takes the fields as filled in by
the Arm ARM pseudocode for TakeGPCException.
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/syndrome.h | 10 ++
1 file changed, 10 insertions(+)
diff --git a/target/arm/syndrome.h b/target/arm/syndrome.h
index
Add an x-rme cpu property to enable FEAT_RME.
Add an x-l0gptsz property to set GPCCR_EL3.L0GPTSZ,
for testing various possible configurations.
Signed-off-by: Richard Henderson
---
target/arm/tcg/cpu64.c | 53 ++
1 file changed, 53 insertions(+)
diff
We will need 2 bits to represent ARMSecurityState.
Do not attempt to replace or widen secure, even though it
logically overlaps the new field -- there are uses within
e.g. hw/block/pflash_cfi01.c, which don't know anything
specific about ARM.
Reviewed-by: Peter Maydell
Signed-off-by: Richard
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