On Tue, Nov 28, 2023 at 4:31 PM Michael S. Tsirkin wrote:
>
> On Mon, Nov 27, 2023 at 07:58:28PM +0900, Hyeonggon Yoo wrote:
> > Hi, this is a fixup for the recent patch series "QEMU: CXL mailbox rework
> > and
> > features (Part 1)" [1].
>
>
> To clarify do you plan v2 of this?
Yes, I will send
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> The H_GUEST_RUN_VCPU hcall is used to start execution of a Guest VCPU.
> The Hypervisor will update the state of the Guest VCPU based on the
> input buffer, restore the saved Guest VCPU state, and start its execution.
>
> The Guest VC
Set mc->valid_cpu_types so that the user specified CPU type can
be validated in machine_run_board_init(). We needn't to do it
by ourselves.
Signed-off-by: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Leif Lindholm
Reviewed-by: Richard Henderson
---
hw/arm/sbsa-ref.c | 36 ++
Set mc->valid_cpu_types so that the user specified CPU type can
be validated in machine_run_board_init(). We needn't to do it
by ourselves.
Signed-off-by: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
---
hw/riscv/shakti_c.c | 13 ++---
1 file changed, 6 insertions(+), 7 deletions(-)
The 'host' CPU model isn't available until KVM or HVF is enabled.
For example, the following error messages are seen when the guest
is started with option '-cpu cortex-a8' on tcg after the next commit
is applied to check the CPU type in machine_run_board_init().
ERROR:../hw/core/machine.c:1423:i
The logic, to check if the specified CPU type is supported in
machine_run_board_init(), is independent enough. Factor it out into
helper is_cpu_type_supported(). machine_run_board_init() looks a bit
clean with this. Since we're here, @machine_class is renamed to @mc to
avoid multiple line spanning
Set mc->valid_cpu_types so that the user specified CPU type can
be validated in machine_run_board_init(). We needn't to do it by
ourselves.
Signed-off-by: Gavin Shan
Reviewed-by: Richard Henderson
Reviewed-by: Philippe Mathieu-Daudé
---
hw/arm/bananapi_m2u.c | 12 ++--
hw/arm/cubiebo
The names of supported CPU models instead of CPU types should be
printed when the user specified CPU type isn't supported, to be
consistent with the output from '-cpu ?'.
Correct the error messages to print CPU model names instead of CPU
type names.
Signed-off-by: Gavin Shan
---
v8: Use g_autofr
It's no sense to check the CPU type when mc->valid_cpu_types[0] is
NULL. So the check is skipped for this particular case. The constraint
has been taken when the error messags are appended.
A precise hint for the error message is given when mc->valid_cpu_types[0]
is the only valid entry. Besides,
Set mc->valid_cpu_types so that the user specified CPU type can be
validated in machine_run_board_init(). We needn't to do the check
by ourselves.
Signed-off-by: Gavin Shan
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Richard Henderson
---
hw/arm/virt.c | 62 +++
QEMU will be terminated if the specified CPU type isn't supported
in machine_run_board_init(). The list of supported CPU type names
is tracked by mc->valid_cpu_types.
The error handling can be used to propagate error messages, to be
consistent how the errors are handled for other situations in the
This series bases on Phil's repository because the prepatory commits
have been queued to the branch.
https://gitlab.com/philmd/qemu.git (branch: cpus-next)
There are two places where the user specified CPU type is checked to see
if it's supported or allowed by the board: machine_run_board_init(
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> spapr_exit_nested gets triggered on a nested guest exit and currently
> being used only for nested-hv API. Isolating code flows based on API
> helps extending it to be used with nested PAPR API as well.
>
Reviewed-by: Nicholas Piggin
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
> partition table info, use the same in spapr_get_pate_nested() as well.
>
> Signed-off-by: Michael Neuling
> Signed-off-by: Harsh Prateek Bora
> ---
> hw/ppc
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> Since cap-nested-hv and cap-nested-papr are mutually exclusive, now it
> makes sense to register api specfic hcalls only when respective
> capability is enabled, hence this change.
>
> Signed-off-by: Harsh Prateek Bora
I think this
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> Introduce a SPAPR capability cap-nested-papr which provides a nested
> HV facility to the guest. This is similar to cap-nested-hv, but uses
> a different (incompatible) API and so they are mutually exclusive.
> This new API is to enab
Hi Phil,
On 11/28/23 20:55, Philippe Mathieu-Daudé wrote:
On 27/11/23 00:12, Gavin Shan wrote:
The names of supported CPU models instead of CPU types should be
printed when the user specified CPU type isn't supported, to be
consistent with the output from '-cpu ?'.
Correct the error messages t
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> Currently, nested_ptcr is being used by existing nested-hv API to store
> nested guest related info. This need to be organised to extend support
> for the nested PAPR API which would need to store additional info related
> to nested g
On Thu Oct 12, 2023 at 8:49 PM AEST, Harsh Prateek Bora wrote:
> Most of the nested code has already been moved to spapr_nested.c
> This logic inside spapr_get_pate is related to nested guests and
> better suited for spapr_nested.c, hence moving there.
>
> Signed-off-by: Harsh Prateek Bora
Review
The KVM_ARM_VCPU_PMU_V3_FILTER provide the ability to let the VMM decide
which PMU events are provided to the guest. Add a new option
`pmu-filter` as -accel sub-option to set the PMU Event Filtering.
Without the filter, the KVM will expose all events from the host to
guest by default.
The `pmu-fil
Ping? Has this been forgotten?
Best regards!
On 2023/11/20 22:01, Peter Xu wrote:
On Mon, Nov 20, 2023 at 11:14:28AM +0800, Zongmin Zhou wrote:
Since socket_parse() will allocate memory for 'saddr',and its value
will pass to 'addr' that allocated by migrate_uri_parse(),
then 'saddr' will no lo
On Tue, Nov 28, 2023 at 11:57 PM Philippe Mathieu-Daudé
wrote:
> Hi Hyman,
>
> On 28/11/23 16:24, Hyman Huang wrote:
> > Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
> >
> > SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> > Organization of State Commercial Adminis
I'll try to understand the comment, if i misunderstood, please point out.
On Wed, Nov 29, 2023 at 12:20 AM Daniel P. Berrangé
wrote:
> On Tue, Nov 28, 2023 at 04:57:20PM +0100, Philippe Mathieu-Daudé wrote:
> > Hi Hyman,
> >
> > On 28/11/23 16:24, Hyman Huang wrote:
> > > Introduce the SM4 ciphe
Hello,
On behalf of the QEMU Team, I'd like to announce the availability of the
third release candidate for the QEMU 8.2 release. This release is meant
for testing purposes and should not be used in a production environment.
http://download.qemu.org/qemu-8.2.0-rc2.tar.xz
http://download.qemu.
Added maintainer for IBM FSI model
Signed-off-by: Ninad Palsule
Signed-off-by: Cédric Le Goater
---
MAINTAINERS | 8
1 file changed, 8 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 695e0bd34f..0536b585fc 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3558,6 +3558,14 @@ F:
This patchset introduces IBM's Flexible Service Interface(FSI).
Time for some fun with inter-processor buses. FSI allows a service
processor access to the internal buses of a host POWER processor to
perform configuration or debugging.
FSI has long existed in POWER processes and so comes with some
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain mapped memory for the devices. The
memory is mapped after CFAM config, peek table and FSI slave registers.
Signed-off-by: Andrew Jeffery
Signed-off-by: Ninad Palsule
[ clg: - remove
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance in the ASPEED SoC due
to tight integration of the FSI master IP with the OPB, mainly the
existence of
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the OPB from being directly
mapped into APB, so all accesses are indirect through the bridge.
Signed-off-
Hello,
Please review the patch-set version 8.
I have incorporated review comments from Cedric.
- Fixed checkpatch failures.
- Fixed commit messages.
- Fixed LBUS memory map size.
Ninad Palsule (10):
hw/fsi: Introduce IBM's Local bus
hw/fsi: Introduce IBM's FSI Bus
hw/fsi: Introduce IB
Added basic qtests for FSI model.
Signed-off-by: Ninad Palsule
Acked-by: Thomas Huth
Signed-off-by: Cédric Le Goater
---
tests/qtest/aspeed-fsi-test.c | 205 ++
tests/qtest/meson.build | 1 +
2 files changed, 206 insertions(+)
create mode 100644 tests/q
This is a part of patchset where FSI bus is introduced.
The FSI bus is a simple bus where FSI master is attached.
Signed-off-by: Andrew Jeffery
Signed-off-by: Ninad Palsule
[ clg: - removed include/hw/fsi/engine-scratchpad.h and
hw/fsi/engine-scratchpad.c
- dropped FSI_SCRATCHPA
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses internal and external
to the POWER chip. Examples include the SBEFIFO and I2C masters. The
engines hang o
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI master. CFAM is hanging out of FSI master which is a
bus controller.
The FSI master: A controller in the platform service processor (e.g.
BMC) driving CFAM engine accesses into the POWER c
Documentation for IBM FSI model.
Signed-off-by: Ninad Palsule
Signed-off-by: Cédric Le Goater
---
docs/specs/fsi.rst | 138 +++
docs/specs/index.rst | 1 +
2 files changed, 139 insertions(+)
create mode 100644 docs/specs/fsi.rst
diff --git a/docs/sp
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
signature.asc
Description: PGP signature
Hi Phil,
On 11/28/23 20:38, Philippe Mathieu-Daudé wrote:
On 27/11/23 00:12, Gavin Shan wrote:
The logic, to check if the specified CPU type is supported in
machine_run_board_init(), is independent enough. Factor it out into
helper is_cpu_type_supported(). machine_run_board_init() looks a bit
c
Hello Cedric,
On 11/27/23 10:31, Cédric Le Goater wrote:
Hello Ninad,
On 10/26/23 18:47, Ninad Palsule wrote:
Hello,
Please review the patch-set version 7.
I have incorporated review comments from Cedric, Philippe and Thomas.
I reworked v7 with the suggestions I made in patches 1-6. Please
Hello Cedric,
On 11/27/23 10:25, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
An APB-to-OPB bridge enabling access to the OPB from the ARM core in
the AST2600. Hardware limitations prevent the
Hi Phil,
On 11/28/23 20:43, Philippe Mathieu-Daudé wrote:
On 27/11/23 00:12, Gavin Shan wrote:
QEMU will be terminated if the specified CPU type isn't supported
in machine_run_board_init(). The list of supported CPU type names
is tracked by mc->valid_cpu_types.
The error handling can be used t
Hello Cedric,
On 11/27/23 10:23, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The On-Chip Peripheral Bus (OPB): A low-speed bus typically found in
POWER processors. This now makes an appearance
Hello Cedric,
On 11/27/23 10:19, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
This commit models the FSI bus. CFAM is hanging out of FSI bus. The bus
is model such a way that it is embedded insi
Hello Cedric,
On 11/27/23 10:31, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses inte
Hello Cedric,
On 11/27/23 10:16, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The Common FRU Access Macro (CFAM), an address space containing
various "engines" that drive accesses on busses inte
Hello Cedric,
On 11/27/23 10:09, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where scratchpad is introduced.
The scratchpad provides a set of non-functional registers. The firmware
is free to use them, hardware does not support any special managem
Hello Cedric,
On 11/27/23 10:30, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically g
On Tue, Nov 28, 2023 at 20:10:10 +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 24.11.23 17:52, Peter Krempa wrote:
> > Introduce a new flag 'backing_file_format_no_protocol' for the
> > block-commit QMP command which instructs the internals to use 'raw'
> > instead of the protocol driver in case
On 11/28/23 18:38, Cédric Le Goater wrote:
On 11/27/23 18:13, Chalapathi V wrote:
Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed
Shutdown requests are normally hardware dependent.
By extending pvpanic to also handle shutdown requests, guests can
submit such requests with an easily implementable and cross-platform
mechanism.
Signed-off-by: Thomas Weißschuh
---
docs/specs/pvpanic.rst | 2 ++
hw/misc/pvpani
Avoid the necessity to update all tests when new events are added
to the device.
Acked-by: Thomas Huth
Signed-off-by: Thomas Weißschuh
---
tests/qtest/pvpanic-pci-test.c | 5 +++--
tests/qtest/pvpanic-test.c | 5 +++--
2 files changed, 6 insertions(+), 4 deletions(-)
diff --git a/tests/qte
Shutdown requests are normally hardware dependent.
By extending pvpanic to also handle shutdown requests, guests can
submit such requests with an easily implementable and cross-platform
mechanism.
The background is the usage of minimal Linux kernels with different
architectures for testing purpose
The different components of pvpanic duplicate the list of supported
events. Move it to the shared header file to minimize changes when new
events are added.
Signed-off-by: Thomas Weißschuh
---
hw/misc/pvpanic-isa.c | 3 +--
hw/misc/pvpanic-pci.c | 3 +--
hw/misc/pvpanic.c | 3 +--
On Tue, Nov 28, 2023 at 06:05:25PM +, Peter Maydell wrote:
> On Tue, 28 Nov 2023 at 17:54, Cédric Le Goater wrote:
> >
> > On 11/21/23 18:11, Alex Bennée wrote:
> > > Peter Maydell writes:
> > >> Topic 2: Are we happy with the email workflow?
> > >> ===
On 11/28/23 05:44, Philippe Mathieu-Daudé wrote:
Thank you Peter. In this case I'm compiling HVF, but this is the
same reasoning. I'll add #ifdef'ry similar to ats_write() (commit
9fb005b02d "target/arm: Restrict the Address Translate write operation
to TCG accel"):
-- >8 --
diff --git a/target/
On Tue, Nov 28, 2023 at 06:54:42PM +0100, Cédric Le Goater wrote:
> On 11/21/23 18:11, Alex Bennée wrote:
> > Peter Maydell writes:
> >
> > > QEMU Summit Minutes 2023
> > >
> > >
> > > As usual, we held a QEMU Summit meeting at KVM Forum. This is an
> > > invite-only me
On 11/28/23 05:08, Philippe Mathieu-Daudé wrote:
Hi,
On 20/7/21 21:54, Richard Henderson wrote:
Trigger breakpoints before beginning translation of a TB
that would begin with a BP. Thus we never generate code
for the BP at all.
Single-step instructions within a page containing a BP so
that we
On Tue, 28 Nov 2023 at 17:54, Cédric Le Goater wrote:
>
> On 11/21/23 18:11, Alex Bennée wrote:
> > Peter Maydell writes:
> >> Topic 2: Are we happy with the email workflow?
> >> ==
> >>
> >> This was a topic to see if there was any consensus among main
On 11/27/23 11:33, Peter Maydell wrote:
There is no architectural requirement that SME implies SVE, but
our implementation currently assumes it. (FEAT_SME_FA64 does
imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
you quickly run into an assert when the guest tries to write to
SM
On 11/21/23 18:11, Alex Bennée wrote:
Peter Maydell writes:
QEMU Summit Minutes 2023
As usual, we held a QEMU Summit meeting at KVM Forum. This is an
invite-only meeting for the most active maintainers and submaintainers
in the project, and we discuss various project
On 11/27/23 18:13, Chalapathi V wrote:
Hello,
Thank you for the review and suggestions on V5.
The suggestions and changes requested from V5 are addressed in V6.
Updates in Version 6 of this series are:
1. adding a device-tree node in QEMU is removed as skiboot defines the
device-tree and Q
Hello Cedric,
On 11/27/23 10:04, Cédric Le Goater wrote:
On 10/26/23 18:47, Ninad Palsule wrote:
This is a part of patchset where IBM's Flexible Service Interface is
introduced.
The LBUS is modelled to maintain the qdev bus hierarchy and to take
advantage of the object model to automatically g
On 11/24/23 09:06, Cédric Le Goater wrote:
When the legacy and iommufd backends were introduced, a set of common
vfio-pci routines were exported in pci.c for both backends to use :
vfio_pci_pre_reset
vfio_pci_get_pci_hot_reset_info
vfio_pci_host_match
vfio_pci_post_reset
This introd
On 24.11.23 17:52, Peter Krempa wrote:
Introduce a new flag 'backing_file_format_no_protocol' for the
block-commit QMP command which instructs the internals to use 'raw'
instead of the protocol driver in case when a image is used without a
dummy 'raw' wrapper.
The flag is designed such that it c
On 11/21/23 09:43, Zhenzhong Duan wrote:
Hi,
Thanks all for giving guides and comments on previous series, this is
the remaining part of the iommufd support.
Besides suggested changes in v6, I'd like to highlight two changes
for final review:
1. Instantiate can_be_deleted callback to fix race w
On Mon, 18 Sep 2023 18:02:39 +0200
Philippe Mathieu-Daudé wrote:
> While create_vcpu_thread() creates a vCPU thread, its counterpart
> is cpu_remove_sync(), which join and destroy the thread.
>
> create_vcpu_thread() is called in qemu_init_vcpu(), itself called
> in cpu_common_realizefn(). Since
On 28/11/23 15:02, Richard Henderson wrote:
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
To allow GTIMER_* definitions to be used by non-ARM specific
hardware models, move them to a new target agnostic "cpu-defs.h"
header.
Signed-off-by: Philippe Mathieu-Daudé
---
target/arm/cpu-defs.h |
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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On Tue, 21 Nov 2023 at 12:35, Kevin Wolf wrote:
>
> Kevin Wolf (2):
> qdev: Fix crash in array property getter
> string-output-visitor: Support lists for non-integer types
>
> hw/core/qdev-properties.c| 33 ++---
> qapi/string-output-visitor.c | 24
Applied, thanks.
Please update the changelog at https://wiki.qemu.org/ChangeLog/8.2 for any
user-visible changes.
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On Tue, Nov 28, 2023 at 04:57:20PM +0100, Philippe Mathieu-Daudé wrote:
> Hi Hyman,
>
> On 28/11/23 16:24, Hyman Huang wrote:
> > Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
> >
> > SM4 (GBT.32907-2016) is a cryptographic standard issued by the
> > Organization of State Commercia
On Mon, 18 Sep 2023 18:02:38 +0200
Philippe Mathieu-Daudé wrote:
> qemu_init_vcpu() is called in each ${target}_cpu_realize() before
> the call to parent_realize(), which is cpu_common_realizefn().
> Call it once there.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/core/cpu-common.c
On Tue, Nov 28, 2023 at 11:00:29AM -0500, Michael S. Tsirkin wrote:
> On Tue, Nov 28, 2023 at 03:53:21PM +0100, Fiona Ebner wrote:
> > Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> > > On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> > >> we received some reports about the new de
On Tue, Nov 28, 2023 at 03:53:21PM +0100, Fiona Ebner wrote:
> Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> > On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> >> we received some reports about the new default causing issues for
> >> certain guest OSes [0][1]. Namely, for Juniper
On Mon, 18 Sep 2023 18:02:37 +0200
Philippe Mathieu-Daudé wrote:
> QDev instance is expected to be in an unknown state until full
> object realization. Thus we shouldn't call DeviceReset() on an
> unrealized instance. Move the cpu_reset() call from *before*
> the parent realize() handler (effecti
Hi Hyman,
On 28/11/23 16:24, Hyman Huang wrote:
Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
SM4 (GBT.32907-2016) is a cryptographic standard issued by the
Organization of State Commercial Administration of China (OSCCA)
as an authorized cryptographic algorithms for the use with
On 11/26/23 09:56, Paolo Bonzini wrote:
Il sab 25 nov 2023, 13:23 Petr Cvek mailto:petrcve...@gmail.com>>
ha scritto:
GCC defines __i386__ for i386 and i486, which both lack RDTSC instruction.
The i386 seems to be impossible to distinguish, but i486 can be identified
by checking
On Mon, 18 Sep 2023 18:02:36 +0200
Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Igor Mammedov
> ---
> target/i386/kvm/kvm-cpu.c | 1 +
> 1 file changed, 1 insertion(+)
>
> diff --git a/target/i386/kvm/kvm-cpu.c b/target/i386/kvm/kvm-cpu.c
> index 723737
[Cross-posted to KVM, Rust-VMM, QEMU, and libvirt lists)
Hi, the CFP for the "Virt & IaaS" DevRoom is out[+].
Something new this year is a new talk-submission system: so you need to
create a new account, even if you've had an account with the older
talk-submission system. Details in the "Submit
On Mon, Nov 27 2023, Peter Maydell wrote:
> There is no architectural requirement that SME implies SVE, but
> our implementation currently assumes it. (FEAT_SME_FA64 does
> imply SVE.) So if you try to run a CPU with eg "-cpu max,sve=off"
> you quickly run into an assert when the guest tries to w
On Mon, 18 Sep 2023 18:02:35 +0200
Philippe Mathieu-Daudé wrote:
> QOM objects shouldn't access each other internals fields
> except using the QOM API.
>
> Declare the 'cpu' and 'base-addr' properties, set them
> using object_property_set_link() and qdev_prop_set_uint32()
> respectively.
>
> Si
On Mon, 18 Sep 2023 18:02:34 +0200
Philippe Mathieu-Daudé wrote:
> APIC state is created under a certain condition,
> use the same condition to realize it.
> Having a NULL APIC state is a bug: use assert().
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/i386/cpu-sysemu.c | 9 +++-
Introduce the SM4 cipher algorithms (OSCCA GB/T 32907-2016).
SM4 (GBT.32907-2016) is a cryptographic standard issued by the
Organization of State Commercial Administration of China (OSCCA)
as an authorized cryptographic algorithms for the use within China.
Use the crypto-sm4 meson build option fo
(Cc'ing Ariadne, libucontext maintainer)
On 21/1/21 19:53, Peter Maydell wrote:
On Tue, 5 Jan 2021 at 02:25, Joelle van Dyne wrote:
This introduces support for building for iOS hosts. When the correct Xcode
toolchain is used, iOS host will be detected automatically.
* block: disable features
Am 28.11.23 um 15:13 schrieb Daniel P. Berrangé:
> On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
>> we received some reports about the new default causing issues for
>> certain guest OSes [0][1]. Namely, for Juniper vSRX, where boot fails
>> and Microsoft Windows, where querying an U
> On Nov 1, 2023, at 9:16 AM, Mattias Nissler wrote:
>
> PCI config space is little-endian, so on a big-endian host we need to
> perform byte swaps for values as they are passed to and received from
> the generic PCI config space access machinery.
>
> Signed-off-by: Mattias Nissler
Reviewed
> On Nov 1, 2023, at 9:16 AM, Mattias Nissler wrote:
>
> Wire up support for DMA for the case where the vfio-user client does not
> provide mmap()-able file descriptors, but DMA requests must be performed
> via the VFIO-user protocol. This installs an indirect memory region,
> which already wo
binutils 2.39 shows some warnings when building pvh.img
/usr/bin/ld: warning: pvh.o: missing .note.GNU-stack section implies executable
stack
/usr/bin/ld: NOTE: This behaviour is deprecated and will be removed in a future
version of the linker
/usr/bin/ld: warning: pvh.img has a LOAD segment wit
On 11/27/23 18:13, Chalapathi V wrote:
A POWER10 chip is divided into logical pieces called chiplets. Chiplets
are broadly divided into "core chiplets" (with the processor cores) and
"nest chiplets" (with everything else). Each chiplet has an attachment
to the pervasive bus (PIB) and with chiplet
On Tue, 28 Nov 2023, Philippe Mathieu-Daudé wrote:
On 28/11/23 13:47, BALATON Zoltan wrote:
On Sun, 26 Nov 2023, BALATON Zoltan wrote:
Philippe,
Could this be merged for 8.2 as it fixes USB on the amigaone machine?
This would be useful as usb-storage is the simplest way to share data
with the
On Tue, Nov 28, 2023 at 02:57:17PM +0100, Fiona Ebner wrote:
> Am 26.06.23 um 14:29 schrieb Michael S. Tsirkin:
> > From: Suravee Suthikulpanit
> >
> > Currently, pc-q35 and pc-i44fx machine models are default to use SMBIOS 2.8
> > (32-bit entry point). Since SMBIOS 3.0 (64-bit entry point) is no
On Tue, 2023-11-28 at 01:20 +, Volodymyr Babchuk wrote:
> Hi David,
>
> Thank you for the review
>
> David Woodhouse writes:
>
> > [[S/MIME Signed Part:Undecided]]
> > On Fri, 2023-11-24 at 23:24 +, Volodymyr Babchuk wrote:
> > > Xen PV devices in QEMU can be created in two ways: either
The vhost-user-blk export implement AioContext switches in its drain
implementation. This means that on drain_begin, it detaches the server
from its AioContext and on drain_end, attaches it again and schedules
the server->co_trip coroutine in the updated AioContext.
However, nothing guarantees tha
From: Fam Zheng
If the text description file is larger than DESC_SIZE, we force the last
byte in the buffer to be 0 and write it out.
This results in a corruption.
Try to allocate a big buffer in this case.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1923
Signed-off-by: Fam Zheng
From: BALATON Zoltan
Return default value in legacy mode for BAR4 when unset. This can't be
set in reset method because BARs are cleared on reset so we return it
instead when BARs are read in legacy mode. This fixes UDMA on amigaone
with AmigaOS.
Signed-off-by: BALATON Zoltan
Message-ID: <20231
From: Andrey Drobyshev
The machine type is being detected based on "-M help" output, and we're
searching for the line ending with " (default)". However, in downstream
one of the machine types s marked as deprecated might become the
default, in which case this logic breaks as the line would now e
The following changes since commit e867b01cd6658a64c16052117dbb18093a2f9772:
Merge tag 'qga-pull-2023-11-25' of https://github.com/kostyanf14/qemu into
staging (2023-11-27 08:59:00 -0500)
are available in the Git repository at:
https://repo.or.cz/qemu/kevin.git tags/for-upstream
for you to
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
The ARMCPU type is forward declared as a pointer to all hw/ files.
Its declaration is restricted to target/arm/ files. By using a
pointer in BCM283XState instead of embedding the whole CPU state,
we don't need to include "cpu.h" which is target-spe
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
The 'mp-affinity' property is present since commit 15a21fe028
("target-arm: Add mp-affinity property for ARM CPU class").
Use it and remove a /* TODO */ comment. Since all ARM CPUs
have this property, use &error_abort, because this call can
not fai
On 11/22/23 12:30, Philippe Mathieu-Daudé wrote:
All ARM CPUs have the 'start-powered-off' property since commit
5de164304a ("arm: Allow secondary KVM CPUs to be booted via PSCI").
Note: since commit c1b701587e ("target/arm: Move start-powered-off
property to generic CPUState"), all CPUs for all
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