Hi,
>
> On Thu, Dec 14, 2023 at 8:26 AM Dongwon Kim
> wrote:
> >
> > If the guest state is paused before it gets a response for the current
> > scanout frame submission (resource-flush), it won't flush new frames
> > after being restored as it still waits for the old response, which is
> > accep
On 11/16/2023 1:58 AM, Daniel P. Berrangé wrote:
On Wed, Nov 15, 2023 at 02:15:01AM -0500, Xiaoyao Li wrote:
From: Isaku Yamahata
For GetQuote, delegate a request to Quote Generation Service.
Add property "quote-generation-socket" to tdx-guest, whihc is a property
of type SocketAddress to spec
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/targ
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by: At
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for m
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 67 ++
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 1 -
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
3 files changed, 35 insertions(+),
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The cycle/instr
Privilege mode filtering can also be emulated for cycle/instret by
tracking host_ticks/icount during each privilege mode switch. This
patch implements that for both cycle/instret and mhpmcounters. The
first one requires Smcntrpmf while the other one requires Sscofpmf
to be enabled.
The cycle/instr
From: Kaiwen Xue
This adds the definitions for ISA extension smcntrpmf.
Signed-off-by: Kaiwen Xue
Signed-off-by: Atish Patra
---
target/riscv/cpu.c | 1 -
target/riscv/cpu.h | 6 ++
target/riscv/cpu_bits.h | 29 +
3 files changed, 35 insertions(+),
This patch series adds the support for RISC-V ISA extension smcntrpmf (cycle and
privilege mode filtering) [1]. It is based on Kevin's earlier work but improves
it by actually implement privilege mode filtering by tracking the privilege
mode switches. This enables the privilege mode filtering for m
mhpmeventhX CSRs are available for RV32. The predicate function
should check that first before checking sscofpmf extension.
Fixes: 14664483457b ("target/riscv: Add sscofpmf extension support")
Signed-off-by: Atish Patra
---
target/riscv/csr.c | 67 ++
From: Kaiwen Xue
QEMU only calculates dummy cycles and instructions, so there is no
actual means to stop the icount in QEMU. Hence this patch merely adds
the functionality of accessing the cfg registers, and cause no actual
effects on the counting of cycle and instret counters.
Signed-off-by: At
From: Kaiwen Xue
This adds the properties for ISA extension smcntrpmf. Patches
implementing it will follow.
Signed-off-by: Atish Patra
Signed-off-by: Kaiwen Xue
---
target/riscv/cpu.c | 3 ++-
target/riscv/cpu_cfg.h | 1 +
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/targ
On 12/24/23 15:48, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/translate.c | 23 +--
target/riscv/vector_helper.c | 10 ++
2 files changed, 31 insertions(+), 2 deletions(-)
diff --git a/target/riscv/translate.c b/t
On 12/24/23 15:48, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 4 +++
target/riscv/cpu_helper.c | 54 +++
2 files changed, 58 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
i
On 12/24/23 15:48, Alexey Baturo wrote:
From: Alexey Baturo
Signed-off-by: Alexey Baturo
---
target/riscv/cpu.h| 15 +--
target/riscv/cpu_helper.c | 3 +++
target/riscv/translate.c | 5 +
3 files changed, 17 insertions(+), 6 deletions(-)
diff --git a/target/ris
On 12/23/23 05:16, Paolo Bonzini wrote:
+case JCC_S:
+cmp_lhs = s->T0, cmp_rhs = tcg_constant_tl(0);
+break;
I think you need an sextract here, when ot != full word size, same as JCC_O.
Otherwise,
Reviewed-by: Richard Henderson
r~
On 12/23/23 05:16, Paolo Bonzini wrote:
ALU instructions can write to both memory and flags. If the CC_SRC*
and CC_DST locations have been written already when a memory access
causes a fault, the value in CC_SRC* and CC_DST might be interpreted
with the wrong CC_OP (the one that is in effect bef
On 12/23/23 05:16, Paolo Bonzini wrote:
Similar to gen_setcc1, make gen_cmovcc1 receive TCGv. This is more friendly
to simultaneous implementation in the old and the new decoder.
A small wart is that s->T0 of CMOV is currently the*second* argument (which
would ordinarily be in T1). Therefore,
On 12/23/23 05:15, Paolo Bonzini wrote:
Do not use gen_op, and pull the load from the accumulator into
disas_insn.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 9 +++--
1 file changed, 7 insertions(+), 2 deletions(-)
Reviewed-by: Richard Henderson
r~
On 12/23/23 05:15, Paolo Bonzini wrote:
Extract the code into new functions, and swap T0/T1 so that T0 corresponds
to the first immediate in the instruction stream.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 90 -
1 file changed, 50 ins
I noticed something weird when using "-cpu host" with Windows vms.
First, I always use it along with ",hv_passthrough" as well.
First, performance: since some years ago, since prior to qemu 6.2 until
latest 8.2, win10 and win11 vms always worked slower than expected. This
could be noticed by co
In 050a1ba, when moving the macros from preprocessor-guarding to
file-based definition, TARGET_O_LARGEFILE appeared to have been
accidentally left off.
This may have correctness implication, but so far I was only confused by
strace's output.
Fixes: 050a1ba69a ("linux-user: move arm/aarch64/m68k f
Commit b8002058 strengthened openat()'s /proc detection by calling
realpath(3) on the given path, which allows various paths and symlinks
that points to the /proc file system to be intercepted correctly.
Using realpath(3), though, has a side effect that it reads the symlinks
along the way, and thu
Since v3:
- Fix build error: ignoring return value of 'readlink' declared with attribute
'warn_unused_result' [-Werror=unused-result]
Since v2:
- More robust handling of `readlink()`
Since v1:
- Eliminate static buffers in do_guest_openat()
Shu-Chun Weng (2):
linux-user: Define TARGET_O_
Yup, reproduced on a system with glibc built with fortified source. Sending
out version 4.
On Thu, Dec 28, 2023 at 7:49 AM Helge Deller wrote:
> On 12/8/23 23:42, Shu-Chun Weng wrote:
> > Commit b8002058 strengthened openat()'s /proc detection by calling
> > realpath(3) on the given path, which
On 12/23/23 05:15, Paolo Bonzini wrote:
Create a new temporary, to ease the register allocator's work.
Creation of the temporary is pushed into gen_ext_tl, which
also allows NULL as the first parameter now.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 9 ++---
1 file ch
On 12/23/23 05:15, Paolo Bonzini wrote:
Just create a temporary for the occasion.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Richard Henderson
r~
On 12/23/23 05:15, Paolo Bonzini wrote:
The new x86 decoder wants the gen_* functions to compute EFLAGS before
writeback, which can be an issue for instructions with a memory
destination such as ARPL or shifts.
Extract code to compute the EFLAGS without clobbering CC_SRC, in case
the memory writ
On 12/23/23 05:15, Paolo Bonzini wrote:
The new decoder would rather have the operand in T0 when expanding SCAS, rather
than use R_EAX directly as gen_scas currently does. This makes SCAS more
similar
to CMP and SUB, in that CC_DST = T0 - T1.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/
On 12/23/23 05:15, Paolo Bonzini wrote:
decode->mem is only used if one operand has has_ea == true. String
operations will not use decode->mem and will load A0 on their own, because
they are the only case of two memory operands in a single instruction.
Signed-off-by: Paolo Bonzini
---
target/
On 12/23/23 05:15, Paolo Bonzini wrote:
Usually the registers are just moved into s->T0 without much care for
their operand size. However, in some cases we can get more efficient
code if the operand fetching logic syncs with the emission function
on what is nicer.
All the current uses are mostl
On 12/23/23 05:15, Paolo Bonzini wrote:
X86_SPECIAL_ZExtOp0 and X86_SPECIAL_ZExtOp2 are poorly named; they are a hack
that is needed by scalar insertion and extraction instructions, and not really
related to zero extension: for PEXTR the zero extension is done by the
generation
functions, for PI
On 12/23/23 05:15, Paolo Bonzini wrote:
The previous check erroneously allowed CMP to be modified with LOCK.
Instead, tag explicitly the instructions that do support LOCK.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 17 ++---
target/i386/tcg/decode-new.h
On 12/23/23 05:15, Paolo Bonzini wrote:
Use _tl operations for 32-bit operands on 32-bit targets, and only go
through trunc and extu ops for 64-bit targets. While the trunc/ext
ops should be pretty much free after optimization, the optimizer also
does not like having the same temporary used in m
On 12/23/23 05:15, Paolo Bonzini wrote:
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/decode-new.c.inc | 12
1 file changed, 12 insertions(+)
Reviewed-by: Richard Henderson
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index 2bdbb1bba
On 12/23/23 05:15, Paolo Bonzini wrote:
cpu_cc_compute_all() has an argument that is always equal to CC_OP for
historical
reasons (dating back to commit a7812ae4123, "TCG variable type checking.",
2008-11-17,
which added the argument to helper_cc_compute_all). It does not make sense for
the
a
On 12/23/23 05:15, Paolo Bonzini wrote:
gen_lea_v_seg (called by gen_add_A0_ds_seg) already zeroes any
bits of s->A0 beyond s->aflag. It does so before summing the
segment base and, if not in 64-bit mode, also after summing it.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/emit.c.inc | 4
On 12/23/23 05:15, Paolo Bonzini wrote:
is_int is always 1, and error_code is always zero.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/excp_helper.c | 7 +++
target/i386/tcg/helper-tcg.h | 3 +--
target/i386/tcg/misc_helper.c | 2 +-
3 files changed, 5 insertions(+), 7 deletions(-
On 12/23/23 05:15, Paolo Bonzini wrote:
OF is equal to the carry flag, so use the same CCPrepare.
Signed-off-by: Paolo Bonzini
---
target/i386/tcg/translate.c | 3 +++
1 file changed, 3 insertions(+)
Reviewed-by: Richard Henderson
r~
On 12/23/23 05:15, Paolo Bonzini wrote:
Take advantage of the fact that there can be no 1 bits between SF and OF.
If they were adjacent, you could sum SF and get a carry only if SF was
already set. Then the value of OF in the sum is the XOR of OF itself,
the carry (which is SF) and 0 (the value
On 12/28/23 23:05, Paolo Bonzini wrote:
In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can
operate on a low-byte register and shorten the output by two or three bytes
(two if a prefix byte is needed for REX.B).
Signed-off-by: Paolo Bonzini
---
tcg/i386/tcg-target.c
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi everyone,
The QEMU v8.1.4 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-8.1.4.tar.xz
https://download.qemu.org/qemu-8.1.4.tar.x
-BEGIN PGP SIGNED MESSAGE-
Hash: SHA256
Hi everyone,
The QEMU v7.2.8 stable release is now available.
You can grab the tarball from our download page here:
https://www.qemu.org/download/#source
https://download.qemu.org/qemu-7.2.8.tar.xz
https://download.qemu.org/qemu-7.2.8.tar.x
The QMP command "x-query-virtio-status" outputs the full
feature and status bit information, so there is no need
to maintain it in the HMP output; drop it.
Signed-off-by: Hyman Huang
---
hw/virtio/virtio-hmp-cmds.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/hw/virtio/virti
This patchset is derived from the series:
https://lore.kernel.org/qemu-devel/cover.1699793550.git.yong.hu...@smartx.com/
Please go to the link to see more background information.
The following points are what we have done in the patchset:
1. Take the policy of adding human-readable output just in
Maintain the feature and status bits in the x-query-virtio-status
output and, as usual, add human-readable output only in HMP.
Applications may find it useful to compare features and status
information directly. An upper application, for example, could
use the QMP command x-query-virtio-status to
Hi Marc-André,
I reviewed and realized these conditions won't be met in normal situations in
given upstream code. But we've initially added those conditions in our internal
code base for dev because we often had to call gd_hw_gl_flushed to forcefully
unblock from HPD code (i.e. 'connectors' par
On 28/12/2023 09:46, Philippe Mathieu-Daudé wrote:
On 27/12/23 22:02, Mark Cave-Ayland wrote:
There is no need to dynamically allocate the memory region from the heap.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 7 +++
include/hw/m68k/q800.h | 1 +
2 files changed, 4
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates
more than 32 event/interrupt requests and thus uses more registers
than STM32F4xx EXTI which generates 23 event/interrupt requests.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
docs/system/arm/b-l475e-iot01a.rs
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 56 --
include/hw/arm/stm32l4x5_soc.h | 3 ++
3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/a
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build | 5 +
tests/qtest/stm32l4x5_exti-test.c | 596 ++
2 files changed, 601 insertions(+)
create mode 100644 tests/qtest/stm32l4x5_exti-test.c
diff --git a/tests/qtest/meson.
ERRATUM : I mistakenly sent an incorrect version v4 of this patch.
This version v5 rectifies the error and replaces the erroneous v4.
All my apologies.
Changes from v4 to v5:
- update the documentation file
Changes from v3 to v4:
- add a test to check that irq trigger selection works correctly
(`
Although very similar to the STM32F4xx EXTI, STM32L4x5 EXTI generates
more than 32 event/interrupt requests and thus uses more registers
than STM32F4xx EXTI which generates 23 event/interrupt requests.
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/misc/Kconfig
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
hw/arm/Kconfig | 1 +
hw/arm/stm32l4x5_soc.c | 56 --
include/hw/arm/stm32l4x5_soc.h | 3 ++
3 files changed, 58 insertions(+), 2 deletions(-)
diff --git a/hw/arm/Kconfig b/hw/a
Signed-off-by: Arnaud Minier
Signed-off-by: Inès Varhol
---
tests/qtest/meson.build | 5 +
tests/qtest/stm32l4x5_exti-test.c | 596 ++
2 files changed, 601 insertions(+)
create mode 100644 tests/qtest/stm32l4x5_exti-test.c
diff --git a/tests/qtest/meson.
Changes from v3 to v4:
- add a test to check that irq trigger selection works correctly
(`test_edge_selector`) and correct `stm32l4x5_exti_set_irq` accordingly
- update the documentation file
Changes from v2 to v3:
- corrected the license to GPL
Changes from v1 to v2:
- correct the commit message
On 23/12/2023 11:47, Paolo Bonzini wrote:
The linear address is the one that has the segment base added, and it is
not truncated to 16 bits (otherwise the whole A20 thing would not
exist). The same should be true of e.g. an FSAVE instruction; it would
allow access slightly beyond the usual 1M+6
On 12/8/23 23:42, Shu-Chun Weng wrote:
Commit b8002058 strengthened openat()'s /proc detection by calling
realpath(3) on the given path, which allows various paths and symlinks
that points to the /proc file system to be intercepted correctly.
Using realpath(3), though, has a side effect that it
On 12/26/23 16:21, Michael S. Tsirkin wrote:
On Mon, Dec 25, 2023 at 11:40:54PM +0700, Bui Quang Minh wrote:
Hi everyone,
This series implements x2APIC mode in userspace local APIC and the
RDMSR/WRMSR helper to access x2APIC registers in x2APIC mode. Intel iommu
and AMD iommu are adjusted to su
RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 51
hw/arm/virt-acpi-build.c| 68 +++
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng
---
hw/riscv/virt-acpi-build.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index d
This series focuses on enabling the Serial Port Console Redirection (SPCR)
table for the RISC-V virt platform. Considering that ARM utilizes the same
function, the initial patch involves migrating the build_spcr function to
common code. This consolidation ensures that RISC-V avoids duplicating the
Le 27/12/2023 à 22:02, Mark Cave-Ayland a écrit :
There is no need to dynamically allocate the memory region from the heap.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 7 +++
include/hw/m68k/q800.h | 1 +
2 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/hw
On 28/12/23 12:33, Paolo Bonzini wrote:
Queued with the duplication removed, thanks.
Thanks!
Extend the existing conditional that generates INC/DEC, to also swap an
ADD for a SUB and vice versa when the immediate is 128. This facilitates
using OPC_ARITH_EvIb instead of OPC_ARITH_EvIz.
Best reviewed with "git diff -b".
Signed-off-by: Paolo Bonzini
---
tcg/i386/tcg-target.c.inc | 40 +++
In the case where OR or XOR has an 8-bit immediate between 128 and 255, we can
operate on a low-byte register and shorten the output by two or three bytes
(two if a prefix byte is needed for REX.B).
Signed-off-by: Paolo Bonzini
---
tcg/i386/tcg-target.c.inc | 7 +++
1 file changed, 7 inserti
Queued with the duplication removed, thanks.
Paolo
If all the bits in a dirty bitmap cluster are ones, the cluster shouldn't
be written. Instead the corresponding L1 entry should be set to 1.
Check if all bits in a memory region are ones and set 1 to L1 entries
corresponding clusters filled with ones.
Signed-off-by: Alexander Ivanov
---
block/p
All the checks were fixed to work with used bitmap. Create used bitmap in
parallels_open() even if need_check is true.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 10 --
1 file changed, 4 insertions(+), 6 deletions(-)
diff --git a/block/parallels.c b/block/parallels.c
index
These tests pass with parallels format. Add parallels to supporting
formats for these tests.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/256 | 2 +-
tests/qemu-iotests/299 | 2 +-
tests/qemu-iotests/304 | 2 +-
tests/qemu-
Now we support extensions saving and can let to work with them in
read-write mode.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 4
block/parallels.c | 17 -
2 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/block/parallels-ext.c b/block/para
After bitmap loading the bitmap is not persistent and is removed on image
saving. Set bitmap persistence to true.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels-ext.c b/block/parallels-ext.c
index 033ca3ec3a..2a7ff6e3
Since we have used bitmap, leak check is useless. Transform
parallels_truncate_unused_clusters() to parallels_check_unused_clusters()
helper and use it in leak check.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 121 +-
1 file changed, 67 in
Add a helper to set unused areas in the used bitmap.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 18 ++
block/parallels.h | 2 ++
2 files changed, 20 insertions(+)
diff --git a/block/parallels.c b/block/parallels.c
index 4470519656..13726fb3d5 100644
--- a/block/par
There is no necessity to search to the end of the bitmap. Limit the search
area as cluster_index + count.
Add cluster_end variable to avoid its calculation in a few places.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff
Use a different bitmap name for parallels images because their has own ID
format, and can't contain an arbitrary string.
Replace hardcoded 'qcow2' format to iotests.imgfmt.
Add 'parallels' to supported formats.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/image-fleecing | 13 ++
Use a different bitmap name for parallels images because their has own ID
format, and can't contain an arbitrary string.
Replace image reopen by shutdown/launch VM because parallels images doesn't
support reopen.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/165 | 40 ++
Now dirty bitmaps can be loaded but there is no their saving. Add code for
dirty bitmap storage.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 168 ++
block/parallels.c | 16 +++-
block/parallels.h | 5 ++
3 files changed, 187 inse
In parallels_check_duplicate() We use a bitmap for duplication detection.
This bitmap is not related to used_bmap field in BDRVParallelsState. Add
a comment about it to avoid confusion.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-
We are going to add parallels image extensions storage and need a separate
function for inactivation code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/block/parallel
In parallels_check_leak() file can be truncated. In this case the used
bitmap would not comply to the file. Recreate the bitmap after file
truncation.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 8
1 file changed, 8 insertions(+)
diff --git a/block/parallels.c b/block/paral
Since we have used bitmap, field data_end in BDRVParallelsState is
redundant and can be removed.
Add parallels_data_end() helper and remove data_end handling.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 33 +
block/parallels.h | 1 -
2 files changed,
Let the function return a success code if a file size is not bigger than
image_end_offset. Thus we can decrease indents in the next code block.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 72 +++
1 file changed, 36 insertions(+), 36 deletio
For parallels images extensions we need to allocate host clusters
without any connection to BAT. Move host clusters allocation code to
parallels_allocate_host_clusters().
This function can be called not only from coroutines so all the
*_co_* functions were replaced by corresponding wrappers.
Sign
On an image closing there can be unused clusters in the end of the image.
Truncate these clusters and update data_end field.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/block/parallels.c b/block/p
We will need this function and a function for marking unused clusters (will
be added in the next patch) in parallels-ext.c too. Let it be a global
function parallels_mark_used().
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 14 --
block/paralle
Parallels format driver:
* make some preparation
* add dirty bitmap saving
* make dirty bitmap RW
* fix broken checks
* refactor leak check
* add parallels format support to several tests
You could find these patches in my repo:
https://github.com/AlexanderIvanov-Virtuozzo/qemu/tree/parallels-v4
In parallels_check_leak() we change file size but don't correct data_end
field of BDRVParallelsState structure. Fix it.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels.c b/block/parallels.c
index 658902ae51..8a6e2ba7ee 100
After used bitmap freeng s->used_bmap points to the freed memory. If we try
to free used bitmap one more time it leads to double free error.
Set s->used_bmap to NULL to exclude double free error.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 1 +
1 file ch
Sorry, incorrect patch set, please ignore.
On 12/28/23 10:41, Alexander Ivanov wrote:
After used bitmap freeng s->used_bmap points to the freed memory. If we try
to free used bitmap one more time it leads to double free error.
Set s->used_bmap to NULL to exclude double free error.
Signed-off-b
On 27/12/23 22:02, Mark Cave-Ayland wrote:
There is no need to dynamically allocate the memory region from the heap.
Signed-off-by: Mark Cave-Ayland
---
hw/m68k/q800.c | 7 +++
include/hw/m68k/q800.h | 1 +
2 files changed, 4 insertions(+), 4 deletions(-)
@@ -406,13 +405,13
On an image closing there can be unused clusters in the end of the image.
Truncate these clusters and update data_end field.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 20 ++--
1 file changed, 18 insertions(+), 2 deletions(-)
diff --git a/block/parallels.c b/block/p
We will need this function and a function for marking unused clusters (will
be added in the next patch) in parallels-ext.c too. Let it be a global
function parallels_mark_used().
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 14 --
block/paralle
Now we support extensions saving and can let to work with them in
read-write mode.
Signed-off-by: Alexander Ivanov
---
block/parallels-ext.c | 4
block/parallels.c | 17 -
2 files changed, 4 insertions(+), 17 deletions(-)
diff --git a/block/parallels-ext.c b/block/para
In parallels_check_leak() file can be truncated. In this case the used
bitmap would not comply to the file. Recreate the bitmap after file
truncation.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 8
1 file changed, 8 insertions(+)
diff --git a/block/parallels.c b/block/paral
In parallels_check_leak() we change file size but don't correct data_end
field of BDRVParallelsState structure. Fix it.
Signed-off-by: Alexander Ivanov
---
block/parallels.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/block/parallels.c b/block/parallels.c
index 658902ae51..8a6e2ba7ee 100
We are going to add parallels image extensions storage and need a separate
function for inactivation code.
Signed-off-by: Alexander Ivanov
Reviewed-by: Denis V. Lunev
---
block/parallels.c | 22 --
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/block/parallel
Use a different bitmap name for parallels images because their has own ID
format, and can't contain an arbitrary string.
Replace hardcoded 'qcow2' format to iotests.imgfmt.
Add 'parallels' to supported formats.
Signed-off-by: Alexander Ivanov
---
tests/qemu-iotests/tests/image-fleecing | 13 ++
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