From: Zack Buhman
The saturation arithmetic logic in helper_macl is not correct.
I tested and verified this behavior on a SH7091.
Signed-off-by: Zack Buhman
Message-Id: <20240404162641.27528-2-z...@buhman.org>
[rth: Reformat helper_macl, add a test case.]
Signed-off-by: Richard Henderson
---
Zack's recent patches, tidied a little bit, and with
test cases added.
r~
Richard Henderson (1):
target/sh4: Merge mach and macl into a union
Zack Buhman (3):
target/sh4: mac.w: memory accesses are 16-bit words
target/sh4: Fix mac.l with saturation enabled
target/sh4: Fix mac.w with
Allow host access to the entire 64-bit accumulator.
Signed-off-by: Richard Henderson
---
target/sh4/cpu.h | 14 --
1 file changed, 12 insertions(+), 2 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9211da6bde..d928bcf006 100644
--- a/target/sh4/cpu.h
+++
From: Zack Buhman
The saturation arithmetic logic in helper_macw is not correct.
I tested and verified this behavior on a SH7091.
Signed-off-by: Zack Buhman
Message-Id: <20240405233802.29128-3-z...@buhman.org>
[rth: Reformat helper_macw, add a test case.]
Signed-off-by: Richard Henderson
---
From: Zack Buhman
Before this change, executing a code sequence such as:
mova tblm,r0
movr0,r1
mova tbln,r0
clrs
clrmac
mac.w @r0+,@r1+
mac.w @r0+,@r1+
.align 4
tblm:.word 0x1234
The saturation arithmetic logic in helper_macw is not correct.
I tested and verified this behavior on a SH7091, the general pattern
is a code sequence such as:
sets
mov.l _mach,r2
lds r2,mach
mov.l _macl,r2
lds r2,macl
mova _n,r0
mov
Peter Maydell writes:
> On Fri, 5 Apr 2024 at 08:55, Zack Buhman wrote:
>>
>> The saturation arithmetic logic in helper_macw is not correct.
>>
>> I tested and verified this behavior on a SH7091, the general pattern
>> is a code sequence such as:
>>
>> sets
>>
>> mov.l
On 4/4/24 06:26, Zack Buhman wrote:
The saturation arithmetic logic in helper_macl is not correct.
I tested and verified this behavior on a SH7091, the general pattern
is a code sequence such as:
sets
mov.l _mach,r2
lds r2,mach
mov.l _macl,r2
lds
On 4/1/24 23:37, Zack Buhman wrote:
Before this change, executing a code sequence such as:
mova tblm,r0
movr0,r1
mova tbln,r0
clrs
clrmac
mac.w @r0+,@r1+
mac.w @r0+,@r1+
.align 4
tblm:
On 4/4/24 09:47, Philippe Mathieu-Daudé wrote:
Only the files in hwcore_ss[] are required to link
a user emulation binary.
Have meson process the hw/ sub-directories if system
emulation is selected, otherwise directly process
hw/core/ to get hwcore_ss[], which is the only set
required by user
On 4/4/24 09:47, Philippe Mathieu-Daudé wrote:
reset.c contains core code used by any CPU, required
by user emulation. Move it to hwcore_ss[] where it
belongs.
Signed-off-by: Philippe Mathieu-Daudé
---
hw/core/meson.build | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
On Fri, Apr 5, 2024 at 7:03 AM Jonathan Cameron
wrote:
>
> On Fri, 5 Apr 2024 00:07:06 +
> "Ho-Ren (Jack) Chuang" wrote:
>
> > The current implementation treats emulated memory devices, such as
> > CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> >
On 4/2/24 23:20, Michael Vogt wrote:
From: Michael Vogt
Tiny patch to add the missing FITRIM ioctl.
Signed-off-by: Michael Vogt
---
linux-user/ioctls.h| 3 +++
linux-user/syscall_defs.h | 1 +
linux-user/syscall_types.h | 5 +
3 files changed, 9 insertions(+)
Thanks,
On 3/31/24 00:07, Michael Tokarev wrote:
A few cleanups and fixes for linux-user/syscall:do_setsockopt().
Michael Tokarev (4):
linux-user/syscall: do_setsockopt: fix SOL_ALG.ALG_SET_KEY
linux-user/syscall: do_setsockopt(): make ip_mreq local to the place
it is used and inline
The copy back to siginfo_t should be conditional only on arg3,
not the specific values that might have been written.
The copy back to rusage was missing entirely.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2262
Signed-off-by: Richard Henderson
---
linux-user/syscall.c | 22
On Fri, Apr 05, 2024 at 11:40:56AM +0800, Wei Wang wrote:
> Before loading the guest states, ensure that the preempt channel has been
> ready to use, as some of the states (e.g. via virtio_load) might trigger
> page faults that will be handled through the preempt channel. So yield to
> the main
On Fri, 5 Apr 2024 at 14:07, Michael S. Tsirkin wrote:
>
> On Fri, Apr 05, 2024 at 01:54:46PM +0300, Manos Pitsidianakis wrote:
> > ping
>
> confused at this point.
> Do you mind sending a patchset with everything in the correct order?
> Tag it PATCH repost so people know nothing changed.
>
On 4/5/24 08:02, Peter Maydell wrote:
When we do an AT address translation operation, the page table walk
is supposed to be performed in the context of the EL we're doing the
walk for, so for instance an AT S1E2R walk is done for EL2. In the
pseudocode an EL is passed to AArch64.AT(), which
On Fri, Apr 05, 2024 at 06:44:52PM +0100, Jonathan Cameron wrote:
> On Fri, 5 Apr 2024 12:07:45 -0400
> Gregory Price wrote:
>
> > 3. (C) Upon Device receiving Release Dynamic Capacity Request
> >a. check for a pending release request. If exists, error.
>
> Not sure that's necessary - can
When we do an AT address translation operation, the page table walk
is supposed to be performed in the context of the EL we're doing the
walk for, so for instance an AT S1E2R walk is done for EL2. In the
pseudocode an EL is passed to AArch64.AT(), which calls
SecurityStateAtEL() to find the
On 4/5/24 03:15, Philippe Mathieu-Daudé wrote:
Previous commits replaced them by translator_ld* calls.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu_ldst.h | 10 --
1 file changed, 10 deletions(-)
Thanks, queued.
r~
diff --git a/include/exec/cpu_ldst.h
From: Zhu Yangyang
Coroutines are not supposed to block. Instead, they should yield.
The client performs TLS upgrade outside of an AIOContext, during
synchronous handshake; this still requires g_main_loop. But the
server responds to TLS upgrade inside a coroutine, so a nested
g_main_loop is
On Fri, 5 Apr 2024 12:07:45 -0400
Gregory Price wrote:
> On Fri, Apr 05, 2024 at 01:27:19PM +0100, Jonathan Cameron wrote:
> > On Wed, 3 Apr 2024 14:16:25 -0400
> > Gregory Price wrote:
> >
> > A few follow up comments.
> >
> > >
> > > > +error_setg(errp, "no valid extents to
On Fri, 15 Mar 2024 10:29:07 +0800
Shiyang Ruan wrote:
> 在 2024/2/14 0:51, Jonathan Cameron 写道:
> >
> >> +
> >> +void cxl_event_handle_record(struct cxl_memdev *cxlmd,
> >> + enum cxl_event_log_type type,
> >> + enum cxl_event_type event_type,
> >>
01.04.2024 09:02, Michael Tokarev:
Anyone can guess why this rather trivial and obviously correct patch causes
segfaults
in a few tests in staging-7.2 - when run in tcg mode, namely:
pxe-test
migration-test
boot-serial-test
bios-tables-test
vmgenid-test
cdrom-test
When
On 4/5/24 02:53, Nicholas Piggin wrote:
Some TLB flush operations can flush other CPUs. The problem with this
is they used non-synced variants of flushes (i.e., that return
before the destination has completed the flush). Since all TLB flush
users need the _synced variants, and that last user
On 4/5/24 02:53, Nicholas Piggin wrote:
These are no longer used.
tlb_flush_all_cpus: removed by previous commit.
tlb_flush_page_all_cpus: removed by previous commit.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used.
tlb_flush_page_by_mmuidx_all_cpus: never used.
On Mon, 1 Apr 2024 17:00:50 +0100
Jonathan Cameron via wrote:
> On Thu, 28 Mar 2024 06:24:24 +
> "Xingtao Yao (Fujitsu)" wrote:
>
> > Jonathan
> >
> > thanks for your reply!
> >
> > > -Original Message-
> > > From: Jonathan Cameron
> > > Sent: Wednesday, March 27, 2024 9:28 PM
On Fri, Apr 05, 2024 at 01:27:19PM +0100, Jonathan Cameron wrote:
> On Wed, 3 Apr 2024 14:16:25 -0400
> Gregory Price wrote:
>
> A few follow up comments.
>
> >
> > > +error_setg(errp, "no valid extents to send to process");
> > > +return;
> > > +}
> > > +
> >
> > I'm
On 4/5/24 11:04 AM, Eugenio Perez Martin wrote:
On Fri, Apr 5, 2024 at 3:59 PM Jonah Palmer wrote:
On 4/4/24 12:33 PM, Eugenio Perez Martin wrote:
On Thu, Apr 4, 2024 at 4:42 PM Jonah Palmer wrote:
On 4/4/24 7:35 AM, Eugenio Perez Martin wrote:
On Wed, Apr 3, 2024 at 6:51 PM Jonah
On Fri, Apr 5, 2024 at 3:20 PM Wafer wrote:
>
> If a virtio-net device has the VIRTIO_NET_F_MRG_RXBUF feature
> but not the VIRTIO_RING_F_INDIRECT_DESC feature,
> 'VirtIONetQueue->rx_vq' will use the merge feature
> to store data in multiple 'elems'.
> The 'num_buffers' in the virtio header
On Fri, Apr 5, 2024 at 3:59 PM Jonah Palmer wrote:
>
>
>
> On 4/4/24 12:33 PM, Eugenio Perez Martin wrote:
> > On Thu, Apr 4, 2024 at 4:42 PM Jonah Palmer wrote:
> >>
> >>
> >>
> >> On 4/4/24 7:35 AM, Eugenio Perez Martin wrote:
> >>> On Wed, Apr 3, 2024 at 6:51 PM Jonah Palmer
> >>> wrote:
>
On Fri, Apr 05, 2024 at 05:10:16PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 04.04.24 04:42, Eric Blake wrote:
> > From: Zhu Yangyang
> >
> > Coroutines are not supposed to block. Instead, they should yield.
> >
> > The client performs TLS upgrade outside of an AIOContext, during
> >
On Fri, 5 Apr 2024 at 08:55, Zack Buhman wrote:
>
> The saturation arithmetic logic in helper_macw is not correct.
>
> I tested and verified this behavior on a SH7091, the general pattern
> is a code sequence such as:
>
> sets
>
> mov.l _mach,r2
> lds r2,mach
>
Het Gala writes:
> On 27/03/24 2:37 am, Fabiano Rosas wrote:
>> Het Gala writes:
>>
>> Some comments, mostly just thinking out loud...
>>
>>> For --> migrate
>>> //
>>> //O:/...
>>>
>>> For --> validate
>>> ///O:/O:/
>>> /O:/O:/...
>> Do we need an optional 'capability' element? I'm not
On Fri, 29 Mar 2024 at 17:44, Arnaud Minier
wrote:
>
> This patch adds the STM32L4x5 USART
> (Universal Synchronous/Asynchronous Receiver/Transmitter)
> device and is part of a series implementing the
> STM32L4x5 with a few peripherals.
>
> It implements the necessary functionalities to
On Fri, 29 Mar 2024 at 17:45, Arnaud Minier
wrote:
>
> Test:
> - read/write from/to the usart registers
> - send/receive a character/string over the serial port
>
> Signed-off-by: Arnaud Minier
> Signed-off-by: Inès Varhol
> ---
Reviewed-by: Peter Maydell
thanks
-- PMM
On Thu, 4 Apr 2024 at 17:36, Pierre-Clément Tosi wrote:
>
> EL2 accesses to CNTPOFF_EL2 should only ever trap to EL3 if EL3 is
> present, as described by the reference manual (for MRS):
>
> /* ... */
> elsif PSTATE.EL == EL2 then
> if Halted() && HaveEL(EL3) && /*...*/ then
>
On 04.04.24 04:42, Eric Blake wrote:
From: Zhu Yangyang
Coroutines are not supposed to block. Instead, they should yield.
The client performs TLS upgrade outside of an AIOContext, during
synchronous handshake; this still requires g_main_loop. But the
server responds to TLS upgrade inside a
On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote:
>
> This patch set implements FEAT_NMI and FEAT_GICv3_NMI for ARMv8. These
> introduce support for a new category of interrupts in the architecture
> which we can use to provide NMI like functionality.
I think I'm now done with review on this
On Fri, 5 Apr 2024 00:07:06 +
"Ho-Ren (Jack) Chuang" wrote:
> The current implementation treats emulated memory devices, such as
> CXL1.1 type3 memory, as normal DRAM when they are emulated as normal memory
> (E820_TYPE_RAM). However, these emulated devices have different
> characteristics
On 4/4/24 12:33 PM, Eugenio Perez Martin wrote:
On Thu, Apr 4, 2024 at 4:42 PM Jonah Palmer wrote:
On 4/4/24 7:35 AM, Eugenio Perez Martin wrote:
On Wed, Apr 3, 2024 at 6:51 PM Jonah Palmer wrote:
On 4/3/24 6:18 AM, Eugenio Perez Martin wrote:
On Thu, Mar 28, 2024 at 5:22 PM Jonah
On Fri, 5 Apr 2024 00:07:05 +
"Ho-Ren (Jack) Chuang" wrote:
> Since different memory devices require finding, allocating, and putting
> memory types, these common steps are abstracted in this patch,
> enhancing the scalability and conciseness of the code.
>
> Signed-off-by: Ho-Ren (Jack)
On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote:
>
> A PE that implements FEAT_NMI and FEAT_GICv3 also implements
> FEAT_GICv3_NMI. A PE that does not implement FEAT_NMI, does not implement
> FEAT_GICv3_NMI
This is true but not really relevant here -- FEAT_GICv3_NMI
is not "NMI support in the
On 13.03.24 18:28, Vladimir Sementsov-Ogievskiy wrote:
Hi all! The main patch is 04, please look at it for description and
diagram.
v4: add t-b by Fiona
add r-b by Fiona to 02-05 (patch 01 still lack an r-b)
05: fix copyrights and subject in the test
04: since 9.0 --> since 9.1
Don't send zero length packets in virtio_net_flush_tx().
Reproducer from https://gitlab.com/qemu-project/qemu/-/issues/1451
creates small packet (1 segment, len = 10 == n->guest_hdr_len),
destroys queue.
"if (n->host_hdr_len != n->guest_hdr_len)" is triggered, if body creates
zero length/zero
On Wed, 3 Apr 2024 at 11:18, Jinjie Ruan wrote:
>
> Add a property has-nmi to the GICv3 device, and use this to set
> the NMI bit in the GICD_TYPER register. This isn't visible to
> guests yet because the property defaults to false and we won't
> set it in the board code until we've landed all of
If a virtio-net device has the VIRTIO_NET_F_MRG_RXBUF feature
but not the VIRTIO_RING_F_INDIRECT_DESC feature,
'VirtIONetQueue->rx_vq' will use the merge feature
to store data in multiple 'elems'.
The 'num_buffers' in the virtio header indicates how many elements are merged.
If the value of
On 04.04.24 12:11, Alexander Ivanov wrote:
If a blockcommit is aborted the base image remains in RW mode, that leads
to a fail of subsequent live migration.
How to reproduce:
$ virsh snapshot-create-as vm snp1 --disk-only
*** write something to the disk inside the guest ***
$ virsh
Previous commits replaced them by translator_ld* calls.
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu_ldst.h | 10 --
1 file changed, 10 deletions(-)
diff --git a/include/exec/cpu_ldst.h b/include/exec/cpu_ldst.h
index eb8f3f0595..85ca104dc9 100644
---
On Fri, Apr 5, 2024 at 12:25 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Cc: Edgar E. Iglesias
> Signed-off-by: Richard Henderson
>
Reviewed-by: Edgar E. Iglesias
> ---
> target/microblaze/translate.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
>
> diff
On Fri, Apr 5, 2024 at 12:25 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Cc: Edgar E. Iglesias
> Signed-off-by: Richard Henderson
>
Reviewed-by: Edgar E. Iglesias
> ---
> target/cris/translate.c | 1 -
> target/cris/translate_v10.c.inc | 30
On 5/4/24 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Michael Rolnik
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On Fri, Apr 5, 2024 at 12:25 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> Cc: Edgar E. Iglesias
> Signed-off-by: Richard Henderson
>
Reviewed-by: Edgar E. Iglesias
> ---
> target/cris/translate.c | 25 -
> 1 file changed, 8 insertions(+), 17
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Yoshinori Sato
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
Some TLB flush operations can flush other CPUs. The problem with this
is they used non-synced variants of flushes (i.e., that return
before the destination has completed the flush). Since all TLB flush
users need the _synced variants, and that last user (ppc) of the
non-synced flush was buggy,
With mttcg, broadcast tlbie instructions do not wait until other vCPUs
have been kicked out of TCG execution before they complete (including
necessary subsequent tlbsync, etc., instructions). This is contrary to
the ISA, and it permits other vCPUs to use translations after the TLB
flush. For
These are no longer used.
tlb_flush_all_cpus: removed by previous commit.
tlb_flush_page_all_cpus: removed by previous commit.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used.
tlb_flush_page_by_mmuidx_all_cpus: never used.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used, thus:
ppc's broadcast tlb flushe must ensure all vCPUs have invalidated
their TLBs when the tlbie sequence completes. This is not true in
the current TCG implementation, due to async_run_on_cpu() returning
before the remote CPU runs the job.
Fixing ppc requires moving to async_safe_run_on_cpu(),
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/microblaze/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 1 -
target/cris/translate_v10.c.inc | 30 +-
2 files changed, 9 insertions(+), 22 deletions(-)
Nice.
Reviewed-by: Philippe
On 5/4/24 12:24, Richard Henderson wrote:
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/4/24 12:24, Richard Henderson wrote:
Replace translator_fake_ldb, which required multiple calls,
with translator_fake_ld, which can take all data at once.
Signed-off-by: Richard Henderson
---
include/exec/translator.h| 8
accel/tcg/translator.c | 5 ++---
On 5/4/24 12:24, Richard Henderson wrote:
We have eliminated most uses of this hook. Reduce
further by allowing the hook to handle only the
special cases, returning false for normal processing.
Signed-off-by: Richard Henderson
---
include/exec/translator.h| 2 +-
On 5/4/24 12:24, Richard Henderson wrote:
Almost all of the disas_log implementations are identical.
Unify them within translator_loop.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 9 -
target/alpha/translate.c | 9 -
On 5/4/24 12:24, Richard Henderson wrote:
We do not need to separately record the start of the TB.
Signed-off-by: Richard Henderson
---
include/qemu/plugin.h | 1 -
accel/tcg/plugin-gen.c | 3 +--
plugins/api.c | 3 ++-
3 files changed, 3 insertions(+), 4 deletions(-)
On 5/4/24 12:24, Richard Henderson wrote:
Do not allow translation to proceed beyond one insn with mmio,
as we will not be caching the TranslationBlock.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 4
1 file changed, 4 insertions(+)
Reviewed-by: Philippe
On 5/4/24 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/translator.h| 5 +++--
accel/tcg/translator.c | 2 +-
target/s390x/tcg/translate.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé
On 5/4/24 12:24, Richard Henderson wrote:
While there are other methods that could be used to replace
TARGET_PAGE_MASK, the function is not really required outside
the context of target-specific translation.
This makes the header usable by target independent code.
Signed-off-by: Richard
On 5/4/24 12:24, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 18 +-
accel/tcg/translator.c| 15 ---
target/hexagon/translate.c| 1 +
target/microblaze/translate.c | 1 +
target/nios2/translate.c
On Mon, 25 Mar 2024 12:02:30 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Before the change, the QMP interface used for add/release DC extents
> only allows to release an extent whose DPA range is contained by a single
> accepted extent in the device.
>
> With the change, we relax the
On Mon, 25 Mar 2024 12:02:29 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> With the change, we extend the extent release mailbox command processing
> to allow more flexible release. As long as the DPA range of the extent to
> release is covered by accepted extent(s) in the device, the
On Mon, 25 Mar 2024 12:02:28 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> All dpa ranges in the DC regions are invalid to access until an extent
Let's be more consistent for commit logs and use DPA DC HPA etc all
caps. It's a bit of a mixture in this series at the moment.
> covering
On Wed, 3 Apr 2024 14:16:25 -0400
Gregory Price wrote:
A few follow up comments.
> On Mon, Mar 25, 2024 at 12:02:27PM -0700, nifan@gmail.com wrote:
> > From: Fan Ni
> >
> > To simulate FM functionalities for initiating Dynamic Capacity Add
> > (Opcode 5604h) and Dynamic Capacity Release
On Mon, 25 Mar 2024 12:02:27 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> To simulate FM functionalities for initiating Dynamic Capacity Add
> (Opcode 5604h) and Dynamic Capacity Release (Opcode 5605h) as in CXL spec
> r3.1 7.6.7.6.5 and 7.6.7.6.6, we implemented two QMP interfaces to
On Mon, 25 Mar 2024 12:02:26 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Per CXL spec 3.1, two mailbox commands are implemented:
> Add Dynamic Capacity Response (Opcode 4802h) 8.2.9.9.9.3, and
> Release Dynamic Capacity (Opcode 4803h) 8.2.9.9.9.4.
>
> For the process of the above two
On Thu, 4 Apr 2024 13:32:23 +
Jørgen Hansen wrote:
Hi Jørgen,
> > +static CXLRetCode cmd_dcd_add_dyn_cap_rsp(const struct cxl_cmd *cmd,
> > + uint8_t *payload_in,
> > + size_t len_in,
> > +
On Mon, 25 Mar 2024 12:02:25 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add dynamic capacity extent list representative to the definition of
> CXLType3Dev and implement get DC extent list mailbox command per
> CXL.spec.3.1:.8.2.9.9.9.2.
>
> Signed-off-by: Fan Ni
One really minor
On Fri, Apr 05, 2024 at 01:54:46PM +0300, Manos Pitsidianakis wrote:
> ping
confused at this point.
Do you mind sending a patchset with everything in the correct order?
Tag it PATCH repost so people know nothing changed.
Thanks!
--
MST
On Mon, 25 Mar 2024 12:02:24 -0700
nifan@gmail.com wrote:
> From: Fan Ni
>
> Add (file/memory backed) host backend, all the dynamic capacity regions
> will share a single, large enough host backend.
This doesn't parse. I suggests splitting it into 2 sentences.
Add (file/memory backend)
ping
On Sun, 24 Mar 2024 12:04, Manos Pitsidianakis
wrote:
This is a logic fix for the error handling in the TX/RX virt queue
handlers. A potential invalid address dereference was reported and fixed
by Zheyu Ma in <20240322110827.568412-1-zheyum...@gmail.com>. This patch
moves the invalid
ping
On Fri, 22 Mar 2024 13:08, Zheyu Ma wrote:
This patch improves error handling in virtio_snd_handle_tx_xfer()
and virtio_snd_handle_rx_xfer() in the VirtIO sound driver. Previously,
'goto' statements were used for error paths, leading to unnecessary
processing and potential null pointer
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 1 -
target/cris/translate_v10.c.inc | 30 +-
2 files changed, 9 insertions(+), 22 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index
Signed-off-by: Richard Henderson
---
include/exec/translator.h| 5 +++--
accel/tcg/translator.c | 2 +-
target/s390x/tcg/translate.c | 2 +-
3 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/include/exec/translator.h b/include/exec/translator.h
index 185ab5c374..65d0c6489a
Signed-off-by: Richard Henderson
---
include/tcg/tcg.h | 1 +
accel/tcg/plugin-gen.c | 1 +
2 files changed, 2 insertions(+)
diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h
index 135e36d729..2a1c080bab 100644
--- a/include/tcg/tcg.h
+++ b/include/tcg/tcg.h
@@ -537,6 +537,7 @@ struct
Signed-off-by: Richard Henderson
---
target/i386/tcg/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 796180f085..d0ba81eb6d 100644
--- a/target/i386/tcg/translate.c
+++
While there are other methods that could be used to replace
TARGET_PAGE_MASK, the function is not really required outside
the context of target-specific translation.
This makes the header usable by target independent code.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 2 ++
Reorg translator_access into translator_ld, with a more
memcpy-ish interface. If both pages are in ram, do not
go through the caller's slow path.
Assert that the access is within the two pages that we are
prepared to protect, per TranslationBlock. Allow access
prior to pc_first, so long as it
Cc: Yoshinori Sato
Signed-off-by: Richard Henderson
---
target/rx/translate.c | 27 ++-
1 file changed, 14 insertions(+), 13 deletions(-)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 92fb2b43ad..9b81cf20b3 100644
--- a/target/rx/translate.c
+++
Do not allow translation to proceed beyond one insn with mmio,
as we will not be caching the TranslationBlock.
Signed-off-by: Richard Henderson
---
accel/tcg/translator.c | 4
1 file changed, 4 insertions(+)
diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c
index
Cc: Michael Rolnik
Signed-off-by: Richard Henderson
---
target/avr/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 6df93d4c77..2d51892115 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@
Cc: Edgar E. Iglesias
Signed-off-by: Richard Henderson
---
target/cris/translate.c | 25 -
1 file changed, 8 insertions(+), 17 deletions(-)
diff --git a/target/cris/translate.c b/target/cris/translate.c
index b5410189d4..bb2d6612ba 100644
--- a/target/cris/translate.c
Based-on: 20240404230611.21231-1-richard.hender...@linaro.org
("[PATCH v2 00/21] Rewrite plugin code generation")
While I was trying to debug something the other week, I noticed
that hppa_cpu_get_phys_page_debug was not using the same cpu state
as the translator, which meant that the disassembler
Cc: Max Filippov
Signed-off-by: Richard Henderson
---
target/xtensa/translate.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index 42109d33ad..75b7bfda4c 100644
--- a/target/xtensa/translate.c
+++
The ilen value extracted from ex_value is the length of the
EXECUTE instruction itself, and so is the increment to the pc.
However, the length of the synthetic insn is located in the
opcode like all other instructions.
Cc: qemu-s3...@nongnu.org
Signed-off-by: Richard Henderson
---
Copy data out of a completed translation. This will be used
for both plugins and disassembly.
Signed-off-by: Richard Henderson
---
include/exec/translator.h | 23
accel/tcg/translator.c| 55 +++
2 files changed, 78 insertions(+)
diff
We have eliminated most uses of this hook. Reduce
further by allowing the hook to handle only the
special cases, returning false for normal processing.
Signed-off-by: Richard Henderson
---
include/exec/translator.h| 2 +-
accel/tcg/translator.c | 5 ++---
target/hppa/translate.c
We don't need to allocate plugin context at startup,
we can wait until we actually use it.
Signed-off-by: Richard Henderson
---
accel/tcg/plugin-gen.c | 36
tcg/tcg.c | 11 ---
2 files changed, 20 insertions(+), 27 deletions(-)
diff
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