[PATCH v3 06/19] range: Introduce range_get_last_bit()

This helper get the highest 1 bit position of the upper bound. If the range is empty or upper bound is zero, -1 is returned. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/qemu/range.h | 11 +++ 1 file changed, 11 insertions(+) diff --git a/include/qemu/range

[PATCH v3 03/19] backends/iommufd: Introduce abstract HostIOMMUDeviceIOMMUFD device

HostIOMMUDeviceIOMMUFD represents a host IOMMU device under iommufd backend. Currently it contains public iommufd handle and device id which will be passed to vIOMMU to allocate/free ioas, hwpt, etc. When nested translation is supported in future, vIOMMU will request iommufd related operations li

[PATCH v3 17/19] intel_iommu: Extract out vtd_cap_init() to initialize cap/ecap

Extract cap/ecap initialization in vtd_cap_init() to make code cleaner. No functional change intended. Reviewed-by: Eric Auger Signed-off-by: Zhenzhong Duan --- hw/i386/intel_iommu.c | 93 --- 1 file changed, 51 insertions(+), 42 deletions(-) diff --git

[PATCH v3 12/19] vfio: Introduce VFIOIOMMUClass::hiod_typename attribute

Initialize attribute VFIOIOMMUClass::hiod_typename based on VFIO backend type. This attribute will facilitate HostIOMMUDevice creation in vfio_attach_device(). Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-container-base.h | 3 +++ hw/vfio/container.c

[PATCH v3 08/19] backends/iommufd: Introduce helper function iommufd_backend_get_device_info()

Introduce a helper function iommufd_backend_get_device_info() to get host IOMMU related information through iommufd uAPI. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- include/sysemu/iommufd.h | 4 backends/iommufd.c | 24 +++- 2

[PATCH v3 14/19] hw/pci: Introduce helper function pci_device_get_iommu_bus_devfn()

Extract out pci_device_get_iommu_bus_devfn() from pci_device_iommu_address_space() to facilitate implementation of pci_device_[set|unset]_iommu_device() in following patch. No functional change intended. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Nicolin Chen Signed-off-by: Zhe

[PATCH v3 05/19] backends/host_iommu_device: Introduce HostIOMMUDeviceCaps

HostIOMMUDeviceCaps's elements map to the host IOMMU's capabilities. Different platform IOMMU can support different elements. Currently only two elements, type and aw_bits, type hints the host platform IOMMU type, i.e., INTEL vtd, ARM smmu, etc; aw_bits hints host IOMMU address width. Introduce .

[PATCH v3 19/19] intel_iommu: Check compatibility with host IOMMU capabilities

If check fails, host device (either VFIO or VDPA device) is not compatible with current vIOMMU config and should not be passed to guest. Only aw_bits is checked for now, we don't care other capabilities before scalable modern mode is introduced. Signed-off-by: Yi Liu Signed-off-by: Zhenzhong Dua

[PATCH v3 18/19] intel_iommu: Implement [set|unset]_iommu_device() callbacks

From: Yi Liu Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU. In set call, a new structure VTDHostIOMMUDevice which holds a reference to HostIOMMUDevice is stored in hash table indexed by PCI BDF. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw

[PATCH v3 13/19] vfio: Create host IOMMU device instance

Create host IOMMU device instance in vfio_attach_device() and call .realize() to initialize it further. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 1 + hw/vfio/common.c | 18 +- 2 files changed, 18 insertions(+)

[PATCH v3 07/19] vfio/container: Implement HostIOMMUDeviceClass::realize() handler

Utilize range_get_last_bit() to get host IOMMU address width and package it in HostIOMMUDeviceCaps for query with .check_cap(). Signed-off-by: Zhenzhong Duan --- hw/vfio/container.c | 29 + 1 file changed, 29 insertions(+) diff --git a/hw/vfio/container.c b/hw/vfio/c

[PATCH v3 15/19] hw/pci: Introduce pci_device_[set|unset]_iommu_device()

From: Yi Liu pci_device_[set|unset]_iommu_device() call pci_device_get_iommu_bus_devfn() to get iommu_bus->iommu_ops and call [set|unset]_iommu_device callback to set/unset HostIOMMUDevice for a given PCI device. Signed-off-by: Yi Liu Signed-off-by: Yi Sun Signed-off-by: Nicolin Chen Signed-o

[PATCH v3 16/19] vfio/pci: Pass HostIOMMUDevice to vIOMMU

With HostIOMMUDevice passed, vIOMMU can check compatibility with host IOMMU, call into IOMMUFD specific methods, etc. Originally-by: Yi Liu Signed-off-by: Nicolin Chen Signed-off-by: Yi Sun Signed-off-by: Zhenzhong Duan --- hw/vfio/pci.c | 20 +++- 1 file changed, 15 insertion

[PATCH v3 09/19] vfio/iommufd: Implement HostIOMMUDeviceClass::realize() handler

It calls iommufd_backend_get_device_info() to get host IOMMU related information and translate it into HostIOMMUDeviceCaps for query with .check_cap(). Introduce macro VTD_MGAW_FROM_CAP to get MGAW which equals to (aw_bits - 1). Signed-off-by: Zhenzhong Duan --- include/hw/i386/intel_iommu.h |

[PATCH v3 10/19] vfio/container: Implement HostIOMMUDeviceClass::check_cap() handler

Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- hw/vfio/container.c | 12 1 file changed, 12 insertions(+) diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 863eec3943..3683487605 100644 --- a/hw/vfio/container.c +++ b/hw/vfio/container.c @@ -1164,11 +11

[PATCH v3 11/19] backends/iommufd: Implement HostIOMMUDeviceClass::check_cap() handler

Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- backends/iommufd.c | 18 ++ 1 file changed, 18 insertions(+) diff --git a/backends/iommufd.c b/backends/iommufd.c index d61209788a..28faec528e 100644 --- a/backends/iommufd.c +++ b/backends/iommufd.c @@ -233,6 +233

[PATCH v3 04/19] vfio/iommufd: Introduce HostIOMMUDeviceIOMMUFDVFIO device

HostIOMMUDeviceIOMMUFDVFIO represents a host IOMMU device under VFIO iommufd backend. It will be created during VFIO device attaching and passed to vIOMMU. It includes a link to VFIODevice so that we can do VFIO device specific operations, i.e., [at/de]taching hwpt, etc. Signed-off-by: Zhenzhong

[PATCH v3 00/19] Add a host IOMMU device abstraction to check with vIOMMU

Hi, The most important change in this version is instroducing a common HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface between vIOMMU and HostIOMMUDevice. HostIOMMUDeviceClass::realize() is introduced to initialize HostIOMMUDeviceCaps and other fields of HostIOMMUDevice varia

[PATCH v3 02/19] vfio/container: Introduce HostIOMMUDeviceLegacyVFIO device

HostIOMMUDeviceLegacyVFIO represents a host IOMMU device under VFIO legacy container backend. It includes a link to VFIODevice. Suggested-by: Eric Auger Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan --- include/hw/vfio/vfio-common.h | 12 hw/vfio/container.c

[PATCH v3 01/19] backends: Introduce HostIOMMUDevice abstract

Introduce HostIOMMUDevice as an abstraction of host IOMMU device. Introduce .realize() to initialize HostIOMMUDevice further after instance init. Introduce a macro CONFIG_HOST_IOMMU_DEVICE to define the usage for VFIO, and VDPA in the future. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzh

[PULL 6/9] backends/cryptodev-builtin: Fix local_error leaks

From: Li Zhijian via It seems that this error does not need to be propagated to the upper, directly output the error to avoid the leaks Closes: https://gitlab.com/qemu-project/qemu/-/issues/2283 Fixes: 2fda101de07 ("virtio-crypto: Support asynchronous mode") Signed-off-by: Li Zhijian Reviewed-b

[PULL 4/9] scripts/checkpatch: Avoid author email mangled by qemu-*@nongnu.org

From: Philippe Mathieu-Daudé Commit f5177798d8 ("scripts: report on author emails that are mangled by the mailing list") added a check for qemu-devel@ list, extend the regexp to cover more such qemu-trivial@, qemu-block@ and qemu-ppc@. Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael

[PULL 0/9] Trivial patches for 2024-04-29

The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479: Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging (2024-04-26 15:28:13 -0700) are available in the Git repository at: https://gitlab.com/mjt0k/qemu.git tags/pull-trivial-patches for you to

[PULL 2/9] target/s390x/cpu_models: Rework the output of "-cpu help"

From: Thomas Huth Printing an "s390x" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's

[PULL 9/9] checkpatch.pl: forbid strerrorname_np()

From: Daniel Henrique Barboza Commit d424db2354 removed an instance of strerrorname_np() because it was breaking building with musl libc. A recent RISC-V patch ended up re-introducing it again by accident. Put this function in the baddies list in checkpatch.pl to avoid this situation again. This

[PULL 5/9] scripts/checkpatch: Do not use mailmap

From: Philippe Mathieu-Daudé The .mailmap file fixes mistake we already did. Do not use it when running checkpatch.pl, otherwise we might commit the very same mistakes. Reported-by: Peter Maydell Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Michael Tokarev Signed-off-by: Michael Tokarev

[PULL 1/9] target/i386/cpu: Remove "x86" prefix from the CPU list

From: Thomas Huth Printing an "x86" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's si

[PULL 8/9] target/riscv/kvm: remove sneaky strerrorname_np() instance

From: Daniel Henrique Barboza Commit d424db2354 excluded some strerrorname_np() instances because they break musl libc builds. Another instance happened to slip by via commit d4ff3da8f4. Remove it before it causes trouble again. Fixes: d4ff3da8f4 (target/riscv/kvm: initialize 'vlenb' via get-re

[PULL 3/9] target/ppc/cpu_init: Remove "PowerPC" prefix from the CPU list

From: Thomas Huth Printing a "PowerPC" in front of each CPU name is not helpful at all: It is confusing for the users since they don't know whether they have to specify these letters for the "-cpu" parameter, too, and it also takes some precious space in the dense output of the CPU entries. Let's

[PULL 7/9] target/loongarch/cpu.c: typo fix: expection

Fixes: 1590154ee437 ("target/loongarch: Fix qemu-system-loongarch64 assert failed with the option '-d int'") Signed-off-by: Michael Tokarev Reviewed-by: Richard Henderson --- target/loongarch/cpu.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/loongarch/cpu.c b/targ

Re: [PATCH v2 2/4] hw/arm/sbsa-ref: Force CPU generic timer to 62.5MHz

W dniu 26.04.2024 o 14:29, Peter Maydell pisze: The default frequency used by the 'max' CPU is about to change, so make the sbsa-ref board force the CPU frequency to the value which the firmware expects. Newer versions of TF-A will read the frequency from the CPU's CNTFRQ_EL0 register: https:

Re: [PATCH v4 1/1] hw/arm/sbsa-ref: Enable CPU cluster on ARM sbsa machine

W dniu 26.04.2024 o 18:06, Richard Henderson pisze: Isn't this basically what MPIDR_EL1 is supposed to indicate? We do not yet implement all of that in QEMU, but should. QEMU has socket/cluster/core/thread model which could map to aff3/aff2/aff1/aff0 (or aff0/1/2/3) of MPIDR_EL1 register, righ

Re: [PATCH v7 3/4] target/riscv: Expose sdtrig ISA extension

On Fri, Mar 15, 2024 at 5:02 AM Himanshu Chauhan wrote: > > This patch adds "sdtrig" in the ISA string when sdtrig extension is enabled. > The sdtrig extension may or may not be implemented in a system. Therefore, the >-cpu rv64,sdtrig= > option can be used to dynamically turn sdtrig e

[PATCH 2/3] target/ppc: Move VMX integer logical instructions to decodetree.

Moving the following instructions to decodetree specification: v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form The changes were verified by validating that the tcp ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-

[PATCH 1/3] target/ppc: Move VMX storage access instructions to decodetree

Moving the following instructions to decodetree specification : {l,st}ve{b,h,w}x, {l,st}v{x,xl}, lvs{l,r}: X-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured using the '-d in_

[PATCH 0/3] target/ppc: Moving VMX insns to decodetree

Moving VMX instructions of the following types to decodetree specification : storage access, integer logical & integer max/min. Chinmay Rath (3): target/ppc: Move VMX storage access instructions to decodetree target/ppc: Move VMX integer logical instructions to decodetree target/ppc: Move VM

[PATCH 3/3] target/ppc: Move VMX integer max/min instructions to decodetree.

Moving the following instructions to decodetree specification : v{max, min}{u, s}{b, h, w, d} : VX-form The changes were verified by validating that the tcg ops generated by those instructions remain the same, which were captured with the '-d in_asm,op' flag. Signed-off-by: Chinmay Rat

Re: [PATCH v7 2/4] target/riscv: Enable mcontrol6 triggers only when sdtrig is selected

On Fri, Mar 15, 2024 at 5:01 AM Himanshu Chauhan wrote: > > The mcontrol6 triggers are not defined in debug specification v0.13 > These triggers are defined in sdtrig ISA extension. > > This patch: >* Adds ext_sdtrig capability which is used to select mcontrol6 triggers >* Keeps the debug

Re: [PATCH v7 1/4] target/riscv: Check for valid itimer pointer before free

On Fri, Mar 15, 2024 at 5:01 AM Himanshu Chauhan wrote: > > Check if each element of array of pointers for itimer contains a non-null > pointer before freeing. > > Signed-off-by: Himanshu Chauhan Reviewed-by: Alistair Francis Alistair > --- > target/riscv/debug.c | 5 - > 1 file changed,

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH v3] target/riscv: raise an exception when CSRRS/CSRRC writes a read-only CSR

On Wed, Apr 3, 2024 at 5:10 PM Yu-Ming Chang via wrote: > > Both CSRRS and CSRRC always read the addressed CSR and cause any read side > effects regardless of rs1 and rd fields. Note that if rs1 specifies a register > holding a zero value other than x0, the instruction will still attempt to > wri

Re: [PATCH 12/12] tests/qtest/bios-tables-test.c: Enable basic testing for RISC-V

On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote: > > Add basic ACPI table testing for RISC-V. > > Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Alistair > --- > tests/qtest/bios-tables-test.c | 28 > 1 file changed, 28 insertions(+) > > diff --git a/tes

Re: [PATCH 11/12] tests/data/acpi/virt/riscv64: Add expected ACPI tables for RISC-V

On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote: > > Add expected ACPI tables for RISC-V so that bios-table-test can be > enabled for RISC-V. Can you detail where and how these files are generated/built? Alistair > > Signed-off-by: Sunil V L > --- > tests/data/acpi/virt/riscv64/APIC | Bin 0

Re: [PATCH 10/12] tests/data/acpi/rebuild-expected-aml.sh: Add RISC-V

On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote: > > Update the list of supported architectures to include RISC-V. > > Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Alistair > --- > tests/data/acpi/rebuild-expected-aml.sh | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-)

Re: [PATCH v4] target/riscv: Implement dynamic establishment of custom decoder

On Thu, Mar 14, 2024 at 7:23 PM Huang Tao wrote: > > In this patch, we modify the decoder to be a freely composable data > structure instead of a hardcoded one. It can be dynamically builded up > according to the extensions. > This approach has several benefits: > 1. Provides support for heterogen

Re: [PATCH 09/12] pc-bios/meson.build: Add support for RISC-V in unpack_edk2_blobs

On Fri, Mar 15, 2024 at 11:10 PM Sunil V L wrote: > > Update list of images supported in unpack_edk2_blobs to enable RISC-V > ACPI table testing. > > Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Alistair > --- > pc-bios/meson.build | 2 ++ > tests/qtest/meson.build | 3 +++ > 2

Re: [PATCH 08/12] meson.build: Add RISC-V to the edk2-target list

On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote: > > so that ACPI table test can be supported. > > Signed-off-by: Sunil V L Reviewed-by: Alistair Francis Alistair > --- > meson.build | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/meson.build b/meson.build > index b

Re: [PATCH 07/12] tests/data/acpi/virt: Move ACPI tables under aarch64

On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote: > > Since virt is a common machine name across architectures like ARM64 and > RISC-V, move existing ARM64 ACPI tables under aarch64 folder so that > RISC-V tables can be added under riscv64 folder in future. > > Signed-off-by: Sunil V L Reviewed-

Re: [PATCH 06/12] tests/qtest/bios-tables-test.c: Add support for arch in path

On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote: > > Since virt machine is common for multiple architectures, add "arch" in > the path to search expected AML files. Since the AML files are still > under old path, support both by searching with and without arch in the > path. > > Signed-off-by: Su

Re: [PATCH 05/12] qtest: bios-tables-test: Rename aarch64 tests with aarch64 in them

On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote: > > Existing AARCH64 virt test functions do not have AARCH64 in their name. > To add RISC-V virt related test cases, better to rename existing > functions to indicate they are ARM only. > > Signed-off-by: Sunil V L Reviewed-by: Alistair Francis

Re: [PATCH 04/12] tests/data/uefi-boot-images: Add RISC-V ISO image

On Fri, Mar 15, 2024 at 11:09 PM Sunil V L wrote: > > To test ACPI tables, edk2 needs to be booted with a disk image having > EFI partition. This image is created using UefiTestToolsPkg. Can we document exactly how this is generated? Alistair > > Signed-off-by: Sunil V L > --- > .../bios-tabl

Re: [PATCH v4] target/riscv: Implement dynamic establishment of custom decoder

On Thu, Mar 14, 2024 at 7:23 PM Huang Tao wrote: > > In this patch, we modify the decoder to be a freely composable data > structure instead of a hardcoded one. It can be dynamically builded up > according to the extensions. > This approach has several benefits: > 1. Provides support for heterogen

Re: [PATCH v3] target/riscv: Fix the element agnostic function problem

On Mon, Mar 25, 2024 at 12:18 PM Huang Tao wrote: > > In RVV and vcrypto instructions, the masked and tail elements are set to 1s > using vext_set_elems_1s function if the vma/vta bit is set. It is the element > agnostic policy. > > However, this function can't deal the big endian situation. This

Re: [PATCH v3 0/3] target/riscv: Support Zve32x and Zve64x extensions

On Thu, Mar 28, 2024 at 12:25 PM Jason Chien wrote: > > This patch series adds the support for Zve32x and Zvx64x and makes vector > registers visible in GDB if any of the V/Zve*/Zvk* extensions is enabled. > > v2: > Rebase onto riscv-to-apply.next (commit 385e575). > v3: > Spuash patch 2 i

Re: [PATCH v4] riscv: thead: Add th.sxstatus CSR emulation

On Mon, Apr 22, 2024 at 4:53 PM Christoph Müllner wrote: > > The th.sxstatus CSR can be used to identify available custom extension > on T-Head CPUs. The CSR is documented here: > > https://github.com/T-head-Semi/thead-extension-spec/blob/master/xtheadsxstatus.adoc > > An important property of

[RFC PATCH v3 07/18] hw/arm/smmuv3: Translate CD and TT using stage-2 table

According to ARM SMMU architecture specification (ARM IHI 0070 F.b), In "5.2 Stream Table Entry": [51:6] S1ContextPtr If Config[1] == 1 (stage 2 enabled), this pointer is an IPA translated by stage 2 and the programmed value must be within the range of the IAS. In "5.4.1 CD notes": The transla

[RFC PATCH v3 01/18] hw/arm/smmu-common: Add missing size check for stage-1

According to the SMMU architecture specification (ARM IHI 0070 F.b), in “3.4 Address sizes” The address output from the translation causes a stage 1 Address Size fault if it exceeds the range of the effective IPA size for the given CD. However, this check was missing. There is already a s

[RFC PATCH v3 06/18] hw/arm/smmu: Consolidate ASID and VMID types

ASID and VMID used to be uint16_t in the translation config, however, in other contexts they can be int as -1 in case of TLB invalidation, to represent all(don’t care). When stage-2 was added asid was set to -1 in stage-2 and vmid to -1 in stage-1 configs. However, that meant they were set as (6553

[RFC PATCH v3 12/18] hw/arm/smmu: Support nesting in the rest of commands

Some commands need rework for nesting, as they used to assume S1 and S2 are mutually exclusive: - CMD_TLBI_NH_ASID: Consider VMID if stage-2 is supported - CMD_TLBI_NH_ALL: Consider VMID if stage-2 is supported, otherwise invalidate everything, this required a new vmid invalidation function fo

[PULL 0/1] ufs queue

From: Jeuk Kim The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479: Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging (2024-04-26 15:28:13 -0700) are available in the Git repository at: https://gitlab.com/jeuk20.kim/qemu.git tags/pull-ufs-20

[PULL 1/1] hw/ufs: Fix buffer overflow bug

From: Jeuk Kim It fixes the buffer overflow vulnerability in the ufs device. The bug was detected by sanitizers. You can reproduce it by: cat << EOF |\ qemu-system-x86_64 \ -display none -machine accel=qtest -m 512M -M q35 -nodefaults -drive \ file=null-co://,if=none,id=disk0 -device ufs,id=ufs

[RFC PATCH v3 16/18] hw/arm/smmu: Refactor SMMU OAS

SMMUv3 OAS is hardcoded to 44 bits, for nested configurations that can be a problem as stage-2 might be shared with the CPU which might have different PARANGE, and according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. This patch doesn't cha

[RFC PATCH v3 17/18] hw/arm/smmuv3: Add property for OAS

Add property that sets the OAS of the SMMU, this in not used in this patch. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3-internal.h | 3 ++- hw/arm/smmuv3.c | 29 - include/hw/arm/smmuv3.h | 1 + 3 files changed, 31 insertions(+), 2 deletions(-) diff --

[RFC PATCH v3 04/18] hw/arm/smmu: Use enum for SMMU stage

Currently, translation stage is represented as an int, where 1 is stage-1 and 2 is stage-2, when nested is added, 3 would be confusing to represent nesting, so we use an enum instead. While keeping the same values, this is useful for: - Doing tricks with bit masks, where BIT(0) is stage-1 and BIT

[RFC PATCH v3 14/18] hw/arm/smmuv3: Support and advertise nesting

Everything is in place, add the last missing bits: - Handle fault checking according to the actual PTW event and not the the translation stage. - Consolidate parsing of STE cfg and setting translation stage. Advertise nesting if stage requested is "nested". Signed-off-by: Mostafa Saleh --- hw

[RFC PATCH v3 11/18] hw/arm/smmu: Support nesting in smmuv3_range_inval()

With nesting, we would need to invalidate IPAs without over-invalidating stage-1 IOVAs. This can be done by distinguishing IPAs in the TLBs by having ASID=-1. To achieve that, rework the invalidation for IPAs to have a separate function, while for IOVA invalidation ASID=-1 means invalidate for all

[RFC PATCH v3 10/18] hw/arm/smmu-common: Support nested translation

When nested translation is requested, do the following: - Translate stage-1 IPA using stage-2 to a physical address. - Translate stage-1 table walks using stage-2. - Combine both to create a single TLB entry using the logic introduced before. For stage-1 table translation, the spec (ARM IHI 007

[RFC PATCH v3 13/18] hw/arm/smmuv3: Support nested SMMUs in smmuv3_notify_iova()

IOMMUTLBEvent only understands IOVA, for stage-2 only SMMUs keep the implementation, while only notify for stage-1 invalidation in case of nesting. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3.c | 23 +++ hw/arm/trace-events | 2 +- 2 files changed, 16 insertions(+), 9

[RFC PATCH v3 09/18] hw/arm/smmu-common: Rework TLB lookup for nesting

In the previous patch, comine_tlb() was added which combines 2 TLB entries into one, which chooses the granule and level from the smallest entry. This means that a nested translation, an entry can be cached with the granule of stage-2 and not stage-1. However, the lookup for an IOVA in nested con

[RFC PATCH v3 15/18] hw/arm/smmuv3: Advertise S2FWB

QEMU doesn's support memory attributes, so FWB is NOP, this might change in the future if memory attributre would be supported. Signed-off-by: Mostafa Saleh --- hw/arm/smmuv3.c | 8 1 file changed, 8 insertions(+) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 88f6473d33..8a11e41

Re: [PATCH 1/1] target/riscv/kvm.c: Fix the hart bit setting of AIA

On Mon, Apr 15, 2024 at 4:53 PM Yong-Xuan Wang wrote: > > The hart bit setting is different with Linux AIA driver[1] when the number > of hart is power of 2. For example, when the guest has 4 harts, the > estimated result of AIA driver is 2, whereas we pass 3 to RISC-V/KVM. Since > only 2 bits are

[RFC PATCH v3 03/18] hw/arm/smmuv3: Fix encoding of CLASS in events

The SMMUv3 spec (ARM IHI 0070 F.b - 7.3 Event records) defines the class of events faults as: CLASS: The class of the operation that caused the fault: - 0b00: CD, CD fetch. - 0b01: TTD, Stage 1 translation table fetch. - 0b10: IN, Input address However, this value was not set and left as 0 which

[RFC PATCH v3 05/18] hw/arm/smmu: Split smmuv3_translate()

smmuv3_translate() does everything from STE/CD parsing to TLB lookup and PTW. Soon, when nesting is supported, stage-1 data (tt, CD) needs to be translated using stage-2. Split smmuv3_translate() to 3 functions: - smmu_translate(): in smmu-common.c, which does the TLB lookup, PTW, TLB insertio

[RFC PATCH v3 18/18] hw/arm/virt: Set SMMU OAS based on CPU PARANGE

Use the new SMMU property to make the SMMU OAS match the CPU PARANGE. That's according to SMMU manual ARM IHI 0070F.b: 6.3.6 SMMU_IDR5, OAS must match the system physical address size. Signed-off-by: Mostafa Saleh --- hw/arm/virt.c | 14 -- target/arm/cpu.h | 2 ++ target

[RFC PATCH v3 02/18] hw/arm/smmu: Fix IPA for stage-2 events

For the following events (ARM IHI 0070 F.b - 7.3 Event records): - F_TRANSLATION - F_ACCESS - F_PERMISSION - F_ADDR_SIZE If fault occurs at stage 2, S2 == 1 and: - If translating an IPA for a transaction (whether by input to stage 2-only configuration, or after successful stage 1 translation

[RFC PATCH v3 00/18] SMMUv3 nested translation support

Currently, QEMU supports emulating either stage-1 or stage-2 SMMUs but not nested instances. This patch series adds support for nested translation in SMMUv3, this is controlled by property “arm-smmuv3.stage=nested”, and advertised to guests as (IDR0.S1P == 1 && IDR0.S2P == 2) Main changes(architec

[RFC PATCH v3 08/18] hw/arm/smmu-common: Add support for nested TLB

This patch adds support for nested(combined) TLB entries. The main function combine_tlb() is not used here but in the next patches, but to simplify the patches it is introduced first. Main changes: 1) New entry added in the TLB, parent_perm, for nested TLB, holds the stage-2 permission, this ca

Re: [PATCH for-9.1 v3 0/2] target/riscv: set tval in breakpoints

On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza wrote: > > Hi, > > This new version has a change suggested by Richard in v2. No other > changes made. > > Changes from v2: > - patch 2: > - use tcg_constant_tl() instead of loading a temp and doing a > movi_tl() > - v2 link: > https://

Re: [PATCH for-9.1 v3 2/2] trans_privileged.c.inc: set (m|s)tval on ebreak breakpoint

On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza wrote: > > Privileged spec section 4.1.9 mentions: > > "When a trap is taken into S-mode, stval is written with > exception-specific information to assist software in handling the trap. > (...) > > If stval is written with a nonzero value whe

Re: [PATCH for-9.1 v3 1/2] target/riscv/debug: set tval=pc in breakpoint exceptions

On Wed, Apr 17, 2024 at 9:05 AM Daniel Henrique Barboza wrote: > > We're not setting (s/m)tval when triggering breakpoints of type 2 > (mcontrol) and 6 (mcontrol6). According to the debug spec section > 5.7.12, "Match Control Type 6": > > "The Privileged Spec says that breakpoint exceptions that o

Re: [PATCH v2 1/1] target/riscv/kvm: tolerate KVM disable ext errors

On Tue, Apr 23, 2024 at 3:15 AM Daniel Henrique Barboza wrote: > > Running a KVM guest using a 6.9-rc3 kernel, in a 6.8 host that has zkr > enabled, will fail with a kernel oops SIGILL right at the start. The > reason is that we can't expose zkr without implementing the SEED CSR. > Disabling zkr i

Re: [PATCH] target/riscv: change RISCV_EXCP_SEMIHOST exception number to 63

On Mon, Apr 22, 2024 at 11:59 PM Clément Léger wrote: > > The current semihost exception number (16) is a reserved number (range > [16-17]). The upcoming double trap specification uses that number for > the double trap exception. Since the privileged spec (Table 22) defines > ranges for custom use

[PULL v2 06/17] hw/loongarch: Init efi_boot_memmap table

The efi_system_table adds a efi_boot_memmap configuration table. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-7-gaos...@loongson.cn> --- hw/loongarch/boot.c | 40 + hw/loongarch/virt.c | 11 ++ incl

[PULL v2 08/17] hw/loongarch: Init efi_fdt table

The efi_system_table adds a efi_fdt configuration table. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-9-gaos...@loongson.cn> --- hw/loongarch/boot.c | 11 +++ hw/loongarch/virt.c | 6 ++ include/hw/loongarch/boot.h | 4 inc

[PULL v2 03/17] hw/loongarch: Add slave cpu boot_code

Load the slave CPU boot code at pflash0 and set the slave CPU elf_address to VIRT_FLASH0_BASE. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-4-gaos...@loongson.cn> --- hw/loongarch/boot.c | 62 - 1 file changed, 61

[PULL v2 12/17] hw/loongarch: fdt adds pch_pic Controller

fdt adds pch pic controller, we use 'loongson,pch-pic-1.0' See: https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-pic.c https://lore.kernel.org/r/20200528152757.1028711-4-jiaxun.y...@flygoat.com Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551

[PULL v2 07/17] hw/loongarch: Init efi_initrd table

The efi_system_table adds a efi_initrd configuration table. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-8-gaos...@loongson.cn> --- hw/loongarch/boot.c | 23 +-- include/hw/loongarch/boot.h | 9 + 2 files changed, 30 inse

[PULL v2 02/17] hw/loongarch: Add load initrd

we load initrd ramdisk after kernel_high address Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-3-gaos...@loongson.cn> --- hw/loongarch/boot.c | 28 +++- 1 file changed, 27 insertions(+), 1 deletion(-) diff --git a/hw/loongarch/boot.c

[PULL v2 15/17] hw/loongarch: fdt remove unused irqchip node

This patch removes the unused fdt irqchip node. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-16-gaos...@loongson.cn> --- hw/loongarch/virt.c | 31 +-- 1 file changed, 1 insertion(+), 30 deletions(-) diff --git a/hw/loongarch/virt

[PULL v2 11/17] hw/loongarch: fdt adds Extend I/O Interrupt Controller

fdt adds Extend I/O Interrupt Controller, we use 'loongson,ls2k2000-eiointc'. See: https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-eiointc.c https://lore.kernel.org/r/764e02d924094580ac0f1d15535f4b98308705c6.1683279769.git.zhoubin...@loongson.cn Signed-off-by: Song Gao R

[PULL v2 17/17] hw/loongarch: Add cells missing from rtc node

rtc node need interrupts and interrupt-parent cells. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-18-gaos...@loongson.cn> --- hw/loongarch/virt.c | 12 +--- 1 file changed, 9 insertions(+), 3 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loonga

[PULL v2 09/17] hw/loongarch: Fix fdt memory node wrong 'reg'

The right fdt memory node like [1], not [2] [1] memory@0 { device_type = "memory"; reg = <0x00 0x00 0x00 0x1000>; }; [2] memory@0 { device_type = "memory"; reg = <0x02 0x00 0x02 0x1000>; };

[PULL v2 16/17] hw/loongarch: Add cells missing from uart node

uart node need interrupts and interrupt-parent cells. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-17-gaos...@loongson.cn> --- hw/loongarch/virt.c | 9 +++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/hw/loongarch/virt.c b/hw/loongarch

[PULL v2 04/17] hw/loongarch: Add init_cmdline

Add init_cmline and set boot_info->a0, a1 Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-5-gaos...@loongson.cn> --- hw/loongarch/boot.c | 30 ++ include/hw/loongarch/virt.h | 2 ++ target/loongarch/cpu.h | 2 ++ 3 fil

[PULL v2 14/17] hw/loongarch: fdt adds pcie irq_map node

This patch adds pcie irq_map node for FDT. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-15-gaos...@loongson.cn> --- hw/loongarch/virt.c | 73 ++--- 1 file changed, 69 insertions(+), 4 deletions(-) diff --git a/hw/loon

[PULL v2 10/17] hw/loongarch: fdt adds cpu interrupt controller node

fdt adds cpu interrupt controller node, we use 'loongson,cpu-interrupt-controller'. See: https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongarch-cpu.c https://lore.kernel.org/r/20221114113824.1880-2-liupei...@loongson.cn Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id

[PULL v2 05/17] hw/loongarch: Init efi_system_table

Add init_systab and set boot_info->a2 Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <20240426091551.2397867-6-gaos...@loongson.cn> --- hw/loongarch/boot.c | 22 + include/hw/loongarch/boot.h | 48 + 2 files changed, 70 inse

[PULL v2 01/17] hw/loongarch: Move boot functions to boot.c

Move some boot functions to boot.c and struct loongarch_boot_info into struct LoongArchMachineState. Signed-off-by: Song Gao Reviewed-by: Bibo Mao Reviewed-by: Philippe Mathieu-Daudé Message-Id: <20240426091551.2397867-2-gaos...@loongson.cn> --- hw/loongarch/boot.c | 128 ++

[PULL v2 13/17] hw/loongarch: fdt adds pch_msi Controller

fdt adds pch msi controller, we use 'loongson,pch-msi-1.0'. See: https://github.com/torvalds/linux/blob/v6.7/drivers/irqchip/irq-loongson-pch-msi.c https://lore.kernel.org/r/20200528152757.1028711-6-jiaxun.y...@flygoat.com Signed-off-by: Song Gao Reviewed-by: Bibo Mao Message-Id: <2024042609155

[PULL v2 00/17] loongarch-to-apply queue

The following changes since commit fd87be1dada5672f877e03c2ca8504458292c479: Merge tag 'accel-20240426' of https://github.com/philmd/qemu into staging (2024-04-26 15:28:13 -0700) are available in the Git repository at: https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240429 for yo

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