-fsanitize=undefined complains if function pointers are casted. It
also prevents enabling teh strict mode of CFI which is currently
disabled with -fsanitize-cfi-icall-generalize-pointers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2346
Signed-off-by: Akihiko Odaki
---
I upgraded my Fedora Asahi Remix from 39 to 40 and found new sanitizer
errors with clang it ships so here are fixes.
The patch "meson: Drop the .fa library prefix" may have a broad impact
to the build system so please tell me if you have a concern with it.
To: Michael Tokarev
To: Laurent Vivier
The non-standard .fa library suffix breaks the link source
de-duplication done by Meson so drop it.
The lack of link source de-duplication causes AddressSanitizer to
complain ODR violations, and makes GNU ld abort when combined with
clang's LTO.
Previously, the non-standard suffix was necessary
-fsanitize=undefined complains if function pointers are casted. It
also prevents enabling teh strict mode of CFI which is currently
disabled with -fsanitize-cfi-icall-generalize-pointers.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2345
Signed-off-by: Akihiko Odaki
---
LeakSanitizer complains about allocations whose references are held
only by automatic variables. It is possible to free them to suppress
the complaints, but it is a chore to make sure they are freed in all
exit paths so make them static instead.
Signed-off-by: Akihiko Odaki
---
qemu-keymap.c |
://gitlab.com/rth7680/qemu.git tags/pull-tcg-20240523
for you to fetch changes up to bfd43cccab9fb77b8405ca556fc2f2ed3b2920a3:
accel/tcg: Init tb size and icount before plugin_gen_tb_end (2024-05-22
19:05:26 -0700)
tcg
On 24/05/2024 02.05, Nicholas Piggin wrote:
On Wed May 22, 2024 at 7:12 PM AEST, Thomas Huth wrote:
On s390x, we recently had a regression that broke migration / savevm
(see commit bebe9603fc ("hw/intc/s390_flic: Fix crash that occurs when
saving the machine state"). The problem was merged
Hi,
could anyone please review this series?
On 2024/5/17 17:52, Changqi Lu wrote:
> Hi,
>
> Please ignore the v2 series. Please review the v3 series instead.
> Thanks!
>
> v2->v3:
> In v2 Persist Through Power Loss(PTPL) is enable default.
> In v3 PTPL is supported, which is passed as a
Song will online next week.
Please correct me if there is something wrong, song.
On 2024/5/24 上午7:50, Jiaxun Yang wrote:
在2024年5月21日五月 下午1:32，Song Gao写道：
On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
This patch adds the extioi virt extension support so that the IRQ
On Wed May 22, 2024 at 7:12 PM AEST, Thomas Huth wrote:
> On s390x, we recently had a regression that broke migration / savevm
> (see commit bebe9603fc ("hw/intc/s390_flic: Fix crash that occurs when
> saving the machine state"). The problem was merged without being noticed
> since we currently do
to lists.
Thanks,
Nick
The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83:
Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into staging
(2024-05-23 09:47:40 -0700)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc
在2024年5月21日五月 下午1:32，Song Gao写道：
> On LoongArch, IRQs can be routed to four vcpus with hardware extioi.
> This patch adds the extioi virt extension support so that the IRQ can
> route to 256 vcpus.
Hi Song,
Sorry for chime in here, I'm a little bit confused by this series, can
you give me a
On 5/23/24 10:18, Manos Pitsidianakis wrote:
>> #define virtio_gpu_hostmem_enabled(_cfg) \
>> (_cfg.hostmem > 0)
>> +#define virtio_gpu_venus_enabled(_cfg) \
>> + (_cfg.flags & (1 << VIRTIO_GPU_FLAG_VENUS_ENABLED))
>>
>
> Can we have both venus and rutabaga enabled on the same virtio-gpu
>
On Fri May 24, 2024 at 9:06 AM AEST, Nicholas Piggin wrote:
> The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83:
>
> Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into
> staging (2024-05-23 09:47:40 -0700)
>
> are available in
On Thu May 23, 2024 at 8:46 AM AEST, Richard Henderson wrote:
> On 5/21/24 21:04, Nicholas Piggin wrote:
> > The crux of the problem being that dynamic exits from a TB would
> > not count instructions previously executed in the TB. I don't
> > know how important it is for PMU to count instructions
From: BALATON Zoltan
Add ppc_real_mode_xlate() to handle real mode translation and allow
removing this case from ppc_jumbo_xlate().
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 46
From: Chinmay Rath
Moving the following instructions to decodetree specification :
cmp{rb, eqb}, t{w, d} : X-form
t{w, d}i: D-form
isel: A-form
The changes were verified by validating that the tcg ops generated by those
instructions
There is a memop_size() function for this.
Reviewed-by: BALATON Zoltan
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 8 +++-
1 file changed, 3 insertions(+), 5 deletions(-)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index
Use DEF_MEMOP() consistently in larx and stcx. generation, and apply it
once when it's used rather than where the macros are expanded, to reduce
typing.
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/translate.c | 18 +-
1 file changed, 9
msgsnd has a broadcast mode that sends hypervisor doorbells to all
threads belonging to the same core as the target. A "subcore" mode
sends to all or one thread depending on 1LPAR mode.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h |
An SPR can be either per-thread, per-core, or per-LPAR. Per-LPAR means
per-thread or per-core, depending on 1LPAR mode.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 28
2 files changed, 30
From: BALATON Zoltan
The value is only used once so no need to introduce a local variable
for it.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-radix64.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git
PPR32 provides access to the upper half of PPR.
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 1 +
target/ppc/cpu_init.c | 12
target/ppc/spr_common.h | 2 ++
target/ppc/translate.c | 24
4 files changed,
From: BALATON Zoltan
The helper_rac function is defined but not used, remove it.
Fixes: 005b69fdcc (target/ppc: Remove PowerPC 601 CPUs)
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/helper.h | 2 --
target/ppc/mmu_helper.c |
From: BALATON Zoltan
Add a new mmu-booke.c file for BookE and related MMU bits from
mmu_common.c.
Acked-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h| 4 -
target/ppc/meson.build | 1 +
target/ppc/mmu-booke.c | 531
From: BALATON Zoltan
The ppc_hash32_pp_prot() function in mmu-hash32.c is the same as
pp_check() in mmu_common.c, merge these to remove duplicated code.
Define the common function as static lnline otherwise exporting the
function from mmu-hash32.c would stop the compiler inlining it which
PTCR is a per-core register.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 16 ++--
target/ppc/translate.c | 4
2 files changed, 18 insertions(+), 2 deletions(-)
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index
From: BALATON Zoltan
As BookE never returns -4 we can drop BookE from the direct store case
in ppc_jumbo_xlate().
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 7 +--
1 file changed, 1 insertion(+), 6 deletions(-)
From: BALATON Zoltan
The real mode handling is identical in the remaining switch cases.
Split off these common real mode cases into a separate conditional to
leave only the else branches in the switch that are different.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
From: BALATON Zoltan
mmubooke206_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 32
From: BALATON Zoltan
Introduce ppc_booke_xlate() to handle BookE and BookE 2.06 cases to
reduce ppc_jumbo_xlate() further.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 146 ++--
1
From: BALATON Zoltan
Now that only 6xx cases left in ppc_jumbo_xlate() we can change it
to ppc_6xx_xlate() also removing get_physical_address_wtlb().
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/internal.h | 5 +
From: BALATON Zoltan
Introduce ppc_40x_xlate() to split off 40x handlning leaving only 6xx
in ppc_jumbo_xlate() now.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 150 +---
1 file
From: Chinmay Rath
Moving the following instructions to decodetree specification :
{l,st}ve{b,h,w}x,
{l,st}v{x,xl},
lvs{l,r}: X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were
From: BALATON Zoltan
Drop MPC8xx cases from get_physical_address_wtlb() and ppc_jumbo_xlate().
The default case would still catch this and abort the same way and
there is still a warning about it in ppc_tlb_invalidate_all() which is
called in ppc_cpu_reset_hold() so likely we never get here but
From: BALATON Zoltan
In mmubooke_check_tlb() and mmubooke206_check_tlb() prot2 is
calculated first but only used after an unrelated check that can
return before tha value is used. Move the calculation after the check,
closer to where it is used, to keep them together and avoid computing
it when
From: BALATON Zoltan
In get_physical_address_wtlb() the real_mode flag depends on either
the MSR[IR] or MSR[DR] bit depending on access_type. Extract just the
needed bit in a more straight forward way instead of doing unnecessary
computation.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON
From: BALATON Zoltan
Merge the code fetch and data access cases in a common switch.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 52 -
1 file changed, 20 insertions(+), 32
LDBAR, TTR are a Power-specific SPRs. These simple implementations
are enough for IBM proprietary firmware for now.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 2 ++
target/ppc/cpu_init.c | 10 ++
2 files changed, 12 insertions(+)
diff --git
From: BALATON Zoltan
Move the debug logging within ppc6xx_tlb_check() from after its only
call to simplify the caller.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 54 ++---
1 file
From: BALATON Zoltan
The "2" in booke206_update_mas_tlb_miss() call corresponds to
MMU_INST_FETCH which is the value of access_type in this branch;
mmubooke206_esr() only checks for MMU_DATA_STORE and it's called from
code access so using MMU_DATA_LOAD here seems wrong so replace it with
This tries to faithfully reproduce the odd BookE logic. Note the
e206 check in gen_msync_4xx() is always false, so not carried over.
It does change the handling of non-zero reserved bits outside the
defined fields from being illegal to being ignored, which the
architecture specifies ot help with
From: BALATON Zoltan
Instead of putting a large block of code in an if, invert the
condition and return early to be able to deindent the code block.
Acked-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 319
From: Chinmay Rath
Moving the following instructions to decodetree :
mul{ld, ldo, hd, hdu}[.]: XO-form
madd{hd, hdu, ld} : VA-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured
From: Chinmay Rath
Moving the below instructions to decodetree specification :
divd[u, e, eu][o][.]: XO-form
mod{sd, ud} : X-form
With this patch, all the fixed-point arithmetic instructions have been
moved to decodetree.
The changes were verified by validating
From: Glenn Miles
The following changes were made:
- Enabled functionality on P10 processors only due to
performance impact seen with P8 and P9 where it is not
disabled for non problem state branches.
- Added a BHRB buffer for storing branch instruction and
target addresses for
From: BALATON Zoltan
This function just does two assignments and and unnecessary check that
is always true so inline it in the only caller left and remove it.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26
From: BALATON Zoltan
mmu40x_get_physical_address() only uses the raddr and prot fields from
mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 37
From: BALATON Zoltan
In ppc_hash32_xlate() the value of need_prop is checked in two places
but precalculating it does not help because when we reach the first
check we always return and not reach the second place so the value
will only be used once. We can drop the local variable and calculate
From: BALATON Zoltan
Checking if a page protection bit is set for a given access type is a
common operation. Add a function to avoid repeating the same check at
multiple places. As this relies on access type and page protection bit
values having certain relation also add an assert to ensure that
From: "Dr. David Alan Gilbert"
I think it's use was removed by
Commit 5883d8b296 ("mmu-hash*: Don't use full ppc_hash{32,
64}_translate() path for get_phys_page_debug()")
Reviewed-by: BALATON Zoltan
Signed-off-by: Dr. David Alan Gilbert
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas
From: BALATON Zoltan
Move setting error_code that appears in every case out in front and
hoist the common fall through case for BOOKE206 as well which allows
removing the nested switches.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
From: BALATON Zoltan
This flag for split instruction/data TLBs is only set for 6xx soft TLB
MMU model and not used otherwise so no need to have a separate flag
for that.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
hw/ppc/pegasos2.c|
From: BALATON Zoltan
Several 4xx CPUs and e200 share the same TLB settings enclosed in an
ifdef. Split it off in a common function to reduce code duplication
and the number of ifdefs.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
From: BALATON Zoltan
Remove mmu_ctx_t definition from internal.h as this type is only used
within mmu_common.c.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/internal.h | 12
target/ppc/mmu_common.c | 11 +++
From: BALATON Zoltan
Fix several qemu_log_mask() calls that are misindented.
Acked-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 42 -
1 file changed, 20 insertions(+), 22 deletions(-)
Some TLB flush operations can flush other CPUs. The problem with this
is they used non-synced variants of flushes (i.e., that return
before the destination has completed the flush). Since all TLB flush
users need the _synced variants, and that last user (ppc) of the
non-synced flush was buggy,
From: BALATON Zoltan
Return directly, which is simpler than dragging a return value through
multpile if and else blocks.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 84 +++--
1
From: BALATON Zoltan
mmubooke_get_physical_address() only uses the raddr and prot fields
from mmu_ctx_t. Pass these directly instead of using a ctx struct.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 30
attn is an implementation-specific instruction that on POWER (and G5/
970) can be enabled with a HID bit (disabled = illegal), and executing
it causes the host processor to stop and the service processor to be
notified. Generally used for debugging.
Implement attn and make it checkstop the
From: BALATON Zoltan
In mmu6xx_get_physical_address() we have a large if block with a two
line else branch that effectively returns. Invert the condition and
move the else there to allow deindenting the large if block to make
the flow easier to follow.
Reviewed-by: Nicholas Piggin
AMOR, MMCRC, HRMOR, TSCR, HMEER, RPR SPRs are per-core or per-LPAR
registers with simple (generic) implementations.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git
The DECAR SPR is 32-bits width.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ee01415c32..927721d49a 100644
--- a/target/ppc/cpu_init.c
From: BALATON Zoltan
In mmubooke_check_tlb() and mmubooke206_check_tlb() we can assign the
value of prot2 directly to the destination, no need to have a separate
local variable for it.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
Change the logging not to print to stderr as well, because a
checkstop is a guest error (or perhaps a simulated machine error)
rather than a QEMU error, so send it to the log.
Update the checkstop message, and log CPU registers too.
Reviewed-by: Richard Henderson
Reviewed-by: Glenn Miles
POWER10 adds a new field to sync for store-store syncs, and some
new variants of the existing syncs that include persistent memory.
Implement the store-store syncs and plwsync/phwsync.
Reviewed-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode | 6 ++--
These are no longer used.
tlb_flush_all_cpus: removed by previous commit.
tlb_flush_page_all_cpus: removed by previous commit.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used.
tlb_flush_page_by_mmuidx_all_cpus: never used.
tlb_flush_page_bits_by_mmuidx_all_cpus: never used, thus:
From: Chinmay Rath
Moving the following instructions to decodetree specification :
mulli : D-form
mul{lw, lwo, hw, hwu}[.]: XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which
From: BALATON Zoltan
BookE does not have real mode so split off and handle it first in
get_physical_address_wtlb() before checking for real mode for other
MMU models.
Reviewed-by: Nicholas Piggin
Signed-off-by: BALATON Zoltan
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 14
This implements the POWER SPRC/SPRD SPRs, and SCRATCH0-7 registers that
can be accessed via these indirect SPRs.
SCRATCH registers only provide storage, but they are used by firmware
for low level crash and progress data, so this implementation logs
writes to the registers to help with analysis.
From: Chinmay Rath
Moving the below instructions to decodetree specification :
neg[o][.] : XO-form
mod{sw, uw}, darn : X-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with
From: BALATON Zoltan
Repurpose get_segment_6xx_tlb() to do the whole address translation
for POWERPC_MMU_SOFT_6xx MMU model by moving the BAT check there and
renaming it to match other similar functions. These are only called
once together so no need to keep these separate functions and
From: Chinmay Rath
This patch moves the below instructions to decodetree specification :
f{add, sub, mul, div, re, rsqrte, madd, msub, nmadd, nmsub}[s][.] : A-form
ft{div, sqrt} : X-form
With this patch, all the floating-point
checkstop state does not halt the system, interrupts continue to be
serviced, and other CPUs run. Make it stop the machine with
qemu_system_guest_panicked.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 16 +---
1 file changed, 13
From: Glenn Miles
Reviewed-by: Nicholas Piggin
Signed-off-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
target/ppc/machine.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index 6b6c31d903..731dd8df35 100644
---
From: Glenn Miles
Since neither instruction is believed to be critical to
performance, both instructions were implemented using helper
functions.
Access to both instructions is controlled by bits in the
HFSCR (for privileged state) and MMCR0 (for problem state).
A new function,
From: Chinmay Rath
Moving the following instructions to decodetree specification:
v{and, andc, nand, or, orc, nor, xor, eqv} : VX-form
The changes were verified by validating that the tcp ops generated by those
instructions remain the same, which were captured with the '-d
From: Chinmay Rath
Moving the below instructions to decodetree specification :
andi[s]., {ori, xori}[s]: D-form
{and, andc, nand, or, orc, nor, xor, eqv}[.],
exts{b, h, w}[.], cnt{l, t}z{w, d}[.],
popcnt{b, w, d}, prty{w, d}, cmp,
From: Chinmay Rath
Moving the following instructions to decodetree specification :
v{max, min}{u, s}{b, h, w, d} : VX-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
The following changes since commit 70581940cabcc51b329652becddfbc6a261b1b83:
Merge tag 'pull-tcg-20240523' of https://gitlab.com/rth7680/qemu into staging
(2024-05-23 09:47:40 -0700)
are available in the Git repository at:
https://gitlab.com/npiggin/qemu.git tags/pull-ppc-for-9.1-1
From: Glenn Miles
BHRB uses several SPR register fields to control whether or not
a branch instruction's address (and sometimes target address)
should be recorded. Checking each of these fields with each
branch instruction using jitted code would lead to a significant
decrease in performance.
From: Chinmay Rath
The handler methods for divw[u] instructions internally use Rc(ctx->opcode),
for extraction of Rc field of instructions, which poses a problem if we move
the above said instructions to decodetree, as the ctx->opcode field is not
popluated in decodetree. Hence, making it
Memory barriers are supposed to do something on BookE systems, these
were probably just missed during MTTCG enablement, maybe no targets
support SMP. Either way, add proper BookE implementations.
Reviewed-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/misc-impl.c.inc
From: Chinmay Rath
Moving the following instructions to decodetree specification :
divw[u, e, eu][o][.] : XO-form
The changes were verified by validating that the tcg ops generated by those
instructions remain the same, which were captured with the '-d in_asm,op' flag.
Reviewed-by:
From: Chinmay Rath
This patch merges the definitions of the following set of fpu helper methods,
which are similar, using macros :
1. f{add, sub, mul, div}(s)
2. fre(s)
3. frsqrte(s)
Reviewed-by: Nicholas Piggin
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
interrupts and TLB misses and is quite costly. Running the
kvm-unit-tests sieve program with radix MMU enabled thrashes the TCG
TLB and spends a lot of time in TLB and page table walking code. The
test takes 67 seconds to
With mttcg, broadcast tlbie instructions do not wait until other vCPUs
have been kicked out of TCG execution before they complete (including
necessary subsequent tlbsync, etc., instructions). This is contrary to
the ISA, and it permits other vCPUs to use translations after the TLB
flush. For
The ibm,pi-features property has a bit to say whether or not
msgsndp should be used. Linux checks if it is being run under
KVM and avoids msgsndp anyway, but it would be preferable to
rely on this bit.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr.c | 28
On Wed, 2024-05-22 at 19:01 +0200, Cédric Le Goater wrote:
> Hello,
>
> The first patches of this series simply apply the practices described
> in the Rules section of the qapi/error.h file for routines taking an
> 'Error **' argument. The remaining patches are a fixup in the error
> path of
The current migration-tests are almost entirely focused on catching
bugs on the migration code itself, not on the device migration
infrastructure (vmstate). That means we miss catching some low hanging
fruits that would show up immediately if only we had the device in
question present in the VM.
We have discussed recently about two relatively cheap ways to catch
migration compatibility breakages across QEMU versions. This series
adds support for both.
1) vmstate-static-checker.py
This script has existed for a while and takes a dmup of vmstates from
two different QEMU versions and
We have the vmstate-static-checker script that takes the output of:
'$QEMU -M $machine -dump-vmstate' for two different QEMU versions and
compares them to check for compatibility breakages. This is just too
simple and useful for us to pass on it. Add a test that runs the
script.
Since this needs
Introduce a qtest_init version that does not go through the QMP
handshake, but does pass the test binary environment variables
forward. This is needed so we can run a simpler instance of QEMU with
-machine, but not much else.
The existing qtest_init_without_qmp_handshake() is not enough because
We have two new migration tests that check cross version
compatibility. One uses the vmstate-static-checker.py script to
compare the vmstate structures from two different QEMU versions. The
other runs a simple migration with a few devices present in the VM, to
catch obvious breakages.
Add both
Among implemented STM32L4x5 devices, USART, GPIO and SYSCFG
have a clock source, but none has a corresponding test in QEMU.
This patch makes sure that all 3 devices create a clock correctly,
adds a QOM property to access clocks' periods from QTests,
and adds QTests checking that clock enable in
For USART, GPIO and SYSCFG devices, check that clock frequency before
and after enabling the peripheral clock in RCC is correct.
Signed-off-by: Inès Varhol
---
tests/qtest/stm32l4x5.h | 43 +
tests/qtest/stm32l4x5_gpio-test.c | 23 +++
This commit creates a clock in STM32L4x5 SYSCFG and wires it up to the
corresponding clock from STM32L4x5 RCC.
Signed-off-by: Inès Varhol
---
include/hw/misc/stm32l4x5_syscfg.h | 1 +
hw/arm/stm32l4x5_soc.c | 2 ++
hw/misc/stm32l4x5_syscfg.c | 19 +--
3
Expose the clock period via the QOM 'qtest-clock-period' property so it
can be used in QTests. This property is only accessible in QTests (not
via HMP).
Signed-off-by: Philippe Mathieu-Daudé
Signed-off-by: Inès Varhol
---
docs/devel/clocks.rst | 3 +++
hw/core/clock.c | 16
`vmstate_stm32l4x5_usart_base` namely uses `VMSTATE_CLOCK` so
version needs to be 2.
Signed-off-by: Inès Varhol
---
hw/char/stm32l4x5_usart.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c
index
On Mon, May 13, 2024 at 04:17:02PM +0200, Markus Armbruster wrote:
> Functions that use an Error **errp parameter to return errors should
> not also report them to the user, because reporting is the caller's
> job. When the caller does, the error is reported twice. When it
> doesn't (because it
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