[PULL 08/42] vfio/iommufd: Implement HostIOMMUDeviceClass::realize() handler

From: Zhenzhong Duan It calls iommufd_backend_get_device_info() to get host IOMMU related information and translate it into HostIOMMUDeviceCaps for query with .get_cap(). For aw_bits, use the same way as legacy backend by calling vfio_device_get_aw_bits() which is common for different vendor IOM

[PULL 42/42] vfio/container: Move vfio_container_destroy() to an instance_finalize() handler

vfio_container_destroy() clears the resources allocated VFIOContainerBase object. Now that VFIOContainerBase is a QOM object, add an instance_finalize() handler to do the cleanup. It will be called through object_unref(). Suggested-by: Zhenzhong Duan Reviewed-by: Zhenzhong Duan Reviewed-by: Eric

[PULL 36/42] vfio/container: Change VFIOContainerBase to use QOM

VFIOContainerBase was made a QOM interface because we believed that a QOM object would expose all the IOMMU backends to the QEMU machine and human interface. This only applies to user creatable devices or objects. Change the VFIOContainerBase nature from interface to object and make the necessary

[PULL 24/42] hw/vfio: Remove memory_region_iommu_set_iova_ranges() call

From: Eric Auger As we have just removed the only implementation of iommu_set_iova_ranges IOMMU MR callback in the virtio-iommu, let's remove the call to the memory wrapper. Usable IOVA ranges are now conveyed through the PCIIOMMUOps in VFIO-PCI. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong

[PULL 35/42] vfio/container: Discover IOMMU type before creating the container

Since the QEMU struct type representing the VFIO container is deduced from the IOMMU type exposed by the host, this type should be well defined *before* creating the container struct. This will be necessary to instantiate a QOM object of the correct type in future changes. Rework vfio_set_iommu()

[PULL 17/42] intel_iommu: Check compatibility with host IOMMU capabilities

From: Zhenzhong Duan If check fails, host device (either VFIO or VDPA device) is not compatible with current vIOMMU config and should not be passed to guest. Only aw_bits is checked for now, we don't care about other caps before scalable modern mode is introduced. Signed-off-by: Yi Liu Signed-

[PULL 06/42] vfio/container: Implement HostIOMMUDeviceClass::realize() handler

From: Zhenzhong Duan The realize function populates the capabilities. For now only the aw_bits caps is computed for legacy backend. Introduce a helper function vfio_device_get_aw_bits() which calls range_get_last_bit() to get host aw_bits and package it in HostIOMMUDeviceCaps for query with .get

[PULL 39/42] vfio/container: Remove VFIOContainerBase::ops

Instead, use VFIO_IOMMU_GET_CLASS() to get the class pointer. Reviewed-by: Zhenzhong Duan Reviewed-by: Eric Auger Tested-by: Eric Auger Signed-off-by: Cédric Le Goater --- include/hw/vfio/vfio-container-base.h | 1 - hw/vfio/common.c | 2 +- hw/vfio/container-base.c

[PULL 16/42] intel_iommu: Implement [set|unset]_iommu_device() callbacks

From: Yi Liu Implement [set|unset]_iommu_device() callbacks in Intel vIOMMU. In set call, we take a reference of HostIOMMUDevice and store it in hash table indexed by PCI BDF. Note this BDF index is device's real BDF not the aliased one which is different from the index of VTDAddressSpace. There

[PULL 00/42] vfio queue

The following changes since commit d89b64beea65f77c21a553cb54cb97b75c53dc21: Merge tag 'pull-request-2024-06-24' of https://gitlab.com/thuth/qemu into staging (2024-06-24 11:57:11 -0700) are available in the Git repository at: https://github.com/legoater/qemu/ tags/pull-vfio-202

[PULL 19/42] virtio-iommu: Implement set|unset]_iommu_device() callbacks

From: Eric Auger Implement PCIIOMMUOPs [set|unset]_iommu_device() callbacks. In set(), the HostIOMMUDevice handle is stored in a hash table indexed by PCI BDF. The object will allow to retrieve information related to the physical IOMMU. Signed-off-by: Eric Auger Reviewed-by: Zhenzhong Duan Rev

[PULL 02/42] backends/host_iommu_device: Introduce HostIOMMUDeviceCaps

From: Zhenzhong Duan HostIOMMUDeviceCaps's elements map to the host IOMMU's capabilities. Different platform IOMMU can support different elements. Currently only two elements, type and aw_bits, type hints the host platform IOMMU type, i.e., INTEL vtd, ARM smmu, etc; aw_bits hints host IOMMU addr

[PULL 03/42] vfio/container: Introduce TYPE_HOST_IOMMU_DEVICE_LEGACY_VFIO device

From: Zhenzhong Duan TYPE_HOST_IOMMU_DEVICE_LEGACY_VFIO represents a host IOMMU device under VFIO legacy container backend. It will have its own realize implementation. Suggested-by: Eric Auger Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by:

[PULL 11/42] vfio: Create host IOMMU device instance

From: Zhenzhong Duan Create host IOMMU device instance in vfio_attach_device() and call .realize() to initialize it further. Introuduce attribute VFIOIOMMUClass::hiod_typename and initialize it based on VFIO backend type. It will facilitate HostIOMMUDevice creation in vfio_attach_device(). Sugg

[PULL 09/42] vfio/container: Implement HostIOMMUDeviceClass::get_cap() handler

From: Zhenzhong Duan Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin --- hw/vfio/container.c | 15 +++ 1 file changed, 15 insertions(+) diff --git a/hw/vfio/container.c b/hw/vfio/container.c index 2f62c1321441

[PULL 05/42] range: Introduce range_get_last_bit()

From: Zhenzhong Duan This helper get the highest 1 bit position of the upper bound. If the range is empty or upper bound is zero, -1 is returned. Suggested-by: Cédric Le Goater Signed-off-by: Zhenzhong Duan Reviewed-by: Eric Auger Reviewed-by: Michael S. Tsirkin --- include/qemu/range.h |

Re: [PATCH v4 0/8] VIRTIO-IOMMU/VFIO: Fix host iommu geometry handling for hotplugged devices

On 6/14/24 11:52 AM, Eric Auger wrote: This series is based on Zhenzhong HostIOMMUDevice: [PATCH v7 00/17] Add a host IOMMU device abstraction to check with vIOMMU https://lore.kernel.org/all/20240605083043.317831-1-zhenzhong.d...@intel.com/ It allows to convey host IOVA reserved regions to the

Re: [PATCH v2 00/17] vfio: QOMify VFIOContainer

On 6/17/24 8:33 AM, Cédric Le Goater wrote: Hello, The series starts with simple changes (patch 1-4). Two of which were initially sent by Joao in a series adding VFIO migration support with vIOMMU [1]. The changes following prepare VFIOContainer for QOMification, switch the container models to

Re: [PATCH v7 00/17] Add a host IOMMU device abstraction to check with vIOMMU

On 6/5/24 10:30 AM, Zhenzhong Duan wrote: Hi, This series introduce a HostIOMMUDevice abstraction and sub-classes. Also HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface between vIOMMU and HostIOMMUDevice. A HostIOMMUDevice is an abstraction for an assigned device that is pro

Re: [PATCH v2] Consider discard option when writing zeros

On Mon, Jun 24, 2024 at 7:08 PM Kevin Wolf wrote: > Am 24.06.2024 um 17:23 hat Stefan Hajnoczi geschrieben: > > On Wed, Jun 19, 2024 at 08:43:25PM +0300, Nir Soffer wrote: > > > Tested using: > > > > Hi Nir, > > This looks like a good candidate for the qemu-iotests test suite. Adding > > it to th

[PATCH 1/1] include/qemu: Provide a C++ compatible version of typeof_strip_qual

From: Roman Kiryanov to use the QEMU headers with a C++ compiler. Signed-off-by: Felix Wu Signed-off-by: Roman Kiryanov --- include/qemu/atomic.h | 8 include/qemu/atomic.hpp | 38 ++ 2 files changed, 46 insertions(+) create mode 100644 include

Re: [PULL 00/11] s390x and qtest patches 2024-06-24

On 6/24/24 02:10, Thomas Huth wrote: The following changes since commit c9ba79baca7c673098361e3a687f72d458e0d18a: Merge tag 'pull-target-arm-20240622' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-06-22 09:56:49 -0700) are available in the Git repository at: htt

[PATCH 1/2] qom: Rename Object::class into Object::klass

From: Roman Kiryanov 'class' is a C++ keyword and it prevents from using the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: I9ab7d2d77edef654a9c7b7cb9cd01795a6ed65a2 Signed-off-by: Felix Wu Signed-off-by: Roman Kiryanov --- hw/core/qdev-properties-system.c | 2 +- incl

[PATCH 2/2] include/qom: Rename typename into type_name

From: Roman Kiryanov `typename` is a C++ keyword and it prevents from using the QEMU headers with a C++ compiler. Google-Bug-Id: 331190993 Change-Id: Iff313ca5ec157a1a3826b4f5665073534d961a26 Signed-off-by: Felix Wu Signed-off-by: Roman Kiryanov --- hw/core/bus.c | 8 +-- include/h

[PATCH v4 03/14] hw/riscv: add RISC-V IOMMU base emulation

From: Tomasz Jeznach The RISC-V IOMMU specification is now ratified as-per the RISC-V international process. The latest frozen specifcation can be found at: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf Add the foundation of the device emulation for RISC-V

[PATCH v4 11/14] hw/riscv/riscv-iommu: add DBG support

From: Tomasz Jeznach DBG support adds three additional registers: tr_req_iova, tr_req_ctl and tr_response. The DBG cap is always enabled. No on/off toggle is provided for it. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iom

[PATCH v4 13/14] qtest/riscv-iommu-test: add init queues test

Add an additional test to further exercise the IOMMU where we attempt to initialize the command, fault and page-request queues. These steps are taken from chapter 6.2 of the RISC-V IOMMU spec, "Guidelines for initialization". It emulates what we expect from the software/OS when initializing the IO

[PATCH v4 08/14] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC)

From: Tomasz Jeznach The RISC-V IOMMU spec predicts that the IOMMU can use translation caches to hold entries from the DDT. This includes implementation for all cache commands that are marked as 'not implemented'. There are some artifacts included in the cache that predicts s-stage and g-stage e

[PATCH v4 02/14] hw/riscv: add riscv-iommu-bits.h

From: Tomasz Jeznach This header will be used by the RISC-V IOMMU emulation to be added in the next patch. Due to its size it's being sent in separate for an easier review. One thing to notice is that this header can be replaced by the future Linux RISC-V IOMMU driver header, which would become

[PATCH v4 04/14] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device

The RISC-V IOMMU PCI device we're going to add next is a reference implementation of the riscv-iommu spec [1], which predicts that the IOMMU can be implemented as a PCIe device. However, RISC-V International (RVI), the entity that ratified the riscv-iommu spec, didn't bother assigning a PCI ID for

[PATCH v4 06/14] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug

From: Tomasz Jeznach Generate device tree entry for riscv-iommu PCI device, along with mapping all PCI device identifiers to the single IOMMU device instance. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/virt.c | 33 ++

[PATCH v4 09/14] hw/riscv/riscv-iommu: add s-stage and g-stage support

From: Tomasz Jeznach Add support for s-stage (sv32, sv39, sv48, sv57 caps) and g-stage (sv32x4, sv39x4, sv48x4, sv57x4 caps). Most of the work is done in the riscv_iommu_spa_fetch() function that now has to consider how many translation stages we need to walk the page table. Signed-off-by: Tomas

[PATCH v4 10/14] hw/riscv/riscv-iommu: add ATS support

From: Tomasz Jeznach Add PCIe Address Translation Services (ATS) capabilities to the IOMMU. This will add support for ATS translation requests in Fault/Event queues, Page-request queue and IOATC invalidations. Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Fr

[PATCH v4 14/14] docs/specs: add riscv-iommu

Add a simple guideline to use the existing RISC-V IOMMU support we just added. This doc will be updated once we add the riscv-iommu-sys device. Signed-off-by: Daniel Henrique Barboza --- docs/specs/index.rst | 1 + docs/specs/riscv-iommu.rst | 55 ++ d

[PATCH v4 07/14] test/qtest: add riscv-iommu-pci tests

To test the RISC-V IOMMU emulation we'll use its PCI representation. Create a new 'riscv-iommu-pci' libqos device that will be present with CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this device will only be consumed by the RISC-V libqos machine. Start with basic tests: a PC

[PATCH v4 12/14] hw/riscv/riscv-iommu: Add another irq for mrif notifications

From: Andrew Jones And add mrif notification trace. Signed-off-by: Andrew Jones Reviewed-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/riscv-iommu-pci.c | 2 +- hw/riscv/riscv-iommu.c | 1 + hw/riscv/trace-events | 1 + 3 files changed, 3 insertions(+), 1 deletio

[PATCH v4 00/14] riscv: QEMU RISC-V IOMMU Support

Hi, This new version contains changes based on suggestions made during the v3 review [1]. Most notable changes: - read/write locks were added in both ctx_lock and iot_lock. This code was picked from Tomasz branch; - a new riscv_iommu_validate_process_ctx() helper was added to make process-con

[PATCH v4 05/14] hw/riscv: add riscv-iommu-pci reference device

From: Tomasz Jeznach The RISC-V IOMMU can be modelled as a PCIe device following the guidelines of the RISC-V IOMMU spec, chapter 7.1, "Integrating an IOMMU as a PCIe device". Signed-off-by: Tomasz Jeznach Signed-off-by: Daniel Henrique Barboza Reviewed-by: Frank Chang --- hw/riscv/meson.bui

[PATCH v4 01/14] exec/memtxattr: add process identifier to the transaction attributes

From: Tomasz Jeznach Extend memory transaction attributes with process identifier to allow per-request address translation logic to use requester_id / process_id to identify memory mapping (e.g. enabling IOMMU w/ PASID translations). Signed-off-by: Tomasz Jeznach Reviewed-by: Frank Chang ---

Re: [PATCH v4 3/5] mirror: allow specifying working bitmap

On 21.05.24 15:20, Fiona Ebner wrote: From: John Snow for the mirror job. The bitmap's granularity is used as the job's granularity. The new @bitmap parameter is marked unstable in the QAPI and can currently only be used for @sync=full mode. Clusters initially dirty in the bitmap as well as n

Re: [RFC PATCH v3 2/5] rust: add bindgen step as a meson dependency

On Thu, 20 Jun 2024 at 14:35, Manos Pitsidianakis wrote: > > On Thu, 20 Jun 2024 15:32, Alex Bennée wrote: > >Manos Pitsidianakis writes: > > > >> Add mechanism to generate rust hw targets that depend on a custom > >> bindgen target for rust bindings to C. > >> > >> This way bindings will be cre

Re: [PATCH v1 00/13] Multifd 🔀 device state transfer support with VFIO consumer

Hi Peter, On 23.06.2024 22:27, Peter Xu wrote: On Tue, Jun 18, 2024 at 06:12:18PM +0200, Maciej S. Szmigiero wrote: From: "Maciej S. Szmigiero" This is an updated v1 patch series of the RFC (v0) series located here: https://lore.kernel.org/qemu-devel/cover.1713269378.git.maciej.szmigi...@orac

Re: [PATCH v4 2/5] block/mirror: replace is_none_mode with sync_mode in MirrorBlockJob struct

On 21.05.24 15:20, Fiona Ebner wrote: It is more flexible and is done in preparation to support specifying a working bitmap for mirror jobs. In particular, this makes it possible to assert that @sync_mode=full when a bitmap is used. That assertion is just to be sure, of course the mirror QMP comm

Re: [PATCH RFC 2/2] migration: abort on destination if switchover limit exceeded

On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote: > During live migration, receive current downtime from source > and start a downtime timer. When the destination dowtime > and added source downtime exceeds downtime limit for more > than switchover limit, abort live migration on dest

Re: [PATCH RFC 1/2] migration: abort when switchover limit exceeded

On Fri, Jun 21, 2024 at 07:32:20AM -0700, Elena Ufimtseva wrote: > @@ -16,6 +16,7 @@ bool migrate_background_snapshot(void); > bool migrate_dirty_limit(void); > bool migrate_postcopy_ram(void); > bool migrate_switchover_ack(void); > +bool migrate_switchover_abort(void); This does look like an i

Re: [PATCH 1/2] migration: Implement dirty ring

Hi, Shota, On Thu, Jun 20, 2024 at 06:47:13PM +0900, Shota Imamura wrote: > This commit implements the dirty ring as an alternative dirty tracking > method to the dirty bitmap. > > While the dirty ring has already been implemented in accel/kvm using KVM's > dirty ring, it was designed to set bits

Re: [PULL v2 00/23] Misc changes for 2024-06-22

On 6/24/24 06:59, Paolo Bonzini wrote: The following changes since commit c9ba79baca7c673098361e3a687f72d458e0d18a: Merge tag 'pull-target-arm-20240622' ofhttps://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-06-22 09:56:49 -0700) are available in the Git repository at: h

Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max

Hi Peter, On 6/24/24 10:27 AM, Peter Maydell wrote: On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is re

Re: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers

Hi Peter! On 6/24/24 10:26 AM, Peter Maydell wrote: On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: Move the initialization of the debug ID registers to aa32_max_features, which is used to set the 32-bit ID registers. This ensures that the debug ID registers are consistently set for the m

[PATCH v3 3/3] target/arm: Enable FEAT_Debugv8p8 for -cpu max

Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU since it concerns the external debug interface for JTAG, but is mandatory in Armv8.8 implementations, hence it is reported as supported in the ID registers. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson ---

[PATCH v3 0/3] target/arm: Enable FEAT_Debugv8p8 for -cpu max

Enable FEAT_Debugv8p8 on Arm max CPU. v2: - Revert to the original comment above call to aa32_max_features() v3: - Added feature entry to docs/system/arm/emulation.rst - Explicitly set t=0 before using it to set DBGDEVID reg. - Put indent fix in a separate patch Cheers, Gustavo Gustavo Rom

[PATCH v3 1/3] target/arm: Fix indentation

Fix comment indentation adding a missing space. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/tcg/cpu64.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/tcg/cpu64.c b/target/arm/tcg/cpu64.c index 0899251eef..71e1bfcd4e 100644 --- a/t

[PATCH v3 2/3] target/arm: Move initialization of debug ID registers

Move the initialization of the debug ID registers to aa32_max_features, which is used to set the 32-bit ID registers. This ensures that the debug ID registers are consistently set for the max CPU in a single place. Signed-off-by: Gustavo Romero Reviewed-by: Richard Henderson --- target/arm/cpu.

Re: [PATCH v3 0/3] Initial support for One-Time Programmable Memory (OTP) in BCM2835

No worries, and thanks! On Mon, Jun 24, 2024 at 3:52 PM Peter Maydell wrote: > > On Mon, 24 Jun 2024 at 10:12, Rayhan Faizel wrote: > > > > Hi, > > > > The patch series is still not merged. > > Oops, sorry about that -- not sure how it got lost. I have > applied it to target-arm.next for real th

Re: [PATCH] docs/cxl: fix some typos

On Sat, 22 Jun 2024 16:25:26 +0900 Hyeongtak Ji wrote: > Hello Jonathan, > > Thank you for your response. > > On Sat, Jun 22, 2024 at 1:10 AM Jonathan Cameron > wrote: > > > > On Wed, 19 Jun 2024 13:54:59 +0900 > > Hyeongtak Ji wrote: > > > > Hi, some description would be good of how you caug

Re: [RFC PATCH v3 1/5] build-sys: Add rust feature option

Il lun 24 giu 2024, 18:52 Daniel P. Berrangé ha scritto: > On Wed, Jun 19, 2024 at 11:13:58PM +0300, Manos Pitsidianakis wrote: > > Add options for Rust in meson_options.txt, meson.build, configure to > > prepare for adding Rust code in the followup commits. > > > > `rust` is a reserved meson nam

Re: [PATCH] Add zh_TW Traditional Chinese translation

On Fri, Jun 21, 2024 at 02:07:52PM +0100, Peter Maydell wrote: > On Fri, 21 Jun 2024 at 13:50, Peter Dave Hello > wrote: > > On Wednesday, April 24th, 2024 at AM 2:20, Peter Dave Hello > > wrote: > > > Thank you for all your help; I wonder if the copyright can just > > > belong to this project

Re: [PATCH] i386/hvf: Integrates x2APIC support with hvf accel

On 6/24/24 16:46, Phil Dennis-Jordan wrote: Support for x2APIC mode was recently introduced in the software emulated APIC implementation for TCG. Enabling it when using macOS’s hvf accelerator is useful and significantly helps performance, as Qemu currently uses the emulated APIC when running on

Re: [RFC PATCH v3 1/5] build-sys: Add rust feature option

On Wed, Jun 19, 2024 at 11:13:58PM +0300, Manos Pitsidianakis wrote: > Add options for Rust in meson_options.txt, meson.build, configure to > prepare for adding Rust code in the followup commits. > > `rust` is a reserved meson name, so we have to use an alternative. > `with_rust` was chosen. > >

Re: [PULL 39/42] i386: Add support for SUCCOR feature

On Thu, Jun 13, 2024 at 05:50:08PM +0800, Xiaoyao Li wrote: > On 6/8/2024 4:34 PM, Paolo Bonzini wrote: > > From: John Allen > > > > Add cpuid bit definition for the SUCCOR feature. This cpuid bit is required > > to > > be exposed to guests to allow them to handle machine check exceptions on AMD

Re: [RFC PATCH v3 1/5] build-sys: Add rust feature option

Il lun 24 giu 2024, 10:36 Zhao Liu ha scritto: > [snip] > > > diff --git a/meson.build b/meson.build > > index c5360fbd299..ad7dbc0d641 100644 > > --- a/meson.build > > +++ b/meson.build > > @@ -290,6 +290,11 @@ foreach lang : all_languages > >endif > > endforeach > > +cargo = not_found > >

[PATCH v3 0/2] tests/avocado: updates for sbsa-ref testing

v2: https://lore.kernel.org/r/20240624-b4-move-to-freebsd-v2-0-64ea7b049...@linaro.org --- Marcin Juszkiewicz (2): tests/avocado: sbsa-ref: add FreeBSD tests tests/avocado: add test for default sbsa-ref cpu tests/avocado/machine_aarch64_sbsaref.py | 90 +++- 1 file c

[PATCH v3 2/2] tests/avocado: add test for default sbsa-ref cpu

We changed sbsa-ref cpu several times already and may do it again in a future. To newer core or to enable/disable some properties. This change switches Neoverse-N2 tests to 'let test default cpu' ones. Signed-off-by: Marcin Juszkiewicz --- tests/avocado/machine_aarch64_sbsaref.py | 29 +

[PATCH v3 1/2] tests/avocado: sbsa-ref: add FreeBSD tests

FreeBSD has longer support cycle for stable release (14.x EoL in 2028) than OpenBSD (7.3 we used is already EoL). Also bugfixes are backported so we can stay on 14.x for longer. Tests done on OpenBSD will now be done using FreeBSD. OpenBSD 7.3 stays with Cortex-A57 test for local runs only. Moved

[Bug Report] Possible Missing Endianness Conversion

The virtio packed virtqueue support patch[1] suggests converting endianness by lines: virtio_tswap16s(vdev, &e->off_wrap); virtio_tswap16s(vdev, &e->flags); Though both of these conversion statements aren't present in the latest qemu code here[2] Is this intentional? [1]: https://mail.gnu.org/a

Re: [PATCH v2] Consider discard option when writing zeros

Am 24.06.2024 um 17:23 hat Stefan Hajnoczi geschrieben: > On Wed, Jun 19, 2024 at 08:43:25PM +0300, Nir Soffer wrote: > > Tested using: > > Hi Nir, > This looks like a good candidate for the qemu-iotests test suite. Adding > it to the automated tests will protect against future regressions. > > P

Re: [QEMU PATCH v2 1/1] hw/arm: FW first ARM processor error injection

On Mon, 24 Jun 2024 at 16:40, wrote: > > From: Shiju Jose > > Add support for QEMU based FW first ARM processor error injection. > +++ b/hw/arm/arm_error_inject_stubs.c > @@ -0,0 +1,22 @@ > +/* > + * ARM Processor errors QMP stubs > + * > + * Copyright(C) 2024 Huawei LTD. > + * > + * This work

[QEMU PATCH v2 1/1] hw/arm: FW first ARM processor error injection

From: Shiju Jose Add support for QEMU based FW first ARM processor error injection. Compliance with N.2.4.4 ARM Processor Error Section in UEFI 2.9A/2.10 specs. Examples, { "execute": "arm-inject-error", "arguments": { "errortypes": ['cache-error'] } } { "execute": "arm-inj

Re: [PATCH 1/1] hw/i386/acpi-build: add OSHP method support for SHPC driver load

On Mon, Jun 24, 2024 at 02:40:48PM +, Gao,Shiyuan wrote: > > > > > +static Aml *build_oshp_method(void) > > > > > +{ > > > > > +    Aml *method; > > > > > + > > > > > +    /* > > > > > +     * Request control of SHPC hotplug via OSHP method, > > > > > +     * no need parameter and return value

Re: [PATCH v7 00/17] Add a host IOMMU device abstraction to check with vIOMMU

On Mon, Jun 24, 2024 at 05:12:13PM +0200, Cédric Le Goater wrote: > On 6/24/24 12:26 PM, Michael S. Tsirkin wrote: > > On Wed, Jun 05, 2024 at 04:30:26PM +0800, Zhenzhong Duan wrote: > > > Hi, > > > > > > This series introduce a HostIOMMUDevice abstraction and sub-classes. > > > Also HostIOMMUDevi

Re: [PATCH v2] Consider discard option when writing zeros

On Wed, Jun 19, 2024 at 08:43:25PM +0300, Nir Soffer wrote: > Tested using: Hi Nir, This looks like a good candidate for the qemu-iotests test suite. Adding it to the automated tests will protect against future regressions. Please add the script and the expected output to tests/qemu-iotests/test/

Re: [Bug Report] Possible Missing Endianness Conversion

On Mon, 24 Jun 2024 at 16:11, Stefano Garzarella wrote: > > CCing Jason. > > On Mon, Jun 24, 2024 at 4:30 PM Xoykie wrote: > > > > The virtio packed virtqueue support patch[1] suggests converting > > endianness by lines: > > > > virtio_tswap16s(vdev, &e->off_wrap); > > virtio_tswap16s(vdev, &e->f

Re: [PATCH v7 00/17] Add a host IOMMU device abstraction to check with vIOMMU

On 6/24/24 12:26 PM, Michael S. Tsirkin wrote: On Wed, Jun 05, 2024 at 04:30:26PM +0800, Zhenzhong Duan wrote: Hi, This series introduce a HostIOMMUDevice abstraction and sub-classes. Also HostIOMMUDeviceCaps structure in HostIOMMUDevice and a new interface between vIOMMU and HostIOMMUDevice.

Re: [Bug Report] Possible Missing Endianness Conversion

CCing Jason. On Mon, Jun 24, 2024 at 4:30 PM Xoykie wrote: > > The virtio packed virtqueue support patch[1] suggests converting > endianness by lines: > > virtio_tswap16s(vdev, &e->off_wrap); > virtio_tswap16s(vdev, &e->flags); > > Though both of these conversion statements aren't present in the

Re: linux-user crash in python test

On Jun 24 2024, Peter Maydell wrote: > Just to check, does the python you're running this on > have the change from > https://github.com/python/cpython/pull/110659 Yes, this is python 3.11.9. -- Andreas Schwab, SUSE Labs, sch...@suse.de GPG Key fingerprint = 0196 BAD8 1CE9 1970 F4BE 1748 E4D4

Re: [PATCH v5 25/65] i386/tdx: Add property sept-ve-disable for tdx-guest object

On Fri, Jun 14, 2024 at 08:49:57AM +0100, Daniel P. Berrangé wrote: > On Fri, Jun 14, 2024 at 09:04:33AM +0800, Xiaoyao Li wrote: > > On 6/13/2024 4:35 PM, Duan, Zhenzhong wrote: > > > > > > > > > > -Original Message- > > > > From: Li, Xiaoyao > > > > Subject: Re: [PATCH v5 25/65] i386/t

Re: [PATCH v3 0/6] virtio,vhost: Add VIRTIO_F_IN_ORDER support

On 6/20/24 2:40 PM, Eugenio Perez Martin wrote: On Thu, Jun 20, 2024 at 7:56 PM Jonah Palmer wrote: The goal of these patches is to add support to a variety of virtio and vhost devices for the VIRTIO_F_IN_ORDER transport feature. This feature indicates that all buffers are used by the devic

Re: [PATCH v3 13/15] backends/igvm: Handle policy for SEV guests

On Fri, Jun 21, 2024 at 03:29:16PM +0100, Roy Hopkins wrote: > Adds a handler for the guest policy initialization IGVM section and > builds an SEV policy based on this information and the ID block > directive if present. The policy is applied using by calling > 'set_guest_policy()' on the Confident

Re: [PATCH v3 14/15] i386/sev: Add implementation of CGS set_guest_policy()

On Fri, Jun 21, 2024 at 03:29:17PM +0100, Roy Hopkins wrote: > The new cgs_set_guest_policy() function is provided to receive the guest > policy flags, SNP ID block and SNP ID authentication from guest > configuration such as an IGVM file and apply it to the platform prior to > launching the guest.

RE: [RFC PATCH 1/1] hw/arm: FW first ARM processor error injection.

Thanks Peter for the valuable comments. >-Original Message- >From: Peter Maydell >Sent: 24 June 2024 14:48 >To: Shiju Jose >Cc: qemu-devel@nongnu.org; linux-e...@vger.kernel.org; Jonathan Cameron >; mchehab+hua...@kernel.org; tanxiaofei >; Zengtao (B) ; Linuxarm > >Subject: Re: [RFC PAT

Re: [PATCH 1/1] hw/i386/acpi-build: add OSHP method support for SHPC driver load

> > > > +static Aml *build_oshp_method(void) > > > > +{ > > > > +    Aml *method; > > > > + > > > > +    /* > > > > +     * Request control of SHPC hotplug via OSHP method, > > > > +     * no need parameter and return value in acpi_pcihp. > > > > +     */ > > > > > > Quote spec and earliest version

Re: [PATCH v1 1/2] aspeed/soc: fix coverity issue

On 6/24/24 4:01 PM, Peter Maydell wrote: On Mon, 24 Jun 2024 at 14:58, Cédric Le Goater wrote: On 6/24/24 2:18 PM, Peter Maydell wrote: On Wed, 19 Jun 2024 at 10:35, Jamin Lin wrote: Fix coverity defect: DIVIDE_BY_ZERO. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 6 ++

Re: linux-user crash in python test

On Mon, 24 Jun 2024 at 15:20, Andreas Schwab wrote: > > $ /usr/bin/python3.11 -m unittest -v > test.test_signal.StressTest.test_stress_modifying_handlers > test_stress_modifying_handlers > (test.test_signal.StressTest.test_stress_modifying_handlers) ... ok > > ---

linux-user crash in python test

$ /usr/bin/python3.11 -m unittest -v test.test_signal.StressTest.test_stress_modifying_handlers test_stress_modifying_handlers (test.test_signal.StressTest.test_stress_modifying_handlers) ... ok -- Ran 1 test in 0.526s OK $ qem

Re: [PATCH v3 15/15] sev: Provide sev_features flags from IGVM VMSA to KVM_SEV_INIT2

On Fri, Jun 21, 2024 at 03:29:18PM +0100, Roy Hopkins wrote: > IGVM files can contain an initial VMSA that should be applied to each > vcpu as part of the initial guest state. The sev_features flags are > provided as part of the VMSA structure. However, KVM only allows > sev_features to be set duri

Re: [PATCH v3 09/15] docs/system: Add documentation on support for IGVM

On Fri, Jun 21, 2024 at 03:29:12PM +0100, Roy Hopkins wrote: > IGVM support has been implemented for Confidential Guests that support > AMD SEV and AMD SEV-ES. Add some documentation that gives some > background on the IGVM format and how to use it to configure a > confidential guest. > > Signed-o

Re: [PATCH v1 1/2] aspeed/soc: fix coverity issue

On Mon, 24 Jun 2024 at 14:58, Cédric Le Goater wrote: > > On 6/24/24 2:18 PM, Peter Maydell wrote: > > On Wed, 19 Jun 2024 at 10:35, Jamin Lin wrote: > >> > >> Fix coverity defect: DIVIDE_BY_ZERO. > >> > >> Signed-off-by: Jamin Lin > >> --- > >> hw/arm/aspeed_ast27x0.c | 6 ++ > >> 1 file

Re: [PATCH v3 04/15] hw/core/machine: Add igvm-cfg object and processing for IGVM files

On Fri, Jun 21, 2024 at 03:29:07PM +0100, Roy Hopkins wrote: > An IGVM file contains configuration of guest state that should be > applied during configuration of the guest, before the guest is started. > > This patch allows the user to add an igvm-cfg object to the machine > configuration that al

[PULL v2 15/23] Revert "host/i386: assume presence of SSE2"

This reverts commit b18236897ca15c3db1506d8edb9a191dfe51429c. The x86-64 instruction set can now be tuned down to x86-64 v1 or i386 Pentium Pro. Signed-off-by: Paolo Bonzini --- host/include/i386/host/cpuinfo.h | 1 + util/cpuinfo-i386.c | 1 + host/include/i386/ho

[PULL v2 00/23] Misc changes for 2024-06-22

The following changes since commit c9ba79baca7c673098361e3a687f72d458e0d18a: Merge tag 'pull-target-arm-20240622' of https://git.linaro.org/people/pmaydell/qemu-arm into staging (2024-06-22 09:56:49 -0700) are available in the Git repository at: https://gitlab.com/bonzini/qemu.git tags/for

Re: [PATCH v1 1/2] aspeed/soc: fix coverity issue

On 6/24/24 2:18 PM, Peter Maydell wrote: On Wed, 19 Jun 2024 at 10:35, Jamin Lin wrote: Fix coverity defect: DIVIDE_BY_ZERO. Signed-off-by: Jamin Lin --- hw/arm/aspeed_ast27x0.c | 6 ++ 1 file changed, 6 insertions(+) diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c ind

Re: [PATCH 1/1] hw/i386/acpi-build: add OSHP method support for SHPC driver load

On Mon, Jun 24, 2024 at 01:34:08PM +, Gao,Shiyuan wrote: > > > SHPC driver will be loaded fail in i440fx platform, the dmesg shows > > > that OS cannot get control of SHPC hotplug and hotplug device to > > > the PCI bridge will fail when we use SHPC Native type: > > > > > >   [3.336059] shpchp

Re: [PATCH v3 00/15] Introduce support for IGVM files

On Fri, Jun 21, 2024 at 03:29:03PM +0100, Roy Hopkins wrote: > Based-on: 02d9c38236 > > Here is v3 of the set of patches to add support for IGVM files to QEMU. > > Firstly, apologies for the long gap between v2 and v3. This was due to a > number > of factors, but particularly holding back until

Re: [RFC PATCH 1/1] hw/arm: FW first ARM processor error injection.

On Fri, 21 Jun 2024 at 17:52, shiju.jose--- via wrote: > > From: Shiju Jose > > diff --git a/hw/arm/arm_error_inject.c b/hw/arm/arm_error_inject.c > new file mode 100644 > index 00..953a9d6705 > --- /dev/null > +++ b/hw/arm/arm_error_inject.c > @@ -0,0 +1,49 @@ > +/* > + * CXL Type 3 (

Re: [PATCH] hw/arm/smmu-common: Replace smmu_iommu_mr with smmu_find_sdev

On Wed, 19 Jun 2024 at 01:22, Nicolin Chen wrote: > > The caller of smmu_iommu_mr wants to get sdev for smmuv3_flush_config(). > > Do it directly instead of bridging with an iommu mr pointer. > > Signed-off-by: Nicolin Chen > --- > hw/arm/smmu-common.c | 8 ++-- > hw/arm/smmuv3.c

Re: [PATCH 1/1] hw/i386/acpi-build: add OSHP method support for SHPC driver load

> > SHPC driver will be loaded fail in i440fx platform, the dmesg shows > > that OS cannot get control of SHPC hotplug and hotplug device to > > the PCI bridge will fail when we use SHPC Native type: > > > >   [3.336059] shpchp :00:03.0: Requesting control of SHPC hotplug via > >OSHP (\_SB_.PC

Re: [PATCH v3 0/2] tests/avocado: make sbsa-ref working with >1 core

On Thu, 20 Jun 2024 at 11:19, Marcin Juszkiewicz wrote: > > Recent changes made sbsa-ref crash when more than 1 cpu core was used. > We handle it in firmware now so one patch updates it to the working > snapshot (TF-A 2.11 + EDK2 snapshot + EDK2-platforms snapshot). > > Other change drops "-smp 1"

Re: [PATCH v3 03/15] backends/igvm: Add IGVM loader and configuration

On Fri, Jun 21, 2024 at 03:29:06PM +0100, Roy Hopkins wrote: > Adds an IGVM loader to QEMU which processes a given IGVM file and > applies the directives within the file to the current guest > configuration. > > The IGVM loader can be used to configure both confidential and > non-confidential gues

Re: [PATCH v2 2/2] target/arm: Enable FEAT_Debugv8p8 for -cpu max

On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: > > Enable FEAT_Debugv8p8 for max CPU. This feature is out of scope for QEMU > since it concerns the external debug interface for JTAG, but is > mandatory in Armv8.8 implementations, hence it is reported as supported > in the ID registers. > > Si

Re: [PATCH v2 1/2] target/arm: Move initialization of debug ID registers

On Fri, 21 Jun 2024 at 15:39, Gustavo Romero wrote: > > Move the initialization of the debug ID registers to aa32_max_features, > which is used to set the 32-bit ID registers. This ensures that the > debug ID registers are consistently set for the max CPU in a single > place. > > Signed-off-by: Gu

<    1   2   3   4   >