On Wed, Jun 26, 2024 at 11:22:46AM +1000, Alistair Francis wrote:
>
> On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote:
> >
> > Hi Alistair,
> >
> > IOPMP can applies all device. In this patch series, PCI devices on the
> > bridge
> > can connect to IOPMP by pci_setup_iommu(), but other
You asked for a summary of my review findings. Here it is:
* PATCH 01: DO-NOT-MERGE, not reviewed
* PATCH 02, 05..07, 10..12: R-by or A-by
* PATCH 03: R-by with straightforward minor adjustments
* PATCH 04, 08: R-by with commit message and doc tweaks
* PATCH 09:
- Commit message tweaks
John Snow writes:
> Eliminate the "Example" sections in QAPI doc blocks, converting them
> into QMP example code blocks. This is generally done in this patch by
> converting "Example:" or "Examples:" lines into ".. code-block:: QMP"
> lines.
[...]
> diff --git a/qapi/migration.json
On 2024-06-23 6:03 p.m., Richard Henderson wrote:
On 6/23/24 10:53, Richard Henderson wrote:
On 6/22/24 19:03, Brad Smith wrote:
util: fix building on OpenBSD/powerpc
Signed-off-by: Brad Smith
---
util/cpuinfo-ppc.c | 20
1 file changed, 12 insertions(+), 8
On 2024-06-23 6:08 p.m., Richard Henderson wrote:
On 6/23/24 10:55, Richard Henderson wrote:
On 6/22/24 19:12, Brad Smith wrote:
+ if (sysctl(mib, 2, , , NULL, 0) != -1) {
+ if (ID_AA64ISAR0_ATOMIC(isar0) >= ID_AA64ISAR0_ATOMIC_IMPL)
+ info |= CPUINFO_LSE;
+ if
This patch corrects minor typographical errors to ensure the ASCII art
aligns with the explanations provided. Specifically, it fixes an
incorrect root port reference and removes redundant words.
Signed-off-by: Hyeongtak Ji
---
docs/system/devices/cxl.rst | 6 +++---
1 file changed, 3
Hi Salil and Igor,
On 6/26/24 9:51 AM, Salil Mehta wrote:
On Wed, Jun 5, 2024 at 3:03 PM Igor Mammedov mailto:imamm...@redhat.com>> wrote:
On Sun, 2 Jun 2024 18:03:05 -0400
"Michael S. Tsirkin" mailto:m...@redhat.com>> wrote:
> On Thu, May 30, 2024 at 12:42:33AM +0100, Salil Mehta
On 2024/6/5 上午10:15, Jiaxun Yang wrote:
It was missed out in previous commit.
Fixes: b4a12dfc2132 ("hw/intc/loongarch_ipi: Rename as loongson_ipi")
Signed-off-by: Jiaxun Yang
---
hw/intc/loongarch_ipi.c | 347
1 file changed, 347
On 6/21/24 8:40 PM, Cédric Le Goater wrote:
On 6/21/24 4:47 PM, Shivaprasad G Bhat wrote:
On 6/21/24 2:19 PM, Cédric Le Goater wrote:
Could you please describe the host/guest OS, hypervisor, processor
and adapter ?
Here is the environment info,
pSeries:
Host : Power10 PowerVM Lpar
Hi Rajnesh,
On 2024/6/19 下午 11:27, Rajnesh Kanwal wrote:
This commit adds logic to records CTR entries of different types
and adds required hooks in TCG and interrupt/Exception logic to
record events.
This commit also adds support to invoke freeze CTR logic for breakpoint
exceptions and
Hi,
On Monday, June 24, 2024 5:06:42 PM GMT+5:30 Eugenio Perez Martin wrote:
> [...]
> > > > /* Shadow virtqueue to relay notifications */
> > > > typedef struct VhostShadowVirtqueue {
> > > >
> > > > +/* Virtio queue shadowing */
> > > > +VirtQueue *vq;
> > > > +
> > > > +/*
Nested SMMUv3 feature requires the support/presence of host-level SMMUv3
instance(s). Add a helper to read the sysfs for the number of instances.
Log them in a vms list using a new struct VirtNestedSmmu.
This will be used by a following patch to assign a passthrough device to
corresponding nested
Hi all,
This is a draft solution adding multiple nested SMMU instances to VM.
The main goal of the series is to collect opinions, to figure out a
reasonable solution that would fit our needs.
I understood that there are concerns regarding this support, from our
previous discussion:
A following patch will add a new MMIO region for nested SMMU instances.
This macro will be repeatedly used to set offsets and MMIO sizes in both
virt and virt-acpi-build.
Signed-off-by: Nicolin Chen
---
hw/arm/virt.c | 2 +-
include/hw/arm/virt.h | 3 +++
2 files changed, 4
On Tue, 25 Jun 2024 19:18, Zhao Liu wrote:
Hi Manos,
On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote:
Date: Wed, 19 Jun 2024 23:14:02 +0300
From: Manos Pitsidianakis
Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with
x-pl011-rust in arm virt machine
On Wed, Jun 26, 2024 at 12:44:29AM +0200, Maciej S. Szmigiero wrote:
> On 25.06.2024 19:25, Peter Xu wrote:
> > On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote:
> > > Hi Peter,
> >
> > Hi, Maciej,
> >
> > >
> > > On 23.06.2024 22:27, Peter Xu wrote:
> > > > On Tue, Jun 18,
I’m sorry, but currently Zhaoxin has not released any specs or
datasheets related
to the current patch. Zhaoxin CPUs are compatible with the x86 architecture,
particularly with Intel. For example, you can refer to the Intel SDM
(Software
Developer’s Manual). Regarding the current patch, except
A nested SMMU must use iommufd ioctls to communicate with the host-level
SMMU instance for 2-stage translation support. Add an iommufd link to the
ARM virt-machine, allowing QEMU command to pass in an iommufd object.
Signed-off-by: Nicolin Chen
---
hw/arm/virt.c | 14 ++
From: Dongwon Kim
Negative page number means the page with that number does not
belong to the notebook so it shouldn't be used as a valid page
number in gd_vc_find_by_page. This function should just return
null in such case.
This change, however, will cause a segfault during detaching
The crash was reported in MAC OS and NixOS, here is the link for this bug
https://gitlab.com/qemu-project/qemu/-/issues/2334
https://gitlab.com/qemu-project/qemu/-/issues/2321
The root cause is the function virtio_pci_set_guest_notifiers() was not called
in the virtio_input device.So the
On Tue, Jun 25, 2024 at 6:21 AM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> Generate device tree entry for riscv-iommu PCI device, along with
> mapping all PCI device identifiers to the single IOMMU device instance.
>
> Signed-off-by: Tomasz Jeznach
> Signed-off-by: Daniel
On 25.06.2024 19:25, Peter Xu wrote:
On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote:
Hi Peter,
Hi, Maciej,
On 23.06.2024 22:27, Peter Xu wrote:
On Tue, Jun 18, 2024 at 06:12:18PM +0200, Maciej S. Szmigiero wrote:
From: "Maciej S. Szmigiero"
This is an updated v1
VIRT_SMMU can be used as an emulated SMMU, i.e. iommu=smmuv3. However, the
MMIO space for VIRT_SMMU isn't large enough to accommodate multiple nested
SMMUv3 instances. Add a new VIRT_NESTED_SMMU to separate MMIO space.
Meanwhile, a nested SMMUv3 could only work with a vfio-pci device that is
On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> This header will be used by the RISC-V IOMMU emulation to be added
> in the next patch. Due to its size it's being sent in separate for
> an easier review.
>
> One thing to notice is that this header can
From: Eric Auger
To handle SMMUv3 nested stage support it is practical to
expose the guest with reserved memory regions (RMRs)
covering the IOVAs used by the host kernel to map
physical MSI doorbells.
Those IOVAs belong to [0x800, 0x810] matching
MSI_IOVA_BASE and MSI_IOVA_LENGTH
For a nested SMMUv3, the ATS capaiblity is decided by the underlying HW,
and then reflected in the IDR0 register of the vSMMU.
The IORT on the other hand could allow it to be always enabled, relying
on the guest-level SMMU kernel driver to disable ATS feature if the ATS
bit isn't set in IDR0.
On Mon, Jun 24, 2024 at 11:47 AM Ethan Chen wrote:
>
> Hi Alistair,
>
> IOPMP can applies all device. In this patch series, PCI devices on the bridge
> can connect to IOPMP by pci_setup_iommu(), but other devices need change their
> memory access address space from system memory to IOPMP by
On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote:
> During live migration, receive current downtime from source
> and start a downtime timer. When the destination dowtime
> and added source downtime exceeds downtime limit for more
> than switchover limit, abort live migration on
On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza
wrote:
>
> Add a simple guideline to use the existing RISC-V IOMMU support we just
> added.
>
> This doc will be updated once we add the riscv-iommu-sys device.
>
> Signed-off-by: Daniel Henrique Barboza
> ---
> docs/specs/index.rst
On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza
wrote:
>
> To test the RISC-V IOMMU emulation we'll use its PCI representation.
> Create a new 'riscv-iommu-pci' libqos device that will be present with
> CONFIG_RISCV_IOMMU. This config is only available for RISC-V, so this
> device will
On Tue, Jun 25, 2024 at 6:20 AM Daniel Henrique Barboza
wrote:
>
> From: Tomasz Jeznach
>
> Extend memory transaction attributes with process identifier to allow
> per-request address translation logic to use requester_id / process_id
> to identify memory mapping (e.g. enabling IOMMU w/ PASID
Each pxb bus created for a nested SMMU has a reserved bus number, allowing
a hotplug device to attach to the bus in a later stage.
Read it out to apply to the id_count calculation.
Signed-off-by: Nicolin Chen
---
hw/arm/virt-acpi-build.c | 28
include/hw/arm/virt.h
With iommu=nested-smmuv3, there could be multiple nested SMMU instances in
the vms. A passthrough device must to look up for its iommu handler in its
sysfs node, and then link to the nested SMMU instance created for the same
iommu handler. This isn't easy to do.
Add an auto-assign piece after all
There can be multiple PCI buses behind different SMMU nodes. And each pair
should be associated in the IORT table too when building the ID mappings.
Create multiple SMMU nodes if needed, store their offsets in an array.
Signed-off-by: Nicolin Chen
---
hw/arm/virt-acpi-build.c | 36
On Tue, Jun 25, 2024 at 9:48 PM wrote:
>
> From: Frank Chang
>
> Currently, the implied extensions are enabled and checked in
> riscv_cpu_validate_set_extensions(). However, the order of enabling the
> implied extensions must follow a strict sequence, which is error-prone.
>
> This patchset
Now, all passthrough devices that should benefit from the nested SMMUv3
feature are assigned to dedicated pxb buses. So, the default PCI bus can
be only used by emulated devices.
In theory, these emualted devices can be still attached to an emualted
SMMUv3 instance, yet there is no gain doing
On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote:
>
> The Control Transfer Records (CTR) extension provides a method to
> record a limited branch history in register-accessible internal chip
> storage.
>
> This extension is similar to Arch LBR in x86 and BRBE in ARM.
> The Extension has been
On Tue, Jun 25, 2024 at 9:47 PM wrote:
>
> From: Frank Chang
>
> RISCVCPUImpliedExtsRule is created to store the implied rules.
> 'is_misa' flag is used to distinguish whether the rule is derived
> from the MISA or other extensions.
> 'ext' stores the MISA bit if 'is_misa' is true. Otherwise, it
On Tue, Jun 25, 2024 at 05:31:19PM +0100, Joao Martins wrote:
> The device-state multifd scaling is a take on improving switchover phase,
> and we will keep improving it whenever we find things... but the
That'll be helpful, thanks. Just a quick note that "reducing downtime" is
a separate issue
Hi Igor,
On Wed, Jun 5, 2024 at 3:03 PM Igor Mammedov wrote:
> On Sun, 2 Jun 2024 18:03:05 -0400
> "Michael S. Tsirkin" wrote:
>
> > On Thu, May 30, 2024 at 12:42:33AM +0100, Salil Mehta wrote:
> > > Virtual CPU hotplug support is being added across various
> architectures[1][3].
> > > This
On Tue, Jun 25, 2024 at 9:47 PM wrote:
>
> From: Frank Chang
>
> Introduce helpers to enable the extensions based on the implied rules.
> The implied extensions are enabled recursively, so we don't have to
> expand all of them manually. This also eliminates the old-fashioned
> ordering
On Thu, Jun 20, 2024 at 1:28 AM Rajnesh Kanwal wrote:
>
> This series enables Control Transfer Records extension support on riscv
> platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
> The Extension has been stable and the latest release can be found here [0]
Can you be
On 6/25/24 07:46, Alexei Filippov wrote:
Was added call backs for machine specific pmu events.
Simplify monitor functions by adding new hash table, which going to map
counter number and event index.
Was added read/write callbacks which going to simplify support for events,
which expected to have
On Mon, 24 Jun 2024 20:14, Paolo Bonzini wrote:
Yes, I agree. However, considering we haven't even checked the
situation
with what language features are required by any idiomatic bindings vs the
1.63 version that we need to support for Debian, I think it's a bit
premature to make it mandatory.
On Tue, Jun 25, 2024 at 08:10:23PM +0900, Shota Imamura wrote:
> Dear Peter Xu,
>
> Thank you for your feedback.
>
> > It looks like this patch will introduce a ring but still it keeps the
> > bitmaps around.
> >
> > Could you elaborate your motivation of this work? It’ll be interesting to
> >
On 6/24/24 14:24, Cédric Le Goater wrote:
The following changes since commit d89b64beea65f77c21a553cb54cb97b75c53dc21:
Merge tag 'pull-request-2024-06-24' ofhttps://gitlab.com/thuth/qemu into
staging (2024-06-24 11:57:11 -0700)
are available in the Git repository at:
On Wed, Jun 26, 2024 at 12:18:55AM +0800, Zhao Liu wrote:
> Hi Manos,
>
> On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote:
> > Date: Wed, 19 Jun 2024 23:14:02 +0300
> > From: Manos Pitsidianakis
> > Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with
> >
On Tue, 25 Jun 2024 at 20:15, Daniel P. Berrangé wrote:
>
> On Wed, Jun 26, 2024 at 12:18:55AM +0800, Zhao Liu wrote:
> > Hi Manos,
> >
> > On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote:
> > > Date: Wed, 19 Jun 2024 23:14:02 +0300
> > > From: Manos Pitsidianakis
> > >
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/vec_helper.c | 24
1 file changed, 16 insertions(+), 8
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/helper.h| 10 ++
target/arm/tcg/a64.decode | 16 +++
target/arm/tcg/translate-a64.c | 206 +
target/arm/tcg/vec_helper.c| 72
4 files changed, 180
MLA, MLS, SQDMULH, SQRDMULH, were converted with 8db93dcd3def
and f80701cb44d, and this code should have been removed then.
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 93 --
1 file changed, 93 deletions(-)
diff --git
On Tue, 25 Jun 2024 14:18, Paolo Bonzini wrote:
The typeof_strip_qual() is most useful for the atomic fetch-and-modify
operations in atomic.h, but it can be used elsewhere as well. For example,
QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a
requirement.
Move the
Input denormals cause the Javascript inexact bit
(output to Z) to be set.
Cc: qemu-sta...@nongnu.org
Fixes: 6c1f6f2733a ("target/arm: Implement ARMv8.3-JSConv")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2375
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
On Tue, Jun 25, 2024 at 10:53:41AM -0400, Peter Xu wrote:
> Then the question is how should we suggest the user to specify these two
> parameters.
>
> The cover letter used:
>
> migrate_set_parameter downtime-limit 300
> migrate_set_parameter switchover-limit 10
What this means is that in
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 33 ++---
2 files changed, 13 insertions(+), 23 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 7 +
target/arm/tcg/translate-a64.c | 54 ++
2 files changed, 35 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/a64.decode
On Tue, 25 Jun 2024 19:00, Zhao Liu wrote:
[snip]
This is for future-proofing the Rust integration in general. I
haven't been
able to compile under macos yet because bindgen cannot find the system clang
header. I also don't have a windows pc to test it on. But it should work
theoretically
On Tue, 11 Jun 2024 at 09:36, Akihiko Odaki wrote:
> > […] I also
> > definitely think host cursor integration is useful and valuable, at
> > least in absolute pointing mode - for example, when the host system is
> > itself being remote controlled, and also to avoid the cursor being
> > cropped
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 6 +
target/arm/tcg/translate-a64.c | 238 ++---
2 files changed, 74 insertions(+), 170 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 +
target/arm/tcg/translate-a64.c | 77 +-
2 files changed, 31 insertions(+), 48 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
On Fri, Jun 21, 2024 at 07:32:20AM -0700, Elena Ufimtseva wrote:
> Introduce capability switchover_abort and migration parameter switchover_limit
> to allow for live migration abort when the source downtime exceeded by
> switchover_limit.
>
> Signed-off-by: Elena Ufimtseva
> ---
>
Preparation for improved u2f-passthru hidraw handle lifetimes:
These callbacks can be implemented by the backing implementation,
i.e. u2f-passthru or u2f-emulated.
The start callback is invoked when the device receives an INTR IN, and
the stop callback is invoked when the endpoint has been
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 4
target/arm/tcg/translate-a64.c | 36 --
2 files changed, 12 insertions(+), 28 deletions(-)
diff --git a/target/arm/tcg/a64.decode
On 6/25/24 04:18, Paolo Bonzini wrote:
The typeof_strip_qual() is most useful for the atomic fetch-and-modify
operations in atomic.h, but it can be used elsewhere as well. For example,
QAPI_LIST_LENGTH() assumes that the argument is not const, which is not a
requirement.
Move the macro to
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/translate-a64.c | 52 +-
1 file changed, 26 insertions(+), 26 deletions(-)
diff --git a/target/arm/tcg/translate-a64.c b/target/arm/tcg/translate-a64.c
index 2697c4b305..57cdde008e
New DCD command definitions updated in response to review comments
from Markus.
- Used Cxl instead of CXLX for newly added types.
- Expanded some abreviations in type names to be easier to read.
- Additional documentation for some fields.
- Replace slightly vague cxl r3.1 references with
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 3 +++
target/arm/tcg/translate-a64.c | 35 --
2 files changed, 11 insertions(+), 27 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
The inner loop, bounded by eltspersegment, must not be
larger than the outer loop, bounded by elements.
Cc: qemu-sta...@nongnu.org
Fixes: 18fc2405781 ("target/arm: Implement SVE fp complex multiply add
(indexed)")
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/2376
Reviewed-by: Peter
Convert another hand-full of instructions, plus fixes
for two issues that are related.
r~
Richard Henderson (13):
target/arm: Fix VCMLA Dd, Dn, Dm[idx]
target/arm: Fix SQDMULH (by element) with Q=0
target/arm: Fix FJCVTZS vs flush-to-zero
target/arm: Convert SQRDMLAH, SQRDMLSH to
Reviewed-by: Peter Maydell
Signed-off-by: Richard Henderson
---
target/arm/tcg/a64.decode | 2 ++
target/arm/tcg/translate-a64.c | 20 +---
2 files changed, 7 insertions(+), 15 deletions(-)
diff --git a/target/arm/tcg/a64.decode b/target/arm/tcg/a64.decode
index
On 25/06/2024 15:53, Peter Xu wrote:
> On Tue, Jun 25, 2024 at 12:38:50PM +0100, Joao Martins wrote:
>> On 24/06/2024 20:41, Peter Xu wrote:
>>> On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote:
@@ -2659,6 +2698,18 @@ qemu_loadvm_section_start_full(QEMUFile *f,
On Mon, Jun 24, 2024 at 09:51:18PM +0200, Maciej S. Szmigiero wrote:
> Hi Peter,
Hi, Maciej,
>
> On 23.06.2024 22:27, Peter Xu wrote:
> > On Tue, Jun 18, 2024 at 06:12:18PM +0200, Maciej S. Szmigiero wrote:
> > > From: "Maciej S. Szmigiero"
> > >
> > > This is an updated v1 patch series of
The Linux kernel presumes a hidraw device to be "active" as long
as an open handle to its character device exists, and during that time
will actively poll its bus for new messages.
The u2f-passthru device keeps an open handle to the hidraw character device
for its entire lifetime, wasting power
FIDO U2FHID features a keep-alive response command (code 0xbb). A
keep-alive response signifies that the request is being processed
and the transaction should not be closed yet.
u2f-passthru does not recognize this command, and hence closes the
transaction prematurely upon receiving it. This
Prepare for implementing the FIDO-U2F keepalive feature:
Represent all u2fhid frames using one coherent structure,
and make casts explicit.
Signed-off-by: David Bouman
---
hw/usb/u2f-passthru.c | 73 ++-
1 file changed, 44 insertions(+), 29 deletions(-)
Hello,
The u2f-passthru device is currently broken for (at least) the Yubikey 5.
(gitlab: https://gitlab.com/qemu-project/qemu/-/issues/2293)
This patchset aims to fix the issue by properly handling the
U2F keepalive response in the u2f-passthru device.
I initially suspected the hidraw chardev
These came from review after Michael Tsirkin had queued the DCD stuff on
his QEMU tree. For reasons unrelated to this series, the pull request
was rejected but I'm assuming Michael will send a fresh pull request soon.
Hence this is based on top of qemu/master with the DCD patches from
Markus suggested that we make the unstable. I don't expect these
interfaces to change because of their tight coupling to the Compute
Express Link (CXL) Specification, Revision 3.1 Fabric Management API
definitions which can only be extended in backwards compatible way.
However, there seems little
On 26.05.24 22:29, Vincent Vanlaer wrote:
Non-active block commits do not discard blocks only containing zeros,
causing images to lose sparseness after the commit. This commit fixes
that by writing zero blocks using blk_co_pwrite_zeroes rather than
writing them out as any oother arbitrary data.
On 30.04.24 20:05, Denis V. Lunev via wrote:
Preallocate filter allows to implement really interesting setups.
Assume that we have
* shared block device, f.e. iSCSI LUN, implemented with some HW device
* clustered LVM on top of it
* QCOW2 image stored inside LVM volume
This allows very cheap
Hi Manos,
On Wed, Jun 19, 2024 at 11:14:02PM +0300, Manos Pitsidianakis wrote:
> Date: Wed, 19 Jun 2024 23:14:02 +0300
> From: Manos Pitsidianakis
> Subject: [RFC PATCH v3 5/5] DO NOT MERGE: replace TYPE_PL011 with
> x-pl011-rust in arm virt machine
> X-Mailer: git-send-email 2.44.0
>
>
On 2024/6/20 12:29 PM, Richard Henderson wrote:
On 6/13/24 10:51, Max Chou wrote:
This commit references the sve_ldN_r/sve_stN_r helper functions in ARM
target to optimize the vector unmasked unit-stride load/store
instructions by following items:
* Get the loose bound of activate elements
*
Existing AARCH64 virt test functions do not have AARCH64 in their name.
To add RISC-V virt related test cases, better to rename existing
functions to indicate they are ARM only.
Signed-off-by: Sunil V L
Reviewed-by: Alistair Francis
Reviewed-by: Igor Mammedov
---
To test ACPI tables, edk2 needs to be booted with a disk image having
EFI partition. This image is created using UefiTestToolsPkg.
The image is generated using tests/uefi-test-tools source.
Signed-off-by: Sunil V L
---
.../bios-tables-test.riscv64.iso.qcow2 | Bin 0 -> 16896 bytes
Richard Henderson writes:
> Hiya,
>
> I've just discovered a 32-bit build issue that is probably 3 weeks old.
>
> While we still support 32-bit builds at all, I would request that we
> improve our cross-i686 testing. For instance: we have cross-i686-user
> and cross-i686-tci. There is some
To search for expected AML files under ${arch}/${machine} path, set this
field for X86 related test cases.
Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
---
tests/qtest/bios-tables-test.c | 77 --
1 file changed, 64 insertions(+), 13 deletions(-)
diff
On Tue, Jun 25, 2024 at 12:38:50PM +0100, Joao Martins wrote:
> On 24/06/2024 20:41, Peter Xu wrote:
> > On Fri, Jun 21, 2024 at 07:32:21AM -0700, Elena Ufimtseva wrote:
> >> @@ -2659,6 +2698,18 @@ qemu_loadvm_section_start_full(QEMUFile *f,
> >> MigrationIncomingState *mis,
> >> if
On 6/25/24 5:04 PM, Philippe Mathieu-Daudé wrote:
Hi Cédric,
On 3/7/23 15:24, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/sd/sd.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/hw/sd/sd.c b/hw/sd/sd.c
index 5ff132139ea9..95cb46b87519 100644
--- a/hw/sd/sd.c
edk2-funcs.sh which is used in this Makefile, was removed in the commit
c28a2891f3 ("edk2: update build script"). It is replaced with a python
based script. So, update the Makefile and add the configuration file as
required to support the python based build script.
Signed-off-by: Sunil V L
Was added call backs for machine specific pmu events.
Simplify monitor functions by adding new hash table, which going to map
counter number and event index.
Was added read/write callbacks which going to simplify support for events,
which expected to have different behavior.
Signed-off-by: Alexei
kvm_riscv_handle_sbi() may return not supported return code to not
trigger qemu abort with vendor-specific sbi.
Add new error path to provide proper error in case of
qemu_chr_fe_read_all() may not return sizeof(ch), because exactly zero
just means we failed to read input, which can happen, so
As per the step 5 in the process documented in bios-tables-test.c,
generate the expected ACPI AML data files for RISC-V using the
rebuild-expected-aml.sh script and update the
bios-tables-test-allowed-diff.h.
These are all new files being added for the first time. Hence, iASL diff
output is not
Enable building the test application for RISC-V with appropriate
dependencies updated.
Signed-off-by: Sunil V L
Acked-by: Gerd Hoffmann
Acked-by: Alistair Francis
Acked-by: Igor Mammedov
---
tests/uefi-test-tools/UefiTestToolsPkg/UefiTestToolsPkg.dsc | 6 +-
1 file changed, 5
Currently, bios-table-test doesn't support RISC-V. This series enables
the framework changes required and basic testing. Things like NUMA
related test cases will be added later.
This needs refactoring/renaming of ARM64 and x86 bios table tests.
Importantly, the test cases now look for the
On 6/25/24 5:32 PM, Philippe Mathieu-Daudé wrote:
On 25/6/24 17:13, Cédric Le Goater wrote:
On 6/25/24 5:04 PM, Philippe Mathieu-Daudé wrote:
Hi Cédric,
On 3/7/23 15:24, Cédric Le Goater wrote:
Signed-off-by: Cédric Le Goater
---
hw/sd/sd.c | 6 ++
1 file changed, 6 insertions(+)
Was added call backs for machine specific pmu events.
Simplify monitor functions by adding new hash table, which going to map
counter number and event index.
Was added read/write callbacks which going to simplify support for events,
which expected to have different behavior.
Signed-off-by: Alexei
RISC-V virt is currently missing default type for block devices. Without
this being set, proper backend is not created when option like -cdrom
is used. So, make the virt board's default block device type be
IF_VIRTIO similar to other architectures.
We also need to set no_cdrom to avoid getting a
On 6/25/24 04:37, Andreas Schwab wrote:
When running qemu-riscv64 on a riscv64 host executing a ET_EXEC riscv64
binary it cannot allocate memory for the stack:
$ qemu-riscv64 -d page ./hello.riscv64
host mmap_min_addr=0x1
Locating guest address space @ 0x3ee000
page layout changed following
> > > + # > WARNING: Project specifies a minimum meson_version '>=0.63.0'
> > > but
> > > + # > uses features which were added in newer versions:
> > > + # > * 0.64.0: {'fs.copyfile'}
> > > + # > * 1.0.0: {'dependencies arg in rust.bindgen', 'module rust as
> > > stable
Same machine name can be used by different architectures. Hence, create
aarch64 folder and move all aarch64 related AML files for virt machine
inside.
Signed-off-by: Sunil V L
Reviewed-by: Igor Mammedov
---
tests/data/acpi/{ => aarch64}/virt/APIC | Bin
.../data/acpi/{ =>
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