On 2025-09-06 07:18, Richard Henderson wrote:
All uses have been replaced with tb_flush__exclusive.
Signed-off-by: Richard Henderson
---
include/exec/tb-flush.h | 19 ---
accel/tcg/tb-maint.c| 22 --
2 files changed, 8 insertions(+), 33 deletions(-)
Hi,
based on the low-level sketch in Zhao and my presentation,
I would like to propose this more high-level implementation
of pre/post migration callbacks.
Instead of dealing with pre/post callbacks, devices implement a
snapshot/restore mechanism; this way, C code sees a simplified
picture and d
We only need invalidate tbs from a single page, not flush
all translations.
Signed-off-by: Richard Henderson
---
hw/ppc/spapr_hcall.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c
index 1e936f35e4..aa2e5e1e84 100644
--- a/hw/p
+cc target and migration maintainers
On 9/6/25 07:18, Richard Henderson wrote:
It is too easy to mis-use tb_flush(). For instance, because of
the cpu argument, some parts assumed that it needed to call the
global flush function for every cpu. It is easy to forget that
the flush is not complete
On 2025-09-06 07:18, Richard Henderson wrote:
Expose a routine to be called when no cpus are running.
Simplify the do_tb_flush run_on_cpu callback, because
that is explicitly called with start_exclusive; there
is no need for the mmap_lock as well.
Signed-off-by: Richard Henderson
---
include/
On 2025-09-06 07:18, Richard Henderson wrote:
It is too easy to mis-use tb_flush(). For instance, because of
the cpu argument, some parts assumed that it needed to call the
global flush function for every cpu. It is easy to forget that
the flush is not complete when the call returns: we have me
On 2025-09-06 07:18, Richard Henderson wrote:
This hasn't been needed since d828b92b8a6
("accel/tcg: Introduce CF_BP_PAGE").
Signed-off-by: Richard Henderson
---
gdbstub/system.c | 4
gdbstub/user.c | 3 ---
2 files changed, 7 deletions(-)
Reviewed-by: Pierrick Bouvier
On 2025-09-06 07:18, Richard Henderson wrote:
The tb_flush within write_misa was incorrect. It assumed
that we could adjust the ISA of the current processor and
discard all TB and all would be well. But MISA is per vcpu,
so globally flushing TB does not mean that the TB matches
the MISA of any
We need not call tb_flush once per cpu, only once per vmload.
Move the call from cpu_common_post_load to a tcg-specific
vm_change_state_handler.
Signed-off-by: Richard Henderson
---
accel/tcg/tcg-all.c | 21 +
hw/core/cpu-system.c | 8
2 files changed, 21 insertion
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/ide/piix.c | 13 -
1 file changed, 13 deletions(-)
diff --git a/hw/ide/piix.c b/hw/ide/piix.c
index
a0f2709c6973420b9e07fc5cc3fa1ef12a8e3d42..138f8e1936b448cb9185018ba5744d3c5445abd9
100644
--- a/hw/ide/piix.c
+++ b/hw
Signed-off-by: Richard Henderson
---
accel/tcg/translate-all.c | 5 +
1 file changed, 1 insertion(+), 4 deletions(-)
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index d468667b0d..d7cc346414 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -288,
在 2025/9/5 下午4:55, Bibo Mao 写道:
On 2025/9/4 下午8:18, Song Gao wrote:
include CSR_MSGIS0-3, CSR_MSGIR and CSR_MSGIE.
Signed-off-by: Song Gao
---
target/loongarch/cpu-csr.h | 3 +++
target/loongarch/cpu.h | 11 +++
target/loongarch/machine.c | 27 +--
3
The tb_flush within write_misa was incorrect. It assumed
that we could adjust the ISA of the current processor and
discard all TB and all would be well. But MISA is per vcpu,
so globally flushing TB does not mean that the TB matches
the MISA of any given vcpu.
By recording misa in the tb state,
It is too easy to mis-use tb_flush(). For instance, because of
the cpu argument, some parts assumed that it needed to call the
global flush function for every cpu. It is easy to forget that
the flush is not complete when the call returns: we have merely
queued work to the cpu run loop.
(Phil, I
In all cases, we are already within start_exclusive.
Signed-off-by: Richard Henderson
---
plugins/core.c | 6 ++
plugins/loader.c | 2 +-
2 files changed, 3 insertions(+), 5 deletions(-)
diff --git a/plugins/core.c b/plugins/core.c
index c6e9ef1478..4ae1a6ae17 100644
--- a/plugins/core.c
We are going to disallow tb_flush from within the context
of a running cpu. Introduce a tcg-internal exception to
return out of the cpu run loop and perform the flush there.
Signed-off-by: Richard Henderson
---
include/exec/cpu-common.h | 1 +
accel/tcg/tcg-accel-ops-mttcg.c | 7 +++
Expose a routine to be called when no cpus are running.
Simplify the do_tb_flush run_on_cpu callback, because
that is explicitly called with start_exclusive; there
is no need for the mmap_lock as well.
Signed-off-by: Richard Henderson
---
include/exec/tb-flush.h | 1 +
accel/tcg/tb-maint.c|
Since 288a5fe980f, we don't link translation blocks
directly to palcode entry points. If we load palbr
from env instead of encoding the constant, we avoid
all need for tb_flush().
Signed-off-by: Richard Henderson
---
target/alpha/helper.h | 1 -
target/alpha/sys_helper.c | 6 --
targe
On 2025/09/03 7:42, Vivek Kasireddy wrote:
The res->blob pointer is only valid for blobs that have their
backing storage in memfd. Therefore, we cannot use it to determine
if a resource is a blob or not. Instead, we could use res->blob_size
to make this determination as it is non-zero for blob re
On 2025/09/03 7:42, Vivek Kasireddy wrote:
If the Guest provides a gpa (guest physical address) associated with
a PCI region, then we can obtain the hva (host virtual address) via
gpa2hva() API instead of dma_memory_map(). Note that we would still
call dma_memory_unmap() (to unref mr) regardless
From: Richard Henderson
Move the workaround out of linux-user/elfload.c, so that
we don't have to replicate it in many places. Place it
immediately after the include of , which draws
in the relevant symbols.
Note that ARCH_DLINFO is not defined by the kernel header,
and so there's no need to un
virtio-gpu-virgl used to set Object::free() of memory regions, but
memory regions are going to have its own implementation of the
function.
Add the virtio-gpu-virgl-hostmem-region type, which contains a
memory region and performs what Object::free() did during finalization.
Signed-off-by: Akihiko
On 2025/09/03 7:42, Vivek Kasireddy wrote:
There are cases when a blob resource's backing might get detached
and re-attached again such as when the underlying object is getting
migrated in the Guest. In these situations, we need to obtain a new
dmabuf fd, which can be done by calling virtio_gpu_i
On 9/5/25 17:17, Peter Foley wrote:
gstrfuncs.h is not intended to be included directly.
In fact this only works because glib.h is already included by osdep.h.
Just remove the include.
Signed-off-by: Peter Foley
Reviewed-by: Richard Henderson
r~
---
Changes in v2:
- Just remove the inclu
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/ppc/spapr_pci.c | 22 --
1 file changed, 22 deletions(-)
diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c
index
1ac1185825e84ca908fd878f6cbe7e8cacac1d89..b4043ee752c5f9ab2c0f5800dffa809d3c182225
100644
---
On 2025/09/03 7:42, Vivek Kasireddy wrote:
In addition to memfd, a blob resource can also have its backing
storage in a VFIO device region. Therefore, we first need to figure
out if the blob is backed by a VFIO device region or a memfd before
we can call the right API to get a dmabuf fd created.
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/nvme/ctrl.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c
index
f5ee6bf260f159249204571a366472f3e0d16dea..eebce1f787f464978f535356533294c5a0c7bea8
100644
--- a/hw/nvme/ctrl.c
+++ b/hw/nvme/ctr
On 2025/09/03 8:47, Arun Menon wrote:
Hi Akihiko,
It took some time to set up the machines; apologies for the delay in response.
On Mon, Sep 01, 2025 at 02:12:54AM +0900, Akihiko Odaki wrote:
On 2025/09/01 1:38, Arun Menon wrote:
Hi,
On Mon, Sep 01, 2025 at 01:04:40AM +0900, Akihiko Odaki wr
MemoryRegions used to "piggyback" on their owners instead of using their
own reference counters due to the circular dependencies between
them, which caused new circular references. Stop piggybacking, showing
that the circular dependencies are actually broken at the finalization
time.
Circular refe
mips-cpu is not hotpluggable but its instance can still be created and
finalized when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realization tim
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/char/diva-gsp.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/hw/char/diva-gsp.c b/hw/char/diva-gsp.c
index
e1f0713cb794d0442c56935dfe56d784d96949f0..1ae472e879b53555d4751b6a4848354f81c27fee
100644
--- a/hw/char/diva-gsp.c
+++
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/pci/pci.c | 20
1 file changed, 20 deletions(-)
diff --git a/hw/pci/pci.c b/hw/pci/pci.c
index
516029f66cda6705bded15322cb6f7eb3d42f82c..2b408c7ec336df08086f1be9a5bd2555e2e906b7
100644
--- a/hw/pci/pci.c
+++ b
Supersedes: <20250828-san-v9-0-c0dff4b8a...@rsg.ci.i.u-tokyo.ac.jp>
("[PATCH v9 0/2] Fix check-qtest-ppc64 sanitizer errors")
Based-on: <20250906-use-v1-0-c51caafd1...@rsg.ci.i.u-tokyo.ac.jp>
("[PATCH 00/22] Fix memory region leaks and use-after-finalization")
MemoryRegions used to "piggyback" on
The next change adds code to retain references from an object to the
parent when it is being unparented to ensure that the parent outlive
them. This change handles the following scenario with the code:
1. The parent starts being finalized without unparenting.
2. Unparenting happens during finaliza
sun4m-iommu is not hotpluggable but its instance can still be created
and finalized when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realization
A common pattern is that to delete memory subregions during realization
error handling and unrealization. pci automatically automatically
deletes the IO subregions, but the pattern is manually implemented
in other places, which is tedious and error-prone.
Implement the logic to delete subregions i
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/usb/hcd-ehci.c | 4
1 file changed, 4 deletions(-)
diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c
index
b090f253656ba17c7c6b3b805235a9360334baf5..21c3501455b5705b5e155acf9df2156b653f69bf
100644
--- a/hw/usb/hcd-ehci.c
+++
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/ide/cmd646.c | 12
1 file changed, 12 deletions(-)
diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c
index
2a59516a9ddbc0a7d40400f521b9cef07006b76a..ea4d501c5e40b0f7f5fcd5c025c113d97d89f5b7
100644
--- a/hw/ide/cmd646.c
+
Children are automatically unparented so manually unparenting is
unnecessary.
Worse, automatic unparenting happens before the insntance_finalize()
callback of the parent gets called, so object_unparent() calls in
the callback will refer to objects that are already unparented, which
is semantically
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/display/vga-pci.c | 8
1 file changed, 8 deletions(-)
diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c
index
b81f7fd2d0fd11913e6b132897028ca490e74b95..90b4545d382135b109e3bbc880bb8fe1a4fc5275
100644
--- a/hw/displ
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/ide/via.c | 12
1 file changed, 12 deletions(-)
diff --git a/hw/ide/via.c b/hw/ide/via.c
index
dedc2674c002f9de8894e6c49cdb3989cb0deccc..cbaf4ad1548b94afa14809930729eba169f1b061
100644
--- a/hw/ide/via.c
+++ b/hw/ide/
It is no longer necessary.
Signed-off-by: Akihiko Odaki
---
hw/vfio-user/pci.c | 6 --
1 file changed, 6 deletions(-)
diff --git a/hw/vfio-user/pci.c b/hw/vfio-user/pci.c
index
be71c777291f0c68b01b54029612c4dbc6aa86e2..0b6c6a1c5ed327ec53b119a799976a0823e304c3
100644
--- a/hw/vfio-user/pci
aux-bus is not hotpluggable but its instance can still be created and
finalized when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realization time
sun4u-iommu is not hotpluggable but its instance can still be created
and destroyed when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realization
raven-pcihost is not hotpluggable but its instance can still be created
and finalized when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realizatio
When updating memory mappings, pci_bridge_update_mappings() performed
the following operations:
1. Start a transaction
2. Delete the subregions from the container
3. Unparent the subregions
4. Initialize the subregions
5. End the transaction
This assumes the old subregion instances are finalized i
xtensa-cpu is not hotpluggable but its instance can still be created and
finalized when processing the device-list-properties QMP command.
Exposing such a temporary instance to AddressSpace should be
avoided because it leaks the instance.
Expose instances to the AddressSpace at their realization t
Some analysis greatly benefits, or depends on, information about
certain types of dicontinuities such as interrupts. For example, we may
need to handle the execution of a new translation block differently if
it is not the result of normal program flow but of an interrupt.
Even with the existing in
在 2025/9/5 下午4:40, Bibo Mao 写道:
On 2025/9/4 下午8:18, Song Gao wrote:
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/lo
gstrfuncs.h is not intended to be included directly.
In fact this only works because glib.h is already included by osdep.h.
Just remove the include.
Signed-off-by: Peter Foley
---
Changes in v2:
- Just remove the include entirely in favor of osdep.h
- Link to v1:
https://lore.kernel.org/qemu-dev
QEMU_HEXDUMP_LINE_WIDTH calculation doesn't correspond to
qemu_hexdump_line(). This leads to last line of the dump (when
length is not multiply of 16) has badly aligned ASCII part.
Let's calculate length the same way.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
util/hexdump.c | 38 +
Store HEST table address at GPA, placing its the start of the table at
hest_addr_le variable.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes.c | 22 --
include/hw/acpi/ghes.h | 6 +-
2 files change
The current code is actually dependent on having just one error
structure with a single source, as any change there would cause
migration issues.
As the number of sources should be arch-dependent, as it will depend on
what kind of notifications will exist, and how many errors can be
reported at th
September 5, 2025 at 9:25 PM, "BALATON Zoltan" wrote:
> On Fri, 5 Sep 2025, Julian Ganz wrote:
> > September 5, 2025 at 1:38 PM, "BALATON Zoltan" wrote:
> > > Have you done any testing on how much overhead this adds
> > > to interrupt heavy guest workloads? At least for PPC these are already
> > >
Now that we have everything in place, enable using HEST GPA
instead of etc/hardware_errors GPA.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/h
Adds support to ARM virtualization to allow handling
generic error ACPI Event via GED & error source device.
It is aligned with Linux Kernel patch:
https://lore.kernel.org/lkml/1272350481-27951-8-git-send-email-ying.hu...@intel.com/
Co-authored-by: Mauro Carvalho Chehab
Co-authored-by: Jonathan
On Fri, 5 Sep 2025, Julian Ganz wrote:
September 5, 2025 at 1:38 PM, "BALATON Zoltan" wrote:
On Thu, 4 Sep 2025, Julian Ganz wrote:
Even with the existing interfaces, it is more or less possible to
discern these situations, e.g. as done by the cflow plugin. However,
this process poses a cons
On 7/16/25 10:36 AM, Shameerali Kolothum Thodi wrote:
>
>> -Original Message-
>> From: Nicolin Chen
>> Sent: Wednesday, July 16, 2025 12:13 AM
>> To: Shameerali Kolothum Thodi
>> Cc: qemu-...@nongnu.org; qemu-devel@nongnu.org;
>> eric.au...@redhat.com; peter.mayd...@linaro.org; j...@nv
On 2025/9/4 下午8:18, Song Gao wrote:
Add feature register and misc register for avecintc feature checking and
setting
Signed-off-by: Song Gao
---
hw/loongarch/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index 1a2aa92c25.
Add Vladimir and Dan.
On Thu, Aug 14, 2025 at 10:17:14AM -0700, Steve Sistare wrote:
> This patch series adds the live migration cpr-exec mode.
>
> The new user-visible interfaces are:
> * cpr-exec (MigMode migration parameter)
> * cpr-exec-command (migration parameter)
>
> cpr-exec mode i
Hi Mark,
I noticed a few other places where we probably want to
allow unused bits to be set and ignored for pre-v9.
Changes for v2:
- Use TRANS() in the STBAR and RDY patches.
- Apply the same relaxation for RDPSR, RDWIM, RDTBR.
- Do not report illegal_instruction when unused bits
are s
On Fri, Sep 05, 2025 at 11:57:59AM +0200, Eric Auger wrote:
> Hi Shameer,
>
> On 7/14/25 5:59 PM, Shameer Kolothum wrote:
> > From: Nicolin Chen
> >
> > Allocate and associate a vDEVICE object for the Guest device
> > with the vIOMMU. This will help the kernel to do the
> > vSID --> sid translati
Move the check logic into a common function and simplify the
code which checks if GHES is enabled and was properly setup.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/ghes-stub.c| 7 ---
hw/acpi/ghes.c | 38 +
On Fri, Sep 05, 2025 at 05:09:05PM +, Dr. David Alan Gilbert wrote:
> k8s used to find it very hard to change the amount of memory allocated to a
> container after launch (although I heard that's getting fixed); so you'd
> need more excess at the start even if your peek during hand over is only
On Fri, Sep 5, 2025 at 12:26 PM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/5/25 18:00, Peter Foley wrote:
> > We're using glibc 2.27.
>
> That's just too old.
>
Yeah, I'm picking up on that.
So it looks like short of back-porting support for MAP_FIXED_NOREPLACE to
our "grte"
On 9/5/25 18:00, Peter Foley wrote:
We're using glibc 2.27.
That's just too old.
commit c42e77a90d9244c8caf76fe0e54f84200430a4e1
Author: Richard Henderson
Date: Tue Aug 8 09:44:18 2023 -0700
qemu/osdep: Remove fallback for MAP_FIXED_NOREPLACE
In order for our emulation of MAP_FIXE
Handle local-incoming option:
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
include/net/tap.h | 4 ++
net/tap.c | 139 +++---
2 files changed, 122 insertions(+), 21 deletions(-)
diff --git a/include/net/tap.h b/include/net/tap.h
index 6f34f13e
1. Move function higher. (we anyway want to split it into two functions,
and change the code a lot, so take an opportunity to get rid of extra
declaration).
2. Split into _set_options() and _init_vhost(): we'll need it later
to implement TAP local migration feature.
3. Split requires to store opt
On 03.09.25 17:11, Daniel P. Berrangé wrote:
It occurrs to me that this ability to dump a buffer is likely useful for
other areas of QEMU. How about moving this to somewhere in util/ and
renaming it to something like "dump_buffer".
Ha, I started to do it, and found that we already have util/hex
On Tue, Sep 02, 2025 at 08:09:44PM +0300, Vladimir Sementsov-Ogievskiy wrote:
> On 02.09.25 18:33, Steven Sistare wrote:
> > On 9/1/2025 7:44 AM, Vladimir Sementsov-Ogievskiy wrote:
> > > On 29.08.25 22:37, Steven Sistare wrote:
> > > > On 8/28/2025 11:48 AM, Steven Sistare wrote:
> > > > > On 8/23
On Thu, 4 Sep 2025 18:49:02 +0530
Arpit Kumar wrote:
> This patch series refactor existing support for Identify Switch Device
> and Get Physical Port State by utilizing physical ports (USP & DSP)
> information stored during enumeration.
>
> Additionally, it introduces new support for Physical
On 04.09.25 10:41, Vladimir Sementsov-Ogievskiy wrote:
On 03.09.25 19:09, Steven Sistare wrote:
On 9/3/2025 11:31 AM, Vladimir Sementsov-Ogievskiy wrote:
On 03.09.25 17:34, Daniel P. Berrangé wrote:
On Wed, Sep 03, 2025 at 04:37:02PM +0300, Vladimir Sementsov-Ogievskiy wrote:
Handle local-inc
On 2025/9/4 下午8:18, Song Gao wrote:
Implement avec set irq and update CSR_MSIS.
Signed-off-by: Song Gao
---
hw/intc/loongarch_avec.c | 58 ++--
include/hw/intc/loongarch_avec.h | 3 ++
2 files changed, 59 insertions(+), 2 deletions(-)
diff --git a/hw
September 5, 2025 at 1:38 PM, "BALATON Zoltan" wrote:
> On Thu, 4 Sep 2025, Julian Ganz wrote:
> > Even with the existing interfaces, it is more or less possible to
> > discern these situations, e.g. as done by the cflow plugin. However,
> > this process poses a considerable overhead to the core
On Fri, Sep 5, 2025 at 4:48 AM Richard Henderson <
richard.hender...@linaro.org> wrote:
> On 9/5/25 09:31, Paolo Bonzini wrote:
> > On 9/4/25 17:21, Peter Foley wrote:
> >> We're getting errors about this:
> >> linux-user/elfload.c:2770:36: error: use of undeclared identifier
> 'MAP_FIXED_NOREPLAC
On 7/14/25 5:59 PM, Shameer Kolothum wrote:
> On ARM, when a device is behind an IOMMU, its MSI doorbell address is
> subject to translation by the IOMMU. This behavior affects vfio-pci
> passthrough devices assigned to guests using an accelerated SMMUv3.
>
> In this setup, we configure the host
On Fri, Sep 5, 2025 at 12:00 PM Peter Foley wrote:
>
>
> On Fri, Sep 5, 2025 at 4:48 AM Richard Henderson <
> richard.hender...@linaro.org> wrote:
>
>> On 9/5/25 09:31, Paolo Bonzini wrote:
>> > On 9/4/25 17:21, Peter Foley wrote:
>> >> We're getting errors about this:
>> >> linux-user/elfload.c:
On Thu, 4 Sep 2025 18:49:03 +0530
Arpit Kumar wrote:
> -Storing physical ports info during enumeration.
> -Refactored changes using physical ports info for
> Identify Switch Device (Opcode 5100h) & Get Physical Port State
> (Opcode 5101h) physical switch FM-API command set.
>
> Signed-off-by:
Use ## to drop the preceding comma if __VA_ARGS__ is empty.
Signed-off-by: Richard Henderson
---
target/sparc/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index b922e53bf1..336583beab 100644
--- a/target/sparc
The GHES migration logic should now support HEST table location too.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
hw/acpi/generic_event_device.c | 29 +
1 file changed, 29 insertions(+)
diff --git a/hw/acpi/gener
While the HEST layout didn't change, there are some internal
changes related to how offsets are calculated and how memory error
events are triggered.
Update specs to reflect such changes.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Reviewed-by: Igor Mammedov
---
docs/sp
--- /tmp/DSDT_old.dsl 2025-09-05 15:03:18.964968499 +0200
+++ /tmp/DSDT.dsl 2025-09-05 15:03:18.966968470 +0200
@@ -5,13 +5,13 @@
*
* Disassembling to symbolic ASL+ operators
*
- * Disassembly of /tmp/DSDT_old
+ * Disassembly of /tmp/DSDT
*
* Original Table Header:
* Signatu
On Tue, Sep 02, 2025 at 11:06:13AM +0100, Peter Maydell wrote:
> On Tue, 26 Aug 2025 at 23:20, Peter Xu wrote:
> >
> > Currently, QEMU refcounts the MR by always taking it from the owner.
> >
> > It's common that one object will have multiple MR objects embeded in the
> > object itself. All the M
Some error injection notify methods are async, like GPIO
notify. Add a notifier to be used when the error record is
ready to be sent to the guest OS.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Cameron
Acked-by: Igor Mammedov
---
hw/acpi/ghes.c | 5 -
include/hw/acpi
We'll be adding a new GED device for HEST GPIO notification and
increasing the number of entries at the HEST table.
Blocklist testing HEST and DSDT tables until such changes
are completed.
Signed-off-by: Mauro Carvalho Chehab
Acked-by: Igor Mammedov
Reviewed-by: Jonathan Cameron
---
tests/qte
Using the QMP GHESv2 API requires preparing a raw data array
containing a CPER record.
Add a helper script with subcommands to prepare such data.
Currently, only ARM Processor error CPER record is supported, by
using:
$ ghes_inject.py arm
which produces those warnings on Linux:
[ 705.0
There are two pointers that are needed during error injection:
1. The start address of the CPER block to be stored;
2. The address of the read ack.
It is preferable to calculate them from the HEST table. This allows
checking the source ID, the size of the table and the type of the
HEST error blo
Adds a generic error device to handle generic hardware error
events as specified at ACPI 6.5 specification at 18.3.2.7.2:
https://uefi.org/specs/ACPI/6.5/18_Platform_Error_Interfaces.html#event-notification-for-generic-error-sources
using HID PNP0C33.
The PNP0C33 device is used to report hardware
Create a new property (x-has-hest-addr) and use it to detect if
the GHES table offsets can be calculated from the HEST address
(qemu 10.0 and upper) or via the legacy way via an offset obtained
from the hardware_errors firmware file.
Signed-off-by: Mauro Carvalho Chehab
Reviewed-by: Jonathan Came
On Fri, Sep 5, 2025 at 3:25 AM Paolo Bonzini wrote:
> On 9/4/25 17:11, Peter Foley wrote:
> > Relying on `python3` to be avilable in $PATH doesn't work in some build
> > environments. Update the build files to use the found python binary
> > explicitly.
>
> Meson already does this, if the file is
On Wed, Sep 03, 2025 at 10:47:17AM +0100, Peter Maydell wrote:
> On Wed, 3 Sept 2025 at 06:03, chen CJ wrote:
> >
> > I would like to withdraw this patch series.
> >
> > Sorry for the inconvenience, and thank you for your understanding.
>
> That's unfortunate; I think it's an issue we really do n
On Mon, Sep 01, 2025 at 05:57:57PM +0100, Peter Maydell wrote:
> On Fri, 22 Aug 2025 at 10:26, CJ Chen wrote:
> >
> > From: Tomoyuki Hirose
> >
> > This commit adds a qtest for accessing various memory regions. The
> > qtest checks the correctness of handling the access to memory regions
> > by u
On Thu Jan 30, 2025 at 2:43 PM CET, Cédric Le Goater wrote:
> Print a warning if IOMMU address space width is smaller than the
> physical address width. In this case, PCI peer-to-peer transactions on
> BARs are not supported and failures of device MMIO regions are to be
> expected.
>
> This can occ
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
hw/net/virtio-net.c| 100 -
include/hw/virtio/virtio-net.h | 2 +
2 files changed, 101 insertions(+), 1 deletion(-)
diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c
index 6b5b5dace3..874e349fee 10
Allow to specify non default vm for the command.
Signed-off-by: Vladimir Sementsov-Ogievskiy
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Thomas Huth
---
tests/functional/qemu_test/cmd.py | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/tests/functional/qemu_test/
To be used in the next commit: that would be a test for TAP
networking, and it will need to setup TAP device.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
tests/functional/qemu_test/decorators.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/functional/qemu_test/
Add test for a new feature of local TAP migration with fd passing
through unix socket.
Signed-off-by: Vladimir Sementsov-Ogievskiy
---
.../test_x86_64_tap_fd_migration.py | 345 ++
1 file changed, 345 insertions(+)
create mode 100644 tests/functional/test_x86_64_tap_fd
Hi all!
Here is a new migration capability "local-tap", which
allows local migration of TAP device, including its properties
and open fds.
With this new option, management software doesn't need to
initialize new TAP and do a switch to it. Nothing should be
done around virtio-net in local migrati
On 7/14/25 5:59 PM, Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Not all fields in the SMMU IDR registers are meaningful for userspace.
> Only the following fields can be used:
>
> - IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L, ASID16, TTF
> - IDR1: SIDSIZE, SSIDSIZE
>
Solaris 8 appears to have a bug whereby it executes v9 MEMBAR
instructions when booting a freshly installed image. According
to the SPARC v8 architecture manual, whilst bits 13 and bits 12-0
of the "Read State Register Instructions" are notionally zero,
they are marked as unused (i.e. ignored).
Fi
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