On 6/22/22 19:28, Jae Hyun Yoo wrote:
Hello,
I'm sending a series to add Qualcomm BMC machines that are equipped with
Aspeed AST2600 SoC. Also, this series adds MAX31785 fan controller device
emulation. Please help to review.
Thanks,
Jae
Graeme Gregory (2):
hw/arm/aspeed: qcom-dc-scm-v1: a
On 10/25/20 14:14, John Wang wrote:
G220A is a 2 socket x86 motherboard supported by OpenBMC.
Strapping configuration was obtained from hardware.
Signed-off-by: John Wang
Reviewed-by: Cédric Le Goater
Reviewed-by: Joel Stanley
Hello John
Would it be possible to contribute a functional test
Hello Patrick,
On 4/16/21 18:24, Patrick Venture wrote:
The Quanta-Q71l BMC board is a board supported by OpenBMC.
Tested: Booted quanta-q71l firmware.
Signed-off-by: Patrick Venture
Reviewed-by: Hao Wu
---
hw/arm/aspeed.c | 62 +
1 file chan
On 10/25/22 18:51, Guenter Roeck wrote:
supermicrox11-bmc is configured with ast2400-a1 SoC. This does not match
the Supermicro documentation for X11 BMCs, and it does not match the
devicetree file in the Linux kernel.
As it turns out, some Supermicro X11 motherboards use AST2400 SoCs,
while oth
Hello Patrick
On 5/6/20 20:32, Patrick Williams wrote:
Sonora Pass is a 2 socket x86 motherboard designed by Facebook
and supported by OpenBMC. Strapping configuration was obtained
from hardware and i2c configuration is based on dts found at:
https://github.com/facebook/openbmc-linux/blob/1633
This is an incremental step in converting vmstate loading
code to report error via Error objects instead of directly
printing it to console/monitor.
It is ensured that qemu_loadvm_state() must report an error
in errp, in case of failure.
When postcopy live migration runs, the device states are loa
On 30/09/2025 06.13, Philippe Mathieu-Daudé wrote:
flatview_translate()'s @plen argument is output-only and can be NULL.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/memory.h | 5 +++--
system/physmem.c| 6 +++---
2 files changed, 6 insertions(+), 5 deletions(-)
diff --
PCIe Flit Mode, introduced with the PCIe 6.0 specification, is a
fundamental change in how data is transmitted over the bus to
improve transfer rates. It shifts from variable-sized Transaction
Layer Packets (TLPs) to fixed 256-byte Flow Control Units (FLITs).
As with the link speed and width train
This is an incremental step in converting vmstate loading
code to report error via Error objects instead of directly
printing it to console/monitor.
It is ensured that vmstate_load() must report an error
in errp, in case of failure.
The errors are temporarily reported using error_report_err().
Thi
Signed-off-by: Philippe Mathieu-Daudé
---
target/i386/nvmm/nvmm-all.c | 5 -
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/target/i386/nvmm/nvmm-all.c b/target/i386/nvmm/nvmm-all.c
index ed424251673..2e442baf4b7 100644
--- a/target/i386/nvmm/nvmm-all.c
+++ b/target/i386/nvmm/nv
Function fill_tlb_entry() can be used with hardware PTW in future,
here add input parameter MMUContext in fill_tlb_entry().
Signed-off-by: Bibo Mao
---
target/loongarch/tcg/tlb_helper.c | 21 -
1 file changed, 12 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/tc
Hardware page table walk (PTW for short) is one feature supported in
Loongson 3C6000 system. With hardware PTW supported, if there is an TLB
miss, hardware will take PTW and fill it in TLB if matched, report TLB
exception if not matched.
With hardware PTW supported, bit Present and Write in pte en
However with hardware PTW supported, hardware will search page table
with TLB miss. Also if there is no TLB miss however bit Present is not set,
hardware PTW will happen also. Because there is odd/even page in one TLB
entry on LoongArch system, for example in the first time odd TLB entry is
valid a
PTW is short for page table walker, it is hardware page table walker
function. With PTW supported, hardware MMU will parse page table
table and update TLB entries automatically.
This patch adds type OnOffAuto for PTW feature setting.
Signed-off-by: Bibo Mao
---
target/loongarch/cpu.c | 25 +
Add basic plumbing for memory expander devices that support Back
Invalidation. This introduces a 'hdm-db=on|off' parameter and
exposes the relevant BI RT/Decoder component cachemem registers.
Some noteworthy properties:
- Devices require enabling Flit mode.
- Explicit BI-ID commit is required.
Loop in more Nuvoton folks.
-Original Message-
From: Yubin Zou
Sent: Wednesday, September 10, 2025 6:11 AM
To: qemu-devel@nongnu.org
Cc: Paolo Bonzini ; CS20 KFTing ; Hao
Wu ; qemu-...@nongnu.org; Peter Maydell
; Yubin Zou ; Titus Rwantare
Subject: [PATCH 5/7] hw/pci-host: enable MSI
On Mon, Sep 29, 2025 at 02:36:22PM +0100, Shameer Kolothum wrote:
> Accelerated SMMUv3 is only useful when the device can take advantage of
> the host's SMMUv3 in nested mode. To keep things simple and correct, we
> only allow this feature for vfio-pci endpoint devices that use the iommufd
> backen
On 9/25/25 5:11 PM, Richard Henderson wrote:
These bits disable all access to a particular address space.
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 23 +--
1 file changed, 21 insertions(+), 2 deletions(-)
Reviewed-by: Pierrick Bouvier
On 9/25/25 5:11 PM, Richard Henderson wrote:
Signed-off-by: Richard Henderson
---
target/arm/ptw.c | 10 +-
1 file changed, 9 insertions(+), 1 deletion(-)
Reviewed-by: Pierrick Bouvier
On Mon, Sep 29, 2025 at 02:36:20PM +0100, Shameer Kolothum wrote:
> And set to the current default smmu_ops. No functional change intended.
> This will allow SMMUv3 accel implementation to set a different iommu ops
> later.
>
> Signed-off-by: Shameer Kolothum
Reviewed-by: Nicolin Chen
On 9/28/25 22:26, Harsh Prateek Bora wrote:
From: Fabian Vogt
An obsolete wrapper function with a workaround was removed entirely,
without restoring the call it wrapped.
Without this, the guest is stuck after savevm/loadvm.
Fixes: 24ee9229fe31 ("ppc/spapr: remove deprecated machine pseries-2.
On Mon, Sep 29, 2025 at 02:43:48PM +0100, Alex Bennée wrote:
> This is very much the result of my recent fat finger but I think it's
> safer to assume that origin/master points to a recent commit (or at
> least a commit a given branch is based on) than master.
>
> Signed-off-by: Alex Bennée
> ---
This is an idea suggested by Peter Maydell:
https://lore.kernel.org/all/CAFEAcA--K0=EJNNvj98i=ewGY=tn3u4s0+fnb9kjpyynzjh...@mail.gmail.com/
After this small series applied, we should be able to assert on misuse of
accidental (wrong) re-use on a rcu head.
Please review, thanks.
Peter Xu (3):
q
On Thu, Sep 18, 2025 at 08:53:42PM +0530, Arun Menon wrote:
> The post_save() function call is responsible for cleaning up resources
> after the device state has been saved.
> Currently it is infallible, and does not return an error.
>
> It is called regardless of whether there is a preceding erro
On Wed, Sep 10, 2025 at 01:54:16PM +0200, Albert Esteve wrote:
> Add SHMEM_MAP/_UNMAP request to the vhost-user
> spec documentation.
>
> Reviewed-by: Stefan Hajnoczi
> Signed-off-by: Albert Esteve
> ---
> docs/interop/vhost-user.rst | 58 +
> 1 file changed,
When cpu_address_space_init() isn't called during vCPU creation,
its single address space is the global &address_space_memory.
As s390x boards don't call cpu_address_space_init(),
cpu_get_address_space(CPU(cpu), 0) returns &address_space_memory.
We can then replace cpu_physical_memory_is_io() by
On 18/09/2025 01.21, Zhuoying Cai wrote:
Add documentation for secure IPL
Signed-off-by: Collin Walling
Signed-off-by: Zhuoying Cai
---
docs/system/s390x/secure-ipl.rst | 96
1 file changed, 96 insertions(+)
diff --git a/docs/system/s390x/secure-ipl.rst b/d
On 18/09/2025 01.21, Zhuoying Cai wrote:
The current approach to enable secure boot relies on providing
secure-boot and boot-certs parameters of s390-ccw-virtio machine
type option, which apply to all boot devices.
With the possibility of multiple boot devices, secure boot expects all
provided d
From: Jamin Lin
Add MSI support to the ASPEED PCIe RC/Config model and introduce a per-RC
"IOMMU root" address space to correctly route MSI writes.
On AST2700 all RCs use the same MSI address, and the MSI target is PCI
system memory (not normal DRAM). If the MSI window were mapped into real
syst
From: Jamin Lin
AST2700 does not implement a PCIe Root Device; each RC exposes a single
PCIe Root Port at devfn 0:0.0.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/qemu-devel/20250919093017.338309-12-jamin_...@aspeedtech.com
Signed-off-by: Cédric Le Goa
From: Jamin Lin
Introduce PCIe config and host bridge model for the AST2600 platform.
This patch adds support for the H2X (AHB to PCIe Bus Bridge) controller
with a 0x100 byte register space. The register layout is shared between
two root complexes: 0x00–0x7f is common, 0x80–0xbf for RC_L, and 0
Philippe Mathieu-Daudé writes:
> Move ramblock_is_pmem() along with the RAM Block API
> exposed by the "system/ramblock.h" header. Rename as
> ram_block_is_pmem() to keep API prefix consistency.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/system/ram_addr.h | 2 --
> include/system
From: Jamin Lin
This patch introduces an initial ASPEED PCIe PHY/host controller model to
support the AST2600 SoC. It provides a simple register block with MMIO
read/write callbacks, integration into the build system, and trace events
for debugging.
Key changes:
1. PCIe PHY MMIO read/write call
From: Jamin Lin
Refactor ast2700fc_ca35_init(), ast2700fc_ssp_init(), and ast2700fc_tsp_init()
to take an Error **errp parameter and return a bool.
Each function now reports failure through the error object and returns false.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le Goater
Link:
https:
From: Kane-Chen-AS
Implement correct OTP programming behavior for Aspeed OTP:
- Support read-modify-write flow with one-way bit programming:
* prog_bit uses 0s as the "to-be-programmed" mask.
* Even-indexed words: 0->1, odd-indexed words: 1->0.
* Reject non-programmable requests and log con
From: Jamin Lin
Introduce an ASPEED PCIe Root Port and wire it under the RC. The root port
is modeled as TYPE_ASPEED_PCIE_ROOT_PORT (subclass of TYPE_PCIE_ROOT_PORT).
Key changes:
- Add TYPE_ASPEED_PCIE_ROOT_PORT (PCIESlot-based) with vendor/device IDs
and AER capability offset.
- Extend Aspee
From: Jamin Lin
Introduce a PCIe Host Controller PHY model for AST2700. This adds an
AST2700 specific PHY type (TYPE_ASPEED_2700_PCIE_PHY) with a 0x800 byte
register space and link-status bits compatible with the firmware’s
expectations.
AST2700 provides three PCIe RCs; PCIe0 and PCIe1 are GEN4,
From: Jamin Lin
This patch moves the "ast2700-evb" alias from the A0 to A1.
The A0 machine remains available via its explicit name
("ast2700a0-evb"), while functional tests are updated to
target A0 by name instead of relying on the generic alias.
Signed-off-by: Jamin Lin
Reviewed-by: Cédric Le
From: Kane-Chen-AS
The has_otp attribute is enabled in the SBC subclasses for AST1030 to
control the presence of OTP support per SoC type.
Signed-off-by: Kane-Chen-AS
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.org/qemu-devel/20250812094011.2617526-7-kane_c...@aspeedtech.com
Signe
The following changes since commit 4975b64efb5aa4248cbc3760312bbe08d6e71638:
Merge tag 'pull-loongarch-20250928' of https://github.com/bibo-mao/qemu into
staging (2025-09-28 09:01:35 -0700)
are available in the Git repository at:
https://github.com/legoater/qemu/ tags/pull-aspee
From: Kane-Chen-AS
Add a small helper that generates OTP images at test time. This lets
multiple test cases create default OTP contents without shipping prebuilt
fixtures and keeps the tests self-contained.
Signed-off-by: Kane-Chen-AS
Reviewed-by: Cédric Le Goater
Link:
https://lore.kernel.or
On Mon, 29 Sep 2025 14:36:28 +0100
Shameer Kolothum wrote:
> Here we return the IOMMU address space if the device has S1 translation
> enabled by Guest. Otherwise return system address space.
>
> Signed-off-by: Shameer Kolothum
> Signed-off-by: Shameer Kolothum
Naming question inline.
> ---
>
On Mon, Sep 29, 2025 at 04:51:42PM +0100, Alex Bennée wrote:
> Some license scanners are particularly dumb and when combined with
> automatic license scanning for FLOSS accreditation on forges cause
> problems on renewal. As GPL 2.0 applies to the core code link the main
> licence text to COPYING
https://gitlab.com/harshpb/qemu.git tags/pull-ppc-for-20250928-20250929
for you to fetch changes up to 6c51df580d2a64b4e1ef7bdbffeb3615ffe25d43:
target/ppc: use MAKE_64BIT_MASK for mcrfs exception clear mask (2025-09-28
23:50:36 +0530)
--
On Mon, 29 Sep 2025 14:36:26 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Allocate and associate a vDEVICE object for the Guest device with the
> vIOMMU. This will help the host kernel to make a virtual SID --> physical
> SID mapping. Since we pass the raw invalidation commands(eg: CM
On Mon, 29 Sep 2025 14:36:24 +0100
Shameer Kolothum wrote:
> From: Nicolin Chen
>
> Implement a set_iommu_device callback:
> -If found an existing viommu reuse that.
> -Else,
> Allocate a vIOMMU with the nested parent S2 hwpt allocated by VFIO.
> Though, iommufd’s vIOMMU model support
From: Tanish Desai
The syslog backend needs the syslog function from libc and the LOG_INFO enum
value; they are re-exported as "::trace::syslog" and "::trace::LOG_INFO"
so that device crates do not all have to add the libc dependency, but
otherwise there is nothing special.
Signed-off-by: Tanish
From: Tanish Desai
Generating .rs files makes it possible to support tracing in rust.
This support comprises a new format, and common code that converts
the C expressions in trace-events to Rust. In particular, types
need to be converted, and PRI macros expanded.
As of this commit no backend ge
Add the minimal support that is needed by pl011's event and tracepoint.
Reviewed-by: Zhao Liu
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
rust/hw/core/src/qdev.rs | 33 +
1 file changed, 33 insertions(+)
diff --git a/rust/hw/core/src/qdev.rs b
From: Tanish Desai
Signed-off-by: Tanish Desai
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
scripts/tracetool/backend/ftrace.py | 8 +-
tests/tracetool/ftrace.rs | 40 +
tests/tracetool/tracetool-test.py | 2 +-
3 files changed, 4
From: Tanish Desai
Signed-off-by: Tanish Desai
Reviewed-by: Stefan Hajnoczi
Signed-off-by: Paolo Bonzini
---
scripts/tracetool/backend/log.py | 10 ++-
tests/tracetool/log.rs| 44 +++
tests/tracetool/tracetool-test.py | 2 +-
3 files changed, 54 i
Keep RAM blocks API in the same header: "system/ramblock.h".
Signed-off-by: Philippe Mathieu-Daudé
---
include/exec/cpu-common.h | 3 ---
include/system/ramblock.h | 4
accel/kvm/kvm-all.c | 1 +
hw/hyperv/hv-balloon-our_range_memslots.c
This comment was added almost 5 years ago in commit 41aa4e9fd84
("ram_addr: Split RAMBlock definition"). Clearly it got ignored:
$ git grep -l system/ramblock.h
hw/display/virtio-gpu-udmabuf.c
hw/hyperv/hv-balloon.c
hw/virtio/vhost-user.c
migration/dirtyrate.c
migration/file.c
migrat
Rename @start as @offset. Since it express an offset within a
RAMBlock, use the ram_addr_t type to make emphasis on the QEMU
intermediate address space represented.
Signed-off-by: Philippe Mathieu-Daudé
---
include/system/ramblock.h | 3 ++-
system/physmem.c | 12 ++--
2 files
On Mon, 29 Sep 2025 14:36:20 +0100
Shameer Kolothum wrote:
Space between : and Make
I'd repeat the patch title bit of the sentence in here just to make
it more readable.
> And set to the current default smmu_ops. No functional change intended.
> This will allow SMMUv3 accel implementation to set
Usual API cleanups, here focusing on RAMBlock API:
move few prototypes out of "exec/cpu-common.h" and
"system/ram_addr.h" to "system/ramblock.h".
Philippe Mathieu-Daudé (6):
system/ramblock: Remove obsolete comment
system/ramblock: Move ram_block_is_pmem() declaration
system/ramblock: Move r
On Mon, Sep 29, 2025 at 11:30:20AM -0300, Fabiano Rosas wrote:
> Peter Xu writes:
>
> > On Mon, Sep 29, 2025 at 02:19:48PM +0530, Arun Menon wrote:
> >> Hi,
> >> Gentle ping for the series.
> >> Is there something more to be done to improve this before queueing it?
> >> TIA.
> >
> > Arun, don't w
On 29/9/25 17:12, Anton Johansson wrote:
On 29/09/25, Philippe Mathieu-Daudé wrote:
Hi,
On 29/9/25 13:55, Valentin Haudiquet wrote:
From: vhaudiquet
Three instructions were not using the endianness swap flag, which resulted in a
bug on big-endian architectures.
I suppose you mean "big-en
On 9/29/25 11:35, Kevin Wolf wrote:
It's mentioned earlier, since the responsibility is not limited to
exceptions: "To satisfy the DCO, the patch contributor has to fully
understand the copyright and license status of content they are contributing
to QEMU". I find this sentence to be already a b
Cc'ing Salil for previous discussions on
https://lore.kernel.org/qemu-devel/20230918160257.30127-1-phi...@linaro.org/
On 29/9/25 16:42, Peter Maydell wrote:
When a vCPU is created, it typically calls cpu_address_space_init()
one or more times to set up its address spaces. We don't currently
do a
Steve Sistare writes:
> Allow the qtest_qemu_spawn caller to pass the function to be called
> to perform the spawn. The opaque argument is needed by a new spawn
> function in a subsequent patch.
>
> Signed-off-by: Steve Sistare
Reviewed-by: Fabiano Rosas
Steve Sistare writes:
> Define an accessor that returns all the arguments used to exec QEMU.
> Collect the arguments that were passed to qtest_spawn_qemu, plus the trace
> arguments that were composed inside qtest_spawn_qemu, and move them to a
> new function qtest_qemu_args.
>
> This will be nee
Steve Sistare writes:
> Signed-off-by: Steve Sistare
> ---
> tests/qtest/libqtest.h | 9 +
> tests/qtest/libqtest.c | 2 +-
> 2 files changed, 10 insertions(+), 1 deletion(-)
>
> diff --git a/tests/qtest/libqtest.h b/tests/qtest/libqtest.h
> index b3f2e7f..6d3199f 100644
> --- a/tests/q
When we unrealize a CPU object (which happens on vCPU hot-unplug), we
should destroy all the AddressSpace objects we created via calls to
cpu_address_space_init() when the CPU was realized.
Commit 24bec42f3d6eae added a function to do this for a specific
AddressSpace, but did not add any places wh
From: Peter Xu
If an AddressSpace has been created in its own allocated
memory, cleaning it up requires first destroying the AS
and then freeing the memory. Doing this doesn't work:
address_space_destroy(as);
g_free_rcu(as, rcu);
because both address_space_destroy() and g_free_rcu()
try
address_space_destroy() doesn't actually immediately destroy the AS;
it queues it to be destroyed via RCU. This means you can't g_free()
the memory the AS struct is in until that has happened.
Clarify this in the documentation.
Signed-off-by: Peter Maydell
---
include/system/memory.h | 11 +
On 18/09/2025 01.21, Zhuoying Cai wrote:
Add secure-boot as a parameter of s390-ccw-virtio machine type option.
The `secure-boot=on|off` parameter is implemented to enable secure IPL.
By default, secure-boot is set to false if not specified in
the command line.
Signed-off-by: Zhuoying Cai
---
Introduce an “accel” property to enable accelerator mode.
Live migration is currently unsupported when accelerator mode is enabled,
so a migration blocker is added.
Because this mode relies on IORT RMR for MSI support, accelerator mode is
not supported for device tree boot.
Signed-off-by: Shamee
Here we return the IOMMU address space if the device has S1 translation
enabled by Guest. Otherwise return system address space.
Signed-off-by: Shameer Kolothum
Signed-off-by: Shameer Kolothum
---
hw/arm/smmuv3-accel.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/h
Provide a helper and use that to issue the invalidation cmd to host SMMUv3.
We only issue one cmd at a time for now.
Support for batching of commands will be added later after analysing the
impact.
Signed-off-by: Shameer Kolothum
---
hw/arm/smmuv3-accel.c | 38 ++
On ARM, when a device is behind an IOMMU, its MSI doorbell address is
subject to translation by the IOMMU. This behavior affects vfio-pci
passthrough devices assigned to guests using an accelerated SMMUv3.
In this setup, we configure the host SMMUv3 in nested mode, where
VFIO sets up the Stage-2 (
And store it in HostIOMMUDeviceCaps for later use.
Signed-off-by: Shameer Kolothum
---
backends/iommufd.c | 6 +-
hw/arm/smmuv3-accel.c | 3 ++-
hw/vfio/iommufd.c | 7 +--
include/system/host_iommu_device.h | 2 ++
include/system/iommufd.h
QEMU SMMUv3 does not enable ATS (Address Translation Services) by default.
When accelerated mode is enabled and the host SMMUv3 supports ATS, it can
be useful to report ATS capability to the guest so it can take advantage
of it if the device also supports ATS.
Note: ATS support cannot be reliably
This is very much the result of my recent fat finger but I think it's
safer to assume that origin/master points to a recent commit (or at
least a commit a given branch is based on) than master.
Signed-off-by: Alex Bennée
---
.gitpublish | 16
1 file changed, 8 insertions(+), 8 d
Just before the device gets attached to the SMMUv3, make sure QEMU SMMUv3
features are compatible with the host SMMUv3.
Not all fields in the host SMMUv3 IDR registers are meaningful for userspace.
Only the following fields can be used:
- IDR0: ST_LEVEL, TERM_MODEL, STALL_MODEL, TTENDIAN, CD2L,
And set to the current default smmu_ops. No functional change intended.
This will allow SMMUv3 accel implementation to set a different iommu ops
later.
Signed-off-by: Shameer Kolothum
---
hw/arm/smmu-common.c | 7 +--
include/hw/arm/smmu-common.h | 1 +
2 files changed, 6 insertions(
On 29/09/25, Alistair Francis wrote:
> On Thu, Sep 25, 2025 at 7:37 AM Richard Henderson
> wrote:
> >
> > On 9/24/25 00:20, Anton Johansson via wrote:
> > > +++ b/target/riscv/machine.c
> > > @@ -84,13 +84,13 @@ static const VMStateDescription vmstate_hyper = {
> > > .minimum_version_id = 4,
On 26/9/25 09:08, Luc Michel wrote:
Add the Versal Gen 2 Virtual development machine embedding a
versal2 SoC. This machine follows the same principle than the
xlnx-versal-virt machine. It creates its own DTB and feeds it to the
software payload. This way only implemented devices are exposed to th
On 26/9/25 09:07, Luc Michel wrote:
Add the target field in the IRQ descriptor. This allows to target an IRQ
to another IRQ controller than the GIC(s). Other supported targets are
the PMC PPU1 CPU interrupt controller and the EAM (Error management)
device. Those two devices are currently not impl
Hi Luc,
On 17/9/25 13:44, Luc Michel wrote:
Based-on: 20250912100059.103997-1-luc.mic...@amd.com ([PATCH v5 00/47] AMD
Versal Gen 2 support)
Note: this series is based on my Versal 2 series. It modifies the CRL
device during the register API refactoring. It can easily be rebased on
master i
On 9/25/25 6:26 PM, Tao Tang wrote:
> This patch adapts the Configuration Cache (STE/CD caches) to support
> multiple security states.
>
> The cache key, previously just the SMMUDevice, is now a composite key
> of the SMMUDevice and the security index (sec_idx). This allows for
> separate cache
On Mon, Sep 22, 2025 at 04:14:55PM +0100, Alex Bennée wrote:
> "Michael S. Tsirkin" writes:
>
> > On Mon, Sep 22, 2025 at 03:26:23PM +0200, Christian Speich wrote:
> >> On Mon, Sep 22, 2025 at 09:08:47AM -0400, Michael S. Tsirkin wrote:
> >> > On Mon, Sep 22, 2025 at 01:49:55PM +0100, Daniel P. B
Am 22.09.2025 um 17:48 hat Paolo Bonzini geschrieben:
> Using phrasing from https://openinfra.org/legal/ai-policy (with just
> "commit" replaced by "submission", because we do not submit changes
> as commits but rather emails), clarify that the contributor remains
> responsible for its copyright or
Hi Tao,
On 9/25/25 6:26 PM, Tao Tang wrote:
> According to the Arm architecture, SMMU-originated memory accesses,
> such as fetching commands or writing events for a secure stream, must
> target the Secure Physical Address (PA) space. The existing model sends
> all DMA to the global address_space_
84 matches
Mail list logo
