The disassembled differences between actual and expected PPTT based on
the following cache topology representation:
```
test_acpi_one("-M virt,smp-cache.0.cache=l1i,smp-cache.0.topology=cluster,"
"smp-cache.1.cache=l1d,smp-cache.1.topology=cluster,"
"smp-cache.2
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
Test new PPTT topolopy with cache representation.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test.c | 4
1 file changed, 4 insertions(+)
diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c
index 36e5c0adde..65219f8823 100644
--- a/tests/qtest/bios-ta
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+
This commit adds IsDefined flag to the object and this helps in avoiding
extra checks for every single layer of caches in both x86 and ARM.
Signed-off-by: Alireza Sanaee
---
hw/core/machine-smp.c | 2 ++
include/hw/boards.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/core/machine-
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/test
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On Fri, 4 Oct 2024 10:59:20 +0100
Jonathan Cameron wrote:
> On Thu, 26 Sep 2024 19:33:18 +0800
> Yicong Yang wrote:
>
> > From: Yicong Yang
> >
> > OS like Linux is using PPTT processor node's identical
> > implementation flag [1] to infer whether the whole system or a
> > certain CPU cluster
On Fri, 13 Sep 2024 11:21:28 +0100
Jonathan Cameron wrote:
> On Thu, 12 Sep 2024 14:38:26 +0100
> Alireza Sanaee wrote:
>
> > This commit adds IsDefined flag to the object and this helps in
> > avoiding extra checks for every single layer of caches in both x86
> > and ARM.
> Hi Ali,
>
> You
Signed-off-by: Alireza Sanaee
---
tests/data/acpi/aarch64/virt/PPTT | Bin 76 -> 76 bytes
tests/data/acpi/aarch64/virt/PPTT.acpihmatvirt | Bin 156 -> 156 bytes
tests/data/acpi/aarch64/virt/PPTT.topology | Bin 336 -> 336 bytes
tests/qtest/bios-tables-test-allowed-diff.h| 3
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function for cpu=max. It introduces three layers of caches and modifies
the cache description registers accordingly.
Signed-off-by: Alireza Sanaee
---
target/arm/tcg/cpu64.c | 13 +
1 file changed, 13 insertions(+
This commit adds IsDefined flag to the object and this helps in avoiding
extra checks for every single layer of caches in both x86 and ARM.
Signed-off-by: Alireza Sanaee
---
hw/core/machine-smp.c | 2 ++
include/hw/boards.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/core/machine-
Prepare to update `build_pptt` function to add cache description
functionalities, thus add binaries in this patch.
Signed-off-by: Alireza Sanaee
---
tests/qtest/bios-tables-test-allowed-diff.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/t
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
On Tue, 3 Sep 2024 15:18:41 +0200
Philippe Mathieu-Daudé wrote:
> On 3/9/24 10:35, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and might be prone to e
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On Tue, 3 Sep 2024 00:11:04 +0200
Philippe Mathieu-Daudé wrote:
> Hi Alireza,
>
> On 2/9/24 22:32, Alireza Sanaee wrote:
> > This patch allows for easier manipulation of the cache description
> > register, CCSIDR. Which is helpful for testing as well. Currently,
> > numbers get hard-coded and mi
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently,
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds a wrapper for different types of CPUs
available in tcg to decribe caches. One functi
On Mon, 2 Sep 2024 11:25:36 +0100
Peter Maydell wrote:
> On Mon, 2 Sept 2024 at 11:07, Philippe Mathieu-Daudé
> wrote:
> >
> > Hi Alireza,
> >
> > On 30/8/24 20:47, Alireza Sanaee via wrote:
> > > This patch allows for easier manipulation of the cache de
On Sat, 31 Aug 2024 19:25:47 +0800
Zhao Liu wrote:
> Hi Alireza,
>
> Great to see your Arm side implementation!
>
> On Fri, Aug 23, 2024 at 01:54:44PM +0100, Alireza Sanaee wrote:
> > Date: Fri, 23 Aug 2024 13:54:44 +0100
> > From: Alireza Sanaee
> > Subject: [RFC PATCH 0/2] Specifying cache t
This patch allows for easier manipulation of the cache description
register, CCSIDR. Which is helpful for testing as well. Currently
numbers get hard-coded and might be prone to errors.
Therefore, this patch adds wrappers for different types of CPUs
available in tcg to decribe caches. Two function
On Fri, 30 Aug 2024 17:29:59 +0100
Peter Maydell wrote:
> On Fri, 30 Aug 2024 at 17:19, Alireza Sanaee
> wrote:
> >
> > Add wrapper for different types of CPUs available in tcg to decribe
> > caches. Two functions `make_ccsidr32` and `make_ccsidr64`
> > describing descriptions. The 32 bit versio
Add wrapper for different types of CPUs available in tcg to decribe
caches. Two functions `make_ccsidr32` and `make_ccsidr64`
describing descriptions. The 32 bit version receives extra parameters
that became unknown later in 64 bit.
For CCSIDR register, 32 bit version follows specification [1].
Co
Specify which layer (core/cluster/socket) caches found at in the CPU
topology.
Example:
Here, 2 sockets (packages), and 2 clusters, 4 cores and 2 threads
created, in aggregate 2*2*4*2 logical cores. In the smp-cache object,
cores will have l1d and l1i (threads will share these caches by default.
This patch addresses cache description in the `aarch64_max_tcg_initfn`
function. It introduces three layers of caches and modifies the cache
description registers accordingly. Additionally, a new function is added
to handle cache description when CCIDX is disabled. The CCIDX remains
disabled for cp
Specifying the cache layout in virtual machines is useful for
applications and operating systems to fetch accurate information about
the cache structure and make appropriate adjustments. Enforcing correct
sharing information can lead to better optimizations. This patch enables
the specification of
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