At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien
synco is a SH4-A only instruction.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deleti
We only emulate UP SH4, however as the tas.b instruction is used in the GNU
libc, this improve linux-user emulation.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 19 +++
1 fil
In case of exception, there is no need to call tcg_gen_exit_tb as the
exception helper won't return.
Also fix a few cases where BS_BRANCH is called instead of BS_EXCP.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-
When stopping the translation because the state has changed, goto_tb
should not be used as it might link TB with different flags.
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 5 +++--
1 fil
Use cpu_loop_exit_restore when using cpu_restore_state and cpu_loop_exit
together.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/op_helper.c | 10 ++
1 file changed, 2 insertions(+), 8 deletions(-)
diff --git a/target/sh4/op_helper.c b/target/sh4/op_helper.c
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.n
dé <f4...@amsat.org>
Reviewed-by: Richard Henderson <r...@twiddle.net>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 3 +--
target/sh4/helper.c| 2 --
target/sh4/translate.c | 17 +
3 files changed, 6 insertions(+), 16 deletions(-)
Reviewed-by entries
v2:
- Add some comments in the struct DisasContext declaration, as suggested
by Philippe Mathieu-Daudé
Aurelien Jarno (15):
target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags
target/sh4: get rid of DELAY_SLOT_CLEARME
target/sh4: do not include DELAY_
;
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.h
index 9445cc779f..da8d15f1b9 100644
--- a/target/sh4/cpu.h
+++ b/target/sh4/cpu.h
@@ -382,8 +382,7 @@
On 2017-05-10 10:43, Richard Henderson wrote:
> On 05/10/2017 10:13 AM, Éric Bischoff wrote:
> > Le mercredi 10 mai 2017, 12:16:20 Aurelien Jarno a écrit :
> > > > +/* In a parallel context, stop the world and single step. */
> >
On 2017-05-09 11:07, Richard Henderson wrote:
> From: Eric Bischoff <ebisch...@nerim.net>
>
> Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
> Signed-off-by: Eric Bischoff <ebisch...@nerim.net>
> Message-Id: <20170228120134.7921-1-ebisch...@suse.com>
On 2017-05-09 14:13, Richard Henderson wrote:
> On 05/06/2017 04:14 AM, Aurelien Jarno wrote:
> > +void superh_cpu_do_unaligned_access(CPUState *cs, vaddr addr,
> > +MMUAccessType access_type,
> > +i
On 2017-05-09 14:09, Richard Henderson wrote:
> On 05/06/2017 04:14 AM, Aurelien Jarno wrote:
> > +tcg_gen_extrl_i64_i32(cpu_fregs[reg + 1], t);
> > +tcg_gen_extrh_i64_i32(cpu_fregs[reg], t);
>
> This is
>
> tcg_gen_extr_i64_i32(cpu_fregs[reg + 1], cpu_fre
-data.def | 2 ++
> target/s390x/misc_helper.c | 59
> ++
> target/s390x/translate.c | 17 ++---
> 4 files changed, 72 insertions(+), 8 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno
On 2017-05-09 07:51, Richard Henderson wrote:
> On 05/09/2017 01:14 AM, Aurelien Jarno wrote:
> > > +/* The maximum bit defined at the moment is 129. */
> > > +#define MAX_STFL_WORDS 3
> >
> > Could it be computed from S390_FEAT_MAX? in gen-features.c,
&
run_on_cpu should be used instead. Any help or comments are
welcome.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/cpu.h | 2 ++
target/s390x/misc_helper.c | 64 ++
2 files changed, 61 insertions(+), 5 deletions(-)
diff
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/translate.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/s390x/translate.c b/target/s390x/translate.c
index c58c27f8e9..2f07ce2be9 100644
--- a/target/s390x/translate.c
+++ b/target
The SIGNAL PROCESSOR helper returns its value through the CC register.
set_cc_static should be called just after the helper.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/translate.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/s390x/translate.c b/
Those are just random patches I have written while trying to get a MTTCG
version of qemu/s390x. I just send them to avoid duplicated work.
Aurelien Jarno (3):
target/s390x: mask the SIGP order_code using SIGP_ORDER_MASK
target/s390x: fix SIGNAL PROCESSOR return value
target/s390x: implement
For that move the definition from kvm.c to cpu.h
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/cpu.h | 3 +++
target/s390x/kvm.c | 2 --
target/s390x/misc_helper.c | 3 +--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/s390x/c
the only allowed CPU for TCG is z900,
which makes this code almost useless. And while QEMU implements many
features from newer CPU, some of them are missing and we don't want
them to appear in the feature list.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ertions(+), 38 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ess temps.]
> Signed-off-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/insn-data.def | 4 +++-
> target/s390x/translate.c | 42 ++
> 2 files changed, 45 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno <aurel...@a
-
> 3 files changed, 55 insertions(+), 68 deletions(-)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
-by: Richard Henderson <r...@twiddle.net>
> ---
> target/s390x/insn-data.def | 2 ++
> target/s390x/translate.c | 9 +++++
> 2 files changed, 11 insertions(+)
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
access_type,
> + int mmu_idx, uintptr_t retaddr)
> +{
> +S390CPU *cpu = S390_CPU(cs);
> +CPUS390XState *env = >env;
> +
> +if (retaddr) {
> + cpu_restore_state(cs, retaddr);
> +}
> +program_interrupt(en
065ce808..16412dc150 100644
> --- a/include/hw/mips/mips.h
> +++ b/include/hw/mips/mips.h
> @@ -6,6 +6,7 @@
> #define INITRD_PAGE_MASK (~((1 << 16) - 1))
>
> #include "exec/memory.h"
> +#include "hw/irq.h"
>
> /* gt64xxx.c */
> PCIBus *gt64120_regi
On 2017-05-08 18:36, G 3 wrote:
>
> On May 8, 2017, at 6:13 PM, Aurelien Jarno wrote:
>
> > On 2017-05-07 17:48, G 3 wrote:
> > > I made a diagnostic program for the floating point unit. It will test
> > > various PowerPC floating point instructions for compatibi
On 2017-05-08 18:09, G 3 wrote:
>
> On May 8, 2017, at 5:54 PM, Aurelien Jarno wrote:
>
> > On 2017-05-07 17:48, G 3 wrote:
> > > I made a diagnostic program for the floating point unit. It will test
> > > various PowerPC floating point instructions for compatibi
nt’, but argument 2 has type ‘uint32_t’ [-Wformat=]
| printf(" actual answer: 0x%" PRIx64 "\n", actual_fpscr);
| ^
So I think the cone needs to be improved a bit before we can conclude
anything.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
; bit 6: XX - Floating-point inexact exception
> bit 0: FX - Floating-point exception summary
>
> fdiv test failed
> expected answer: 0x40059f38ee13b48b
> actual answer: 0x82004024
> expected fpscr: 0x82064000
> actual fpscr: 0x82004000
Ditto.
And so on...
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2017-05-08 17:58, Thomas Huth wrote:
> On 08.05.2017 17:36, Aurelien Jarno wrote:
> > Hi,
> >
> > On 2017-05-08 15:58, Alex Bennée wrote:
> >> Hi,
> >>
> >> We've got a task coming up to implement half-precision floating point
> >> (FP
NaN/sNaN, IEEE754-2008 functions, squash input denormal, many floatx80
fixes, ...
Do we know if all those changes are also in the new softfloat version,
and if it is not the case if we can work with upstream to implement
that? That seems to me like a pre-requisite before trying to get this
new ve
Export the rotational qdev property to the block device characteristics
VPD page.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
hw/scsi/scsi-disk.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c
index a53f
Export the rotational qdev property in the IDENTIFY request.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
hw/ide/core.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/ide/core.c b/hw/ide/core.c
index 0b48b64d3a..1aa76b0d90 100644
--- a/hw/ide/core.c
+++ b/hw/ide/
-rotational device. Default
to true to not change the default behavior.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
blockdev.c | 4
include/hw/block/block.h | 4 +++-
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/blockdev.c b/blockdev.c
index 4d8c
(TCGContext *s)
> /* br %r3 (go to TB) */
> tcg_out_insn(s, RR, BCR, S390_CC_ALWAYS, tcg_target_call_iarg_regs[1]);
>
> +/*
> + * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
> + * and fall through to the rest of the epilogue.
> + */
> +
_tb()) {
> tcg_gen_exit_tb(0);
> +} else {
> + tcg_gen_lookup_and_goto_ptr(psw_addr);
> }
> break;
> default:
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
Tested-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
gs[0]);
> tcg_out_insn(s, 3207, BR, tcg_target_call_iarg_regs[1]);
>
> +/*
> + * Return path for goto_ptr. Set return value to 0, a-la exit_tb,
> + * and fall through to the rest of the epilogue.
> + */
> +s->code_gen_epilogue = s->code_ptr;
> +tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_X0, 0);
> +
> +/* TB epilogue */
> tb_ret_addr = s->code_ptr;
>
> /* Remove TCG locals stack space. */
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Debug = (env->CP0_Debug & ~(0x1fULL << CP0DB_DEC)) | 9 <<
> CP0DB_DEC;
> goto set_DEPC;
> case EXCP_DDBS:
> env->CP0_Debug |= 1 << CP0DB_DDBS;
>
Reviewed-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
nc
with env->flags using TCG instructions. ctx->envflags now only contains
the part that of env->flags that is contained in the TB state, i.e. the
DELAY_SLOT* flags.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 161 +-
SH4 requires that memory accesses are naturally aligned, except for the
SH4-A movua.l instructions which can do unaligned loads.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.c | 1 +
targ
There is no need to save flags when entering and exiting the delay slot.
They can be saved only when reaching the end of the TB. If the TB is
interrupted before by an exception, they will be restored using
restore_state_to_opc.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
targ
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8cee7d333f..a4c7a0895b 100644
--- a/target/sh4/translate.c
+++ b/targ
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/targ
At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/tran
Isuing extrh and avoiding intermediate temps.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a4c7a0895b..b4e5606098
dé <f4...@amsat.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 3 +--
target/sh4/helper.c| 2 --
target/sh4/translate.c | 17 +
3 files changed, 6 insertions(+), 16 deletions(-)
diff --git a/target/sh4/cpu.h b/target/sh4/cpu.
DELAY_SLOT_TRUE is used as a dynamic condition for the branch after the
delay slot instruction. It is not used in code generation, so there is
no need to including in the TB state.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 3 +--
1 file changed, 1 ins
In case of exception, there is no need to call tcg_gen_exit_tb as the
exception helper won't return.
Also fix a few cases where BS_BRANCH is called instead of BS_EXCP.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 16 +++-
1 file chan
order to be
able to discard the global before the brcond.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 10 ++
target/sh4/helper.c| 2 +-
target/sh4/translate.c | 22 +-
3 files changed, 16 insertions(+), 18 deletions(-)
We only emulate UP SH4, however as the tas.b instruction is used in the GNU
libc, this improve linux-user emulation.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/targ
When stopping the translation because the state has changed, goto_tb
should not be used as it might link TB with different flags.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/targ
synco is a SH4-A only instruction.
Reviewed-by: Philippe Mathieu-Daudé <f4...@amsat.org>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4
some comments in the struct DisasContext declaration, as suggested
by Philippe Mathieu-Daudé
- Add Reviewed-by entries
Aurelien Jarno (14):
target/sh4: split ctx->flags into ctx->tbflags and ctx->envflags
target/sh4: get rid of DELAY_SLOT_CLEARME
target/sh4: do not include DELAY_
changes up to 2f5a5f5774d95baacf86c03aa8a77a2d0390f2b2:
tcg/mips: fix field extraction opcode (2017-05-06 12:48:53 +0200)
Fix MIPS R2 hosts support
Aurelien Jarno
The "msb" argument should correspond to (len - 1).
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-target.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 01ac7b2c81..2
On 2017-05-02 18:21, Richard Henderson wrote:
> On 04/30/2017 04:52 PM, Aurelien Jarno wrote:
> > +/* jmp to the given host address (could be epilogue) */
> > +tcg_out_opc_reg(s, OPC_JR, 0, a0, 0);
> > +tcg_out_nop(s);
>
> Any particular r
On 2017-05-02 09:16, Philippe Mathieu-Daudé wrote:
> Hi Aurelien,
>
> On 05/01/2017 07:10 PM, Aurelien Jarno wrote:
> > There is a confusion (and not only in the SH4 target) between tb->flags,
> > env->flags and ctx->flags. To avoid it, split ctx->flags into
&
There is no need to save flags when entering and exiting the delay slot.
They can be saved only when reaching the end of the TB. If the TB is
interrupted before by an exception, they will be restored using
restore_state_to_opc.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
targ
SH4 requires that memory accesses are naturally aligned, except for the
SH4-A movua.l instructions which can do unaligned loads.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.c | 1 +
target/sh4/cpu.h | 4
target/sh4/op_helper.
order to be
able to discard the global before the brcond.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 10 ++
target/sh4/helper.c| 2 +-
target/sh4/translate.c | 22 +-
3 files changed, 16 insertions(+), 18 deletions(-)
At the same time change the comment describing the instruction the same
way than other instruction, so that the code is easier to read and search.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 26 +++---
1 file changed, 15 insertions(
synco is a SH4-A only instruction.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 7de459c9a5..c226be9718 100644
--- a/targ
In case of exception, there is no need to call tcg_gen_exit_tb as the
exception helper won't return.
Also fix a few cases where BS_BRANCH is called instead of BS_EXCP.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 16 +++-
1 file chan
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index 8c99e4fb21..a8399239d1 100644
--- a/target/sh4/translate.c
+++ b/targ
When stopping the translation because the state has changed, goto_tb
should not be used as it might link TB with different flags.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/targ
DELAY_SLOT_TRUE is used as a dynamic condition for the branch after the
delay slot instruction. It is not used in code generation, so there is
no need to including in the TB state.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/cpu.h | 3 +--
1 file changed, 1 ins
We only emulate UP SH4, however as the tas.b instruction is used in the GNU
libc, this improve linux-user emulation.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 19 +++
1 file changed, 7 insertions(+), 12 deletions(-)
diff --git a/targ
Now that ctx->flags has been split, it becomes clear that
DELAY_SLOT_CLEARME has not impact on the code generation: in both case
ctx->envflags is cleared, either by clearing all the flags, or by
setting it to 0. This is left-over from pre-TCG era.
Signed-off-by: Aurelien Jarno <aurel..
This patch series try to improve the SH4 target by using the (more or
less) recently introduced TCG features. It also fixes some issues spot
when writting the patches (linking of TB with different flags, SH4-A
specific instructions allowed on SH4) and correctly trap unaligned
accesses.
Aurelien
Isuing extrh and avoiding intermediate temps.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 ++---
1 file changed, 2 insertions(+), 7 deletions(-)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index a8399239d1..23636eeb4c
nc
with env->flags using TCG instructions. ctx->envflags now only contains
the part that of env->flags that is contained in the TB state, i.e. the
DELAY_SLOT* flags.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 161 +-
This doesn't change the generated code on x86, but optimizes it on most
RISC architectures and makes the code simpler to read.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/sh4/translate.c | 9 +++--
1 file changed, 3 insertions(+), 6 deletions(-)
diff --git a/targ
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-target.h | 2 +-
tcg/mips/tcg-target.inc.c | 13 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/tcg/mips/tcg-target.h b/tcg/mips/tcg-target.h
index e3240cfba7..d75cb63ed3 100644
--- a/tc
Please find patches to support cross-tb optimizations on MIPS hosts
and to implement cross-tb optimizations for MIPS target.
Aurelien Jarno (3):
tcg/mips: implement goto_ptr
target/mips: optimize cross-page direct jumps in softmmu
target/mips: optimize indirect branches
target/mips
Cc: Yongbok Kim <yongbok@imgtec.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 3022f349cb..1a7ac07c67 100644
--- a
Cc: Yongbok Kim <yongbok@imgtec.com>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/mips/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/mips/translate.c b/target/mips/translate.c
index 1a7ac07c67..559f8fed89 100644
--- a
The "msb" argument should correspond to (len - 1).
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
tcg/mips/tcg-target.inc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg-target.inc.c b/tcg/mips/tcg-target.inc.c
index 01ac7b2c81..2
and other instability
> (e.g. RCU lockup warnings) when booting + shutting down debian jessie
> in the guest.
I agree that always calling lookup_tb_ptr might be suboptimal in case we
know for sure that the lookup will fail or that there will be an exit
request at the begin
On 2017-04-27 11:42, Richard Henderson wrote:
> On 04/27/2017 11:36 AM, Aurelien Jarno wrote:
> > On 2017-04-26 23:29, Emilio G. Cota wrote:
> > > Speed up indirect branches by jumping to the target if it is valid.
> > >
> > > Softmmu measurements (se
s for this patchset. I have tested it with an arm target, but also
with a mips target with and additional patch. I haven't done any precise
benchmark yet. The patch is trivial and only changes 3 lines, but I am
not 100% sure I have done things correctly (see my comment on patch 7).
Tested-by: Aurel
*/
What would be the reason for that? IIUC the lookup_tb_ptr helper calls
cpu_get_tb_cpu_state to get the new TB flags go lookup from the current
CPU state. It means it is able for example to handle a transition from
user to privileged mode. Also the exit_req flag or its new equivalent
is tested at the beginning of each TB in case there is an interruption.
It therefore seems to be that we can replace all calls to
tcg_gen_exit_tb by tcg_gen_lookup_and_goto_ptr with the program counter
in argument.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
io_hypercall in kvm_arch_handle_exit.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
nknown sigp: 0x0005".
Signed-off-by: Philipp Kern <p...@philkern.de>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/misc_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
This patch has been sent by Philipp Kern a lot of time
s390_virtio_hypercall can trigger IO events and interrupts, most notably
when using virtio-ccw devices.
Reviewed-by: Alexander Graf <ag...@suse.de>
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
target/s390x/misc_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --
On 2017-04-23 19:19, Alexander Graf wrote:
>
>
> > Am 23.04.2017 um 18:08 schrieb Aurelien Jarno <aurel...@aurel32.net>:
> >
> > s390_virtio_hypercall can trigger IO events and interrupts, most notably
> > when using virtio-ccw devices.
> >
> >
s390_virtio_hypercall can trigger IO events and interrupts, most notably
when using virtio-ccw devices.
Signed-off-by: Aurelien Jarno <aurel...@aurel32.net>
---
roms/qemu-palcode | 2 +-
roms/seabios | 2 +-
target/s390x/misc_helper.c | 2 ++
3 files changed, 4 inse
On 2017-04-21 17:18, BALATON Zoltan wrote:
> v7: Define default values for some variables to avoid an (invalid)
> warning from gcc 6 or 7 as suggested by Aurelien Jarno.
Thanks a lot for this new version, I confirm it now builds fine with GCC
6 or 7.
--
Aurelien
5 -
> include/hw/pci/pci_ids.h |3 +
> 8 files changed, 1150 insertions(+), 746 deletions(-)
I have tested this patchset on an SH4 machine and I haven't found any
regression.
Tested-by: Aurelien Jarno <aurel...@aurel32.net>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
[-Wmaybe-uninitialized]
| draw_hwc_line(d, hwc_src, width, hwc_palette, c_x, y - c_y);
| ^~~
GCC fails to notice that hwc_src, c_x and c_y are always defined if
draw_hwc_line is not NULL. This is obvio
ody has a lot of interest in ia64 anymore, so I guess
it's time to just remove the ia64 host backend.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
d/st for mips64 | Fix a style problem |
Thanks for the new version. I just gave it a try on a mips64 le guest,
and I confirm this fixes booting mips64 be and ppc64 guests. I'll try to
do more tests on mips be / mips le / mips64 le over the week-end.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Oops sorry, I answered the wrong mail. The results *are* against *v4*
not v3.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2016-11-30 09:42, Richard Henderson wrote:
> On 11/30/2016 09:22 AM, Aurelien Jarno wrote:
> > On 2016-11-29 14:07, Jin Guojie wrote:
> >> @@ -1312,7 +1340,12 @@ static void tcg_out_qemu_ld_slow_path(TCGContext
> >> *s, TCGLabelQemuLdst *l)
> >>
ut_opc_reg(s, OPC_OR, v0, TCG_REG_V0, TCG_REG_ZERO);
> +}
While thoses are equivalent, I think it would be clearer to keep the
original version for the else case (ie tcg_out_mov) instead of replacing
it by a OR instruction.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
uld block merging the mips64 support on that.
I now plan to do more testing on mips32 be hosts and also test mips32
le hosts. Unfortunately I don't have a way to test mips R6 and mips64 be
hosts.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
?
> ... Maybe the maintainer of the board (Magnus) knows the answer here...
The third serial port is provided by the graphic chipset. The first two
serial ports are provided by the SH7750 CPU, see in hw/sh4/sh7750.c.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
signature.asc
Description: PGP signature
PR rs does not contain a sign-extended 32-bit value (bits 63..31
| equal), then the result of the operation is UNPREDICTABLE.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
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