t-sparc/translate.c | 55
>
> 1 file changed, 28 insertions(+), 27 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-09-22 12:26, Thomas Huth wrote:
> On 13/09/15 23:03, Aurelien Jarno wrote:
> > The xscmpodp and xscmpudp instructions only have the AX, BX bits in
> > there encoding, the lowest bit (usually TX) is marked as an invalid
> > bit. We therefore can't decode them with
+++---
> 1 file changed, 10 insertions(+), 11 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ich will be good for bisection,
> and it certainly does save storage space.
>
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target-cris/translate.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno
On 2015-09-17 21:55, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target-sh4/cpu.h | 1 +
> target-sh4/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
On 2015-09-17 21:55, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target-s390x/cpu.h | 1 +
> target-s390x/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
On 2015-09-17 21:55, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target-i386/cpu.h | 1 +
> target-i386/translate.c | 2 +-
> 2 files changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
On 2015-09-17 21:55, Richard Henderson wrote:
> Reviewed-by: Peter Maydell
> Signed-off-by: Richard Henderson
> ---
> target-mips/cpu.h | 1 +
> target-mips/translate.c | 3 ++-
> 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Aurelien Jarno
; tcg/tcg-op.h | 52
> tcg/tcg-opc.h | 4 ++--
> tcg/tcg.c | 13 +++--
> tcg/tcg.h | 6 ++
> 4 files changed, 59 insertions(+), 16 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 40
tions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
-tricore/translate.c| 3 +--
> target-unicore32/translate.c | 4 ++--
> target-xtensa/translate.c | 4 ++--
> 19 files changed, 41 insertions(+), 39 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
; target-unicore32/translate.c | 5 +
> target-xtensa/translate.c | 5 +
> 20 files changed, 41 insertions(+), 81 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ate.c | 2 +-
> target-unicore32/translate.c | 2 +-
> target-xtensa/translate.c | 2 +-
> tcg/tcg-op.h | 6 +++---
> tcg/tcg-opc.h | 4 ++--
> tcg/tcg.c | 6 +++---
> tci.c | 9 -----
t9,t9,v0
bne at,t9,0x836d838
- nop
+ lw at,9140(a0) load high comparator
+lw a0,9160(a0) load addend
-bne v0,a1,0x836d838
+bne at,a1,0x836d838
addu v0,a0,v0
lw t0,0(v0)
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson
Reviewed-by: Aurelien
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg
81dfaf1a8f7f95259801da9732472f879023ef77:
tcg/mips: pass oi to tcg_out_tlb_load (2015-09-19 11:53:15 +0200)
TCG MIPS queue
- Fixes for 64-bit guests
- Small cleanups
Aurelien
Somehow the tcg_out_addsub2 function ended-up in the middle of the
qemu_ld/st related functions. Move it with other arithmetics related
functions.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 98 +--
1
Instead of computing mem_index and s_bits in both tcg_out_qemu_ld and
tcg_out_qemu_st function and passing them to tcg_out_tlb_load, directly
pass oi to the tcg_out_tlb_load function and compute mem_index and
s_bits there.
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 20
Somehow the tcg_out_addsub2 function ended-up in the middle of the
qemu_ld/st related functions. Move it with other arithmetics related
functions.
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 98 +--
1 file changed, 49 insertions
I have these patches for quite some time in one of my local branch in
the hope I would have time to do further changes. Given that I am going
to send a pull request for the 64-bit qemu_ld issue, I think it's a good
opportunity to also include them.
Aurelien Jarno (2):
tcg/mips:
igh comparator
> +lw a0,9160(a0) load addend
> -bne v0,a1,0x836d838
> +bne at,a1,0x836d838
> addu v0,a0,v0
> lw t0,0(v0)
>
> Suggested-by: Richard Henderson
> Signed-off-by: James Hogan
> Cc: Aurelien Jarno
> ---
> Tested with m
: Alex Smith
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
> Changes in v2:
> - Fix build breakage for user builds.
> - Correct existing code to follow QEMU coding style.
> ---
> target-mips/op_helper.c | 9 +++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
ecent, that's why we
had it opened coded up to now.
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
t there introduced a serious performance regression in user mode:
https://lists.gnu.org/archive/html/qemu-devel/2015-08/msg01620.html
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
sr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd001u);
> -idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired;
> + idx = lfsr % nb_rand_tlb + env->CP0_Wired;
> } while (idx == prev_idx);
> prev_idx = idx;
> return idx;
_load_gpr(t0, rs);
> tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16);
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 8 ++--
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index be0cb32..50043cf 100644
--- a/target-sh4/translate.c
+++ b/target-sh4
o, since the high bits
set due to a value greater than 0x80 in the first sub-expression are
masked off by the second.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/translate.c | 17 +
1 file changed, 5 insertions(+), 12 deletions(-)
diff -
From: Guenter Roeck
If host and target endianness does not match, loding an initramfs does not work.
Fix by writing boot parameters with appropriate endianness conversion.
Signed-off-by: Guenter Roeck
Signed-off-by: Aurelien Jarno
---
hw/sh4/r2d.c | 6 +++---
1 file changed, 3 insertions
Most floating point helpers can trigger an exception, but don't change
the globals. Mark these helpers as TCG_CALL_NO_WG.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
target-sh4/helper.h | 34 +-
1 file changed, 17 insertions(+), 17 dele
endianness issue
----
Aurelien Jarno (5):
target-sh4: add flags markups for FP helpers
target-sh4: use deposit in swap.b instruction
target-sh4: improve cmp/str instruction
target-sh4: improve shld instruction
: Aurelien Jarno
---
target-sh4/translate.c | 53 +-
1 file changed, 22 insertions(+), 31 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index c8dd3a7..724c0e7 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
: Aurelien Jarno
---
target-sh4/translate.c | 48 ++--
1 file changed, 22 insertions(+), 26 deletions(-)
diff --git a/target-sh4/translate.c b/target-sh4/translate.c
index ca6ef5a..c8dd3a7 100644
--- a/target-sh4/translate.c
+++ b/target-sh4/translate.c
tters translate.c.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 624 ++--
1 file changed, 19 insertions(+), 605 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
index 93cb4f2..36bc25d 100644
--- a/t
, it's
probably time to apply it.
Aurelien Jarno (2):
target-mips: get rid of MIPS_DEBUG
target-mips: get rid of MIPS_DEBUG_SIGN_EXTENSIONS
target-mips/translate.c | 663 ++--
1 file changed, 19 insertions(+), 644 deletions(-)
--
2.1.4
MIPS_DEBUG_SIGN_EXTENSIONS was used sometimes ago to verify that 32-bit
instructions correctly sign extend their results. It's now not need
anymore, remove it.
Cc: Leon Alrae
Signed-off-by: Aurelien Jarno
---
target-mips/translate.c | 39 ---
1 file ch
temporary variable.
This fixes openssl when emulating a POWER8 CPU.
Cc: Tom Musta
Cc: Alexander Graf
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno
---
target-ppc/int_helper.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target-ppc/int_helper.c
k
the lowest bit as invalid.
Cc: Tom Musta
Cc: Alexander Graf
Cc: qemu-sta...@nongnu.org
Signed-off-by: Aurelien Jarno
---
target-ppc/translate.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index 84c5cea..c0eed13 1
This patchset fixes some vector instructions which are incorrectly
decoded or implemented. The first patch is needed to run recent version
of openssl, as it enabled POWER8 instrutctions when it detects such a
CPU.
Aurelien Jarno (2):
target-ppc: fix vcipher, vcipherlast, vncipherlast and
On 2015-09-10 19:48, Aurelien Jarno wrote:
> On 2015-09-01 22:51, Richard Henderson wrote:
> > I've been looking at this problem off and on for the last week or so,
> > prompted by the sparc performance work. Although I havn't been able
> > to get a proper sparc64 g
init_temp_info(args[i]);
> + for (i = 0; i < nb_oargs + nb_iargs; i++) {
> +init_temp_info(args[i]);
> +}
> }
>
> /* Do copy propagation */
>
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ooks like the good way to proceed, we just have to take care
that the informations to store do not take too much space compared to
the actual translated code.
I'll give a look and a test asap.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
d / or slowbess comes from is not correct
> > how are SPARC64 benchmarks done usually?
>
> *shrug* No different than any other...
It would be interesting to know if the time taking to generate code is
actually used for code translation or code re-translation. The way the
M
el functions when I zoom into qemu
> thread. Is this qemu signal handling?
> And then it would be interesting to know where in this listing is the
> generated code. Is it [vdso], [unknown] or is it hidden behind
> retint_signal?
>
> Ironically a good optimization target seems to be the tcg_optimize
> function. If I zoom I see it spends most of the time in
> reset_all_temps.
>
> Any suggestions how to improve it?
>
Try this patch:
http://lists.nongnu.org/archive/html/qemu-devel/2015-08/msg02042.html
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
(INITRD_LOAD_OFFSET);
> +boot_params.initrd_size = tswap32(initrd_size);
> }
>
> if (kernel_cmdline) {
Reviewed-by: Aurelien Jarno
Good catch. I have added it to my sh4-next queue:
http://git.aurel32.net/?p=qemu.git;a=shortlog;h=refs/heads/sh4-next
--
Au
On 2015-08-13 23:03, Mark Cave-Ayland wrote:
> On 01/08/15 19:33, Aurelien Jarno wrote:
>
> > On 2015-08-01 17:54, Mark Cave-Ayland wrote:
> >> The existing code incorrectly changes the dma_active flag when a non-block
> >> transfer has completed leading to a h
On 2015-08-17 12:38, Richard Henderson wrote:
> From: Aurelien Jarno
>
> Now that we have real size changing ops, we don't need to mark high
> bits of the destination as garbage. The goal of the optimizer is to
> predict the value of the temps (and not of the registers) and
ecific definition from the global
> namespace.
>
> Cc: Aurelien Jarno
> Signed-off-by: Peter Crosthwaite
> ---
> target-sh4/cpu.h | 2 --
> 1 file changed, 2 deletions(-)
Acked-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
_MIPS directly, as that is
> architecture specific code.
>
> This removes another architecture specific definition from the global
> namespace.
>
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> Signed-off-by: Peter Crosthwaite
> ---
> hw/mips/mips_fulong2e.c | 2 +-
> hw
n under debian(with virtio) a 50sek speedup, netbsd
> (without virtio) just gains 30sek
How big is the source file and the output file? I find strange that I/O
impacts so much for a compilation which should be CPU bounded. Maybe try
to add the -pipe argument to g++.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
xception and retranslation
for the two cases. That said if we want deterministic code execution
(the original purpose of this patch), I don't see how we can do without
forcing retranslation. Pavel, do you have an idea for that?
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
t it will make any
measurable difference in speed. For the MIPS case, that doesn't work
for 16-bit load/stores though.
The best would indeed be to switch to softmmu for the user mode. I know
there are people working on that, but given that it might take time, it
could be a simple temporary so
On 2015-08-09 10:51, Alex Bennée wrote:
>
> Aurelien Jarno writes:
>
> > On 2015-08-09 09:11, Alex Bennée wrote:
> >>
> >> Aurelien Jarno writes:
> >>
> >> > On 2015-08-07 19:03, Alvise Rigo wrote:
> >> >> Introduce the ne
On 2015-08-09 09:11, Alex Bennée wrote:
>
> Aurelien Jarno writes:
>
> > On 2015-08-07 19:03, Alvise Rigo wrote:
> >> Introduce the new --enable-tcg-ldst-excl configure option to enable the
> >> LL/SC operations only for those backends that support them.
>
}
I am not sure it's a good idea to try to use the existing code. For
LL/SC ops, we don't have the slow path and the fast path, as we always
call the helpers. It's probably better to use dedicated code for calling
the helper.
Also given that TCG is already able to handle call helpers
try to provide
the corresponding patches for mips and ia64.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-05 12:08, Peter Maydell wrote:
> On 28 July 2015 at 19:03, Aurelien Jarno wrote:
> > On 2015-07-28 19:22, Stefan Weil wrote:
> >> are there QEMU developers at the Debian Conference 2015 in Heidelberg
> >> (Germany)
> >> (http://debconf15.debconf.org/
On 2015-08-04 13:55, Alex Bennée wrote:
>
> Aurelien Jarno writes:
>
> > On 2015-08-04 08:39, Alex Bennée wrote:
> >>
> >> Paolo Bonzini writes:
> >>
> >> > On 03/08/2015 11:14, Alex Bennée wrote:
> >> >> This allows the
clude "crypto/init.h"
> +#include "qemu-common.h"
>
> #define MAX_VIRTIO_CONSOLES 1
> #define MAX_SCLP_CONSOLES 1
> @@ -3348,6 +3349,9 @@ int main(int argc, char **argv, char **envp)
> case QEMU_OPTION_D:
> log_file = optarg;
> break;
> +case QEMU_OPTION_PERFMAP:
> +tb_enable_perfmap();
> +break;
> case QEMU_OPTION_s:
> add_device_config(DEV_GDB, "tcp::" DEFAULT_GDBSTUB_PORT);
> break;
> --
> 2.5.0
>
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
ap);
> }
>
> -void qemu_log_mask(int mask, const char *fmt, ...)
> -{
> -va_list ap;
> -
> -va_start(ap, fmt);
> -if ((qemu_loglevel & mask) && qemu_logfile) {
> -vfprintf(qemu_logfile, fmt, ap);
> - }
> -
-y2k -Winit-self
> > -Wignored-qualifiers $gcc_flags"
>
> Why do we need this warning switch change?
Some locales might have the year on 2 digits only, so this triggers a
warning. That's also a reason I suggested to use a fixed date format.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
tb_page_addr_t phys_pc, phys_page2;
> target_ulong virt_page2;
> -int code_gen_size;
>
> phys_pc = get_page_addr_code(env, pc);
> if (use_icount) {
> @@ -1045,12 +1036,14 @@ TranslationBlock *tb_gen_code(CPUState *cpu,
> tcg_ctx.tb_ctx.tb_invalidated_flag = 1;
> }
> tb->tc_ptr = tcg_ctx.code_gen_ptr;
> +tb->tc_size = 0;
> tb->cs_base = cs_base;
> tb->flags = flags;
> tb->cflags = cflags;
> -cpu_gen_code(env, tb, &code_gen_size);
> -tcg_ctx.code_gen_ptr = (void *)(((uintptr_t)tcg_ctx.code_gen_ptr +
> -code_gen_size + CODE_GEN_ALIGN - 1) & ~(CODE_GEN_ALIGN - 1));
> +cpu_gen_code(env, tb);
> +tcg_ctx.code_gen_ptr = (void *) (
> +((uintptr_t) tcg_ctx.code_gen_ptr + tb->tc_size + CODE_GEN_ALIGN - 1)
> +& ~(CODE_GEN_ALIGN - 1));
>
> /* check next page if needed */
> virt_page2 = (pc + tb->size - 1) & TARGET_PAGE_MASK;
> --
> 2.5.0
>
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
late_for_iotlb(cpu, paddr, &xlat, &sz);
> assert(sz >= TARGET_PAGE_SIZE);
>
> -#if defined(DEBUG_TLB)
> -qemu_log_mask(CPU_LOG_MMU,
> - "tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
> - " prot=%x idx=%d\n",
> - vaddr, paddr, prot, mmu_idx);
> -#endif
> +tlb_debug("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
> + " prot=%x idx=%d\n",
> + vaddr, paddr, prot, mmu_idx);
>
> address = vaddr;
> if (!memory_region_is_ram(section->mr) &&
> !memory_region_is_romd(section->mr)) {
> --
> 2.5.0
>
>
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
qemu_log("System Emulation started at %s\n", fmt_time);
> + qemu_log("Invocation:");
> +for (i = 0; i < argc; i++) {
> +qemu_log("%s ", argv[i]);
> +}
> +qemu_log("\n");
> +}
> }
>
> if (!is_daemonized()) {
Otherwise:
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
_IN_ASM)) {
> +if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) &&
> +qemu_log_in_addr_range(pc_start)) {
> qemu_log("\n");
> qemu_log("IN: %s\n", lookup_symbol(pc_start));
> log_target_disas(cs, pc_start, dc->pc - pc_start,
We probably want to do the same for the other architectures.
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
gt; #endif
>
> #ifdef DEBUG_DISAS
> -if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT))) {
> +if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP_OPT)
> + && qemu_log_in_addr_range(tb->pc))) {
> qemu_log("OP after optimization and liveness a
tarting at 0x8000
> and
> +the 0x200 sized block starting at 0xffc8.
> +ETEXI
> +
> DEF("L", HAS_ARG, QEMU_OPTION_L, \
> "-L path set the directory for the BIOS, VGA BIOS and keymaps\n",
> QEMU_ARCH_ALL)
> diff --git
+282,9 @@ static inline void tb_add_jump(TranslationBlock *tb, int
> n,
> {
> /* NOTE: this test is only needed for thread safety */
> if (!tb->jmp_next[n]) {
> +qemu_log_mask(CPU_LOG_EXEC, "Linking TBs %p [" TARGET_FMT_lx
> + "] index %d -> %p [" TARGET_FMT_lx "]\n",
> + tb->tc_ptr, tb->pc, n, tb_next->tc_ptr, tb_next->pc);
> /* patch the native jump address */
> tb_set_jmp_target(tb, n, (uintptr_t)tb_next->tc_ptr);
>
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
"log MMU-related activities" },
> { CPU_LOG_PCALL, "pcall",
In practice this is not true for linked TB. Should we also disable TB
linking when this option is enabled?
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
e);
> +}
> +} else {
> + logfilename = g_strdup(filename);
> +}
> qemu_log_close();
> qemu_set_log(qemu_loglevel);
> }
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
d back to the
end of the previous TB. In that case the last entry of the dump might
should be replaced by the new value. If the invalidated TB is not the
last one, it is just left in the generated code.
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-03 14:41, Richard Henderson wrote:
> On 08/03/2015 02:31 PM, Aurelien Jarno wrote:
> >On 2015-08-03 12:35, Richard Henderson wrote:
> >> if (msb != 31) {
> >>-tcg_gen_andi_tl(t0, t0, (1 << (msb + 1)) - 1);
> >>+
n_deposit_tl(t0, t0, t1, lsb + 32, msb - lsb + 1);
> -break;
> +lsb += 32;
> +/* FALLTHRU */
> +case OPC_DINSM:
> +msb += 32;
The same way DINSM can't fail.
> +/* FALLTHRU */
> case OPC_DINS:
> +
hanged, 13 insertions(+), 20 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
/lists.gnu.org/archive/html/qemu-devel/2015-07/msg02581.html
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
-by: Leon Alrae
> ---
> target-mips/translate.c | 10 +++---
> 1 file changed, 7 insertions(+), 3 deletions(-)
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-03 10:31, Artyom Tarasenko wrote:
> Hi Aurelien,
>
> On Fri, Jul 31, 2015 at 5:43 PM, Aurelien Jarno wrote:
>
> >> > It uses a lot of integer functions
> >> > based on CPU flags, so most of the time is spent computing them in
> >> > he
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG S390 backend.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/s390/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/s390
For 32-bit guest, we load a 32-bit address from the TLB, so there is no
need to compensate for the low or high part. This fixes 32-bit guests on
big-endian hosts.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 4 +++-
1 file
.
Aurelien Jarno (4):
tcg/mips: fix TLB loading for BE host with 32-bit guests
tcg/mips: Mask TCGMemOp appropriately for indexing
tcg/s390x: Mask TCGMemOp appropriately for indexing
tcg/mips: fix add2
tcg/mips/tcg-target.c | 11
guests to boot on a
MIPS host.
Cc: qemu-sta...@nongnu.org
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 064db46..e97980d 100644
--- a/tcg/mips/tc
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG MIPS backend.
Reviewed-by: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips
.00: status: { DRDY ERR }
[ 307.271251] ata2.00: configured for MWDMA2
[ 307.271824] ata2: EH complete
The CD-ROM is fully functional though.
Aurelien
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
On 2015-08-01 12:21, Mark Cave-Ayland wrote:
> On 28/07/15 19:02, Aurelien Jarno wrote:
>
> >> Thanks for the heads-up. I have a fairly comprehensive suite of various
> >> OS test images I use for OpenBIOS testing and evidently not a single one
> >> of them iss
On 2015-08-01 12:10, Mark Cave-Ayland wrote:
> On 29/07/15 20:27, Aurelien Jarno wrote:
>
> > Commit bd4214fc dropped TRIM support by mistake. Given it is still
> > advertised to the host when using a drive with discard=on, this cause
> > the IDE bus to hang when the ho
On 2015-07-31 17:31, Artyom Tarasenko wrote:
> On Thu, Jul 30, 2015 at 5:50 PM, Aurelien Jarno wrote:
> > On 2015-07-30 10:55, Aurelien Jarno wrote:
> >> On 2015-07-30 10:16, Dennis Luehring wrote:
> >> > Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
> >>
guests to boot on a
MIPS host.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/tcg/mips/tcg-target.c b/tcg/mips/tcg-target.c
index 064db46..e97980d 100644
--- a/tcg/mips/tcg-target.c
+++ b/tcg/mips/tcg-target.c
his one.
Reviewed-by: Aurelien Jarno
--
Aurelien Jarno GPG: 4096R/1DDD8C9B
aurel...@aurel32.net http://www.aurel32.net
For 32-bit guest, we load a 32-bit address from the TLB, so there is no
need to compensate for the low or high part. This fixes 32-bit guests on
big-endian hosts.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG S390 backend.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/s390/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/s390/tcg
These are small fixes for MIPS and S390 hosts, found by testing various
guests on these hosts.
Aurelien Jarno (3):
tcg/mips: fix TLB loading for BE host with 32-bit guests
tcg/mips: Mask TCGMemOp appropriately for indexing
tcg/s390x: Mask TCGMemOp appropriately for indexing
tcg/mips/tcg
Commit 2b7ec66f fixed TCGMemOp masking following the MO_AMASK addition,
but two cases were forgotten in the TCG MIPS backend.
Cc: Richard Henderson
Signed-off-by: Aurelien Jarno
---
tcg/mips/tcg-target.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/tcg/mips/tcg
think it's
safer to go like in your patch.
> Signed-off-by: Peter Maydell
> ---
> I don't have a fulong2e image, so this is compile tested only...
I have just tested, it still boots fine with the change.
> hw/pci-host/bonito.c | 16
> 1 file changed, 16
On 2015-07-30 10:55, Aurelien Jarno wrote:
> On 2015-07-30 10:16, Dennis Luehring wrote:
> > Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
> > >On 2015-07-30 05:52, Dennis Luehring wrote:
> > >> Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
> > >> &g
On 2015-07-30 11:35, Artyom Tarasenko wrote:
> On Thu, Jul 30, 2015 at 10:55 AM, Aurelien Jarno wrote:
> > On 2015-07-30 10:16, Dennis Luehring wrote:
> >> Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
> >> >On 2015-07-30 05:52, Dennis Luehring wrote:
> >
On 2015-07-30 10:16, Dennis Luehring wrote:
> Am 30.07.2015 um 09:52 schrieb Aurelien Jarno:
> >On 2015-07-30 05:52, Dennis Luehring wrote:
> >> Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
> >> >The point is that emulation has a cost, and it's quite diff
he unaligned access it's actually the reverse. The fact that
aarch64 does unaligned access means they have to go through the slow
path (I have posted a patch to improve that). On sparc given that all
access are aligned means there are more chances to go through the fast
path.
-
On 2015-07-30 05:52, Dennis Luehring wrote:
> Am 29.07.2015 um 17:01 schrieb Aurelien Jarno:
> >The point is that emulation has a cost, and it's quite difficult to
> >to lower it and thus improve the emulation speed.
>
> so its just not strange for you to see an 1/1
On 2015-07-29 21:42, Alex Bennée wrote:
>
> Aurelien Jarno writes:
>
> > On 2015-07-29 17:12, Alex Bennée wrote:
> >>
> >> Aurelien Jarno writes:
> >>
> >> > Now that copies and constants are tracked separately, we can allow
> &g
Cave-Ayland
Cc: John Snow
Signed-off-by: Aurelien Jarno
---
hw/ide/macio.c | 28
1 file changed, 28 insertions(+)
diff --git a/hw/ide/macio.c b/hw/ide/macio.c
index a55a479..66ac2ba 100644
--- a/hw/ide/macio.c
+++ b/hw/ide/macio.c
@@ -208,6 +208,33 @@ static void
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