of 6d00c6f98256 ("Merge tag 'for-upstream' of
https://repo.or.cz/qemu/kevin into staging")
v1: https://lore.kernel.org/qemu-devel/cover.1718218999.git.babu.mo...@amd.com/
--
2.34.1
Babu Moger (3):
i386/cpu: Add RAS feature bits on EPYC CPU models
i386/cpu: Enabl
interrupts.
McaOverflowRecov: MCA overflow recovery support.
Signed-off-by: Babu Moger
Reviewed-by: Zhao Liu
---
v2: Just added reviewed by from Zhao.
---
target/i386/cpu.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
3.41.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Reviewed-by: Zhao Liu
---
v2: Minor typo.
Added Reviewed-by from Zhao.
---
target/i386/cpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
determine
the number of available counters for different PMUs. It also denotes the
availability of global control and status registers.
Add the required CPUID feature word and feature bit to allow guests to
make use of the PerfMonV2 features.
Signed-off-by: Sandipan Das
Signed-off-by: Babu Moger
avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
of Mask Register
avx-vnni : AVX VNNI Instruction
Signed-off-by: Babu Moger
Reviewed-by: Zhao Liu
---
v2: Fixed minor typo.
Added Zhao's Reviewed-by.
---
target/i386/cpu.c
This series adds the support for following features in qemu.
1. RAS feature bits (SUCCOR, McaOverflowRecov)
2. perfmon-v2
3. Update EPYC-Genoa to support perfmon-v2 and RAS bits
4. Add support for EPYC-Turin
Babu Moger (3):
i386/cpu: Add RAS feature bits on EPYC CPU models
i386/cpu: Enable
3.41.
Signed-off-by: Babu Moger
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
---
target/i386/cpu.c | 15 +++
1 file changed, 15 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 7f1837cdc9..64e6dc62e2 100644
--- a/target/i386/cpu.c
+++ b/target/i386/
interrupts.
McaOverflowRecov: MCA overflow recovery support.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 30 ++
1 file changed, 30 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 165b982c8c..86a90b1405 100644
--- a/target/i386/cpu.c
+++ b
determine
the number of available counters for different PMUs. It also denotes the
availability of global control and status registers.
Add the required CPUID feature word and feature bit to allow guests to
make use of the PerfMonV2 features.
Signed-off-by: Sandipan Das
Signed-off-by: Babu Moger
avx512-vp2intersect: AVX512 Vector Pair Intersection to a Pair
of Mask Register
avx-vnni : AVX VNNI Instruction
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 131 ++
1 file changed, 131 insertions(+)
diff --git a/target
01E for AMD")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Reviewed-by: Zhao Liu
Signed-off-by: Babu Moger
---
v3:
Rebased to the latest tree.
Updated the pc_compat_9_0 for the new flag.
v2:
https://lore.kernel.org/kvm/20240102231738.46553-1-babu.mo...@amd.com/
Rebased to t
01E for AMD")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Reviewed-by: Zhao Liu
---
v2: Rebased to the latest tree.
Updated the pc_compat_8_2 for the new flag.
Added the comment for new property legacy_multi_node.
Added Rev
01E for AMD")
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
hw/i386/pc.c | 4 +++-
target/i386/cpu.c | 18 ++
target/i386/cpu.h | 1 +
3 files changed, 14 insertions(+), 9 deletions(-)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 1
s on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link:
https://w
G
c. AMD64 Architecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link:
https://www.amd.com/system/files/documents/securit
2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
---
target/i386/cpu.c | 24
target/i386/cpu.h | 8
2 files changed
chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Santosh Shukla
Signed-off-by: Kim Phillips
Signed-off-by: Babu Moger
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/file
is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger
---
target/i3
LR_BASE to
match the kernel name.
https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/
v1:
https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/
v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com/
v3: https://lore.kernel.
lse in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 118 ++
1 file changed, 118 insertion
Definition",
to allow new cache_info pointers to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 35 ---
ARS_BASE to NULL_SEL_CLR_BASE to
match the kernel name.
https://lore.kernel.org/kvm/20221205233235.622491-3-kim.phill...@amd.com/
v1:
https://lore.kernel.org/kvm/167001034454.62456.7111414518087569436.stgit@bmoger-ubuntu/
v2: https://lore.kernel.org/kvm/20230106185700.28744-1-babu.mo...@amd.com
2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
---
target/i386/cpu.c | 24
target/i386/cpu.h | 8
2 files changed
chitecture Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Santosh Shukla
Signed-off-by: Kim Phillips
Signed-off-by: Babu Moger
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/file
Programmer’s Manual Volumes 1–5 Publication No. Revision
40332 4.05 Date October 2022
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link:
https://www.amd.com/system/files/documents/security-analysis-predictive-store
lse in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 118 ++
1 file changed, 118 insertion
is a "set-and-forget" feature that means that, unlike e.g.,
s/w-toggled SPEC_CTRL.IBRS, h/w manages its IBRS mitigation
resources automatically across CPL transitions.
Signed-off-by: Babu Moger
---
target/i3
to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
---
target/i386/cpu.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --
s on.
The documentation for the features are available in the links below.
a. Processor Programming Reference (PPR) for AMD Family 19h Model 01h,
Revision B1 Processors
b. SECURITY ANALYSIS OF AMD PREDICTIVE STORE FORWARDING
Signed-off-by: Babu Moger
Acked-by: Michael S. Tsirkin
Link:
https://w
This series adds following changes.
a. Allow versioned CPUs to specify new cache_info pointers.
b. Add EPYC-v4, EPYC-Rome-v3 and EPYC-Milan-v2 fixing the
cache_info.complex_indexing.
c. Introduce EPYC-Milan-v2 by adding few missing feature bits.
---
Babu Moger (3):
target/i386: Add a
tive-store-forwarding.pdf
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Signed-off-by: Babu Moger
---
target/i386/cpu.c |4 ++--
target/i386/cpu.h |4
2 files changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
2022
Link: https://www.amd.com/system/files/TechDocs/55898_B1_pub_0.50.zip
Link: https://www.amd.com/system/files/TechDocs/40332_4.05.pdf
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 24
target/i386/cpu.h |8
2 files changed, 32 insertions(+)
diff
lse in the future. Setting this bit will also cause
CPUID validation failures when running SEV-SNP guests.
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 118 +
1 file changed, 118 insertions(+)
diff --git a/t
to be specified for a new CPU version.
Co-developed-by: Wei Huang
Signed-off-by: Wei Huang
Signed-off-by: Michael Roth
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 36 +---
1 file changed, 33 insertions(+), 3 deletions(-)
diff --git a/target/i386/cpu.c b/t
/TechDocs/40332_4.05.pdf
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 70 +
1 file changed, 70 insertions(+)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e9175da92f..54549a5127 100644
--- a/target/i386/cpu.c
+++ b/target/i386
6:08 AM Daniel P. Berrangé
>>> wrote:
>>>> CC'ing Babu Moger who aded the Milan CPU model.
>>>>
>>>> On Sat, Jan 29, 2022 at 07:23:37AM -0300, Leonardo Bras wrote:
>>>>> While trying to bring a VM with EPYC-Milan cpu on a host with
>>&g
David, Are you still working on v2 of these series? I was going to test
and review. Thanks
> -Original Message-
> From: David Edmondson
> Sent: Tuesday, June 8, 2021 3:25 AM
> To: qemu-devel@nongnu.org
> Cc: k...@vger.kernel.org; Eduardo Habkost ; Paolo
> Bonzini ; Marcelo Tosatti ;
> Ric
On 6/29/21 9:06 AM, Dr. David Alan Gilbert wrote:
> * zhenwei pi (pizhen...@bytedance.com) wrote:
>> A AMD server typically has cpuid level 0x10(test on Rome/Milan), it
>> should not be changed to 0x1f in multi-dies case.
>>
>> Fixes: a94e1428991 (target/i386: Add CPUID.1F generation support
>>
Hi Wei,
I dont know the background of this feature. I will let some else to
comment on that.
The patch exposes the feature TscInvariant to the guest successfully.
Tested it on my AMD box. I have few comments on your patch below.
On 4/23/21 12:32 AM, Wei Huang wrote:
> There was a customer reques
86: Add missing cpu feature bits in EPYC-Rome
> model
>
> On Wed, Mar 3, 2021 at 5:24 PM wrote:
> >
> > On Wednesday, 2021-03-03 at 09:45:30 -06, Babu Moger wrote:
> >
> > > Found the following cpu feature bits missing from EPYC-Rome model.
> > > ibrs
@Christian,
Yes. This following patch fixes the problem
https://lists.gnu.org/archive/html/qemu-devel/2021-03/msg01020.html
I saw your ping on the patch. I am not sure why it is not picked up. I am going
ping them today.
>If I might ask - how does the kernel fix you referenced interact with th
I remember seeing something similar before. This was supposed to be
fixed by the linux kernel commit.
commit 841c2be09fe4f495fe5224952a419bd8c7e5b455
Author: Maxim Levitsky
Date: Wed Jul 8 14:57:31 2020 +0300
kvm: x86: replace kvm_spec_ctrl_test_value with runtime test on the host
# git descr
machine type)
x86 EPYC-Rome-v1 AMD EPYC-Rome Processor
x86 EPYC-Rome-v2 AMD EPYC-Rome Processor
Reported-by: Pankaj Gupta
Signed-off-by: Babu Moger
Signed-off-by: Pankaj Gupta
---
v2: Model-id remains same between EPYC-Rome-v1 and EPYC-Rome-v2.
Removed model-id in the patch
On 3/3/21 3:42 AM, David Edmondson wrote:
> On Tuesday, 2021-03-02 at 15:20:00 -06, Babu Moger wrote:
>
>> Found the following cpu feature bits missing from EPYC-Rome model.
>> ibrs: Indirect Branch Restricted Speculation
>> ssbd: Speculative Store Bypass
machine type)
x86 EPYC-Rome-v1 AMD EPYC-Rome Processor
x86 EPYC-Rome-v2 AMD EPYC-Rome Processor
Reported-by: Pankaj Gupta
Signed-off-by: Babu Moger
Signed-off-by: Pankaj Gupta
---
target/i386/cpu.c | 14 ++
1 file changed, 14 insertions(+)
diff --git a/target
issue at my end, Sorry! for the confusion.
> Can you please post the official patch for inclusion.
>
> Best regards,
> Pankaj
>
> On Mon, Mar 1, 2021 at 9:38 PM Babu Moger wrote:
>>
>>
>>
>>> -Original Message-
>>> From: Pankaj Gupt
> -Original Message-
> From: Pankaj Gupta
> Sent: Monday, March 1, 2021 2:22 PM
> To: Moger, Babu
> Cc: Pankaj Gupta ; Paolo Bonzini
> ; richard.hender...@linaro.org; Eduardo Habkost
> ; Qemu Developers
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation
> proc
Pankaj,
> -Original Message-
> From: Pankaj Gupta
> Sent: Monday, March 1, 2021 10:46 AM
> To: Pankaj Gupta
> Cc: Moger, Babu ; Paolo Bonzini
> ; richard.hender...@linaro.org; Eduardo Habkost
> ; Qemu Developers
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd generation
Hi Pankaj,
> -Original Message-
> From: Pankaj Gupta
> Sent: Wednesday, February 24, 2021 2:19 AM
> To: Moger, Babu
> Cc: Paolo Bonzini ; richard.hender...@linaro.org;
> Eduardo Habkost ; Qemu Developers de...@nongnu.org>
> Subject: Re: [PATCH v2] i386: Add the support for AMD EPYC 3rd
cept_dr to generic intercepts")
>> 03bfeeb988a9 ("KVM: SVM: Change intercept_cr to generic intercepts")
>> c45ad7229d13 ("KVM: SVM: Introduce
>> vmcb_(set_intercept/clr_intercept/_is_intercept)")
>> a90c1ed9f11d ("(pcid) KVM: nSVM: Remove u
t/_is_intercept)")
a90c1ed9f11d ("(pcid) KVM: nSVM: Remove unused field")
fa44b82eb831 ("KVM: x86: Move MPK feature detection to common code")
38f3e775e9c2 ("x86/Kconfig: Update config and kernel doc for MPK feature on
AMD")
37486135d3a7 ("KVM: x86: Fix pk
, Eduardo Habkost wrote:
> On Fri, Jan 22, 2021 at 10:36:27AM -0600, Babu Moger wrote:
>> Adds the support for AMD 3rd generation processors. The model
>> display for the new processor will be EPYC-Milan.
>>
>> Adds the following new feature bits on top of the feature bits f
Restricted Speculation
ssbd: Speculative Store Bypass Disable
erms: Enhanced REP MOVSB/STOSB support
fsrm: Fast Short REP MOVSB support
invpcid : Invalidate processor context ID
pku : Protection keys support
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 105
tps://bugzilla.redhat.com/show_bug.cgi?id=1834200
Signed-off-by: Babu Moger
---
v2:
Resubmitting an old patch which was lost in the mix.
Just rebased on the latest tree.
v1:
https://lore.kernel.org/qemu-devel/159257395689.52908.4409314503988289481.st...@naples-babu.amd.com/
target/i386/cpu.c |
On 9/18/20 4:38 PM, Eduardo Habkost wrote:
> On Mon, Aug 31, 2020 at 01:43:07PM -0500, Babu Moger wrote:
>> apic_id contains all the information required to build
>> CPUID_8000_001E. core_id and node_id is already part of
>> apic_id generated by x86_topo_ids_from_apicid.
49.st...@naples-babu.amd.com
Babu Moger (2):
i386: Simplify CPUID_8000_001d for AMD
i386: Simplify CPUID_8000_001E for AMD
target/i386/cpu.c | 226 ++---
1 file changed, 61 insertions(+), 165 deletions(-)
--
Remove all the hardcoded values and replace with generalized
fields.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 31 ---
1 file changed, 16 insertions(+), 15 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ba4667b33c..b12addf323 100644
.
Refer the Processor Programming Reference (PPR) documentation
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
target/i386/cpu.c | 195 -
1
On 9/1/20 6:52 AM, Igor Mammedov wrote:
> On Mon, 31 Aug 2020 13:43:01 -0500
> Babu Moger wrote:
>
>> Remove all the hardcoded values and replace with generalized
>> fields.
>>
>> Signed-off-by: Babu Moger
>> ---
>> target/i386/cpu.c | 31 +
Remove all the hardcoded values and replace with generalized
fields.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 31 +--
1 file changed, 17 insertions(+), 14 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index ba4667b33c..d434c8545a 100644
.
Refer the Processor Programming Reference (PPR) documentation
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 195 -
1 file changed, 45 insertions
This reverts commit 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 37 +++--
2 files changed, 10 insertions
This reverts commit 6121c7fbfd98dbc3af1b00b56ff2eef66df87828.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |5 -
include/hw/i386/x86.h |9 -
2 files changed, 14 deletions(-)
diff --git a
This reverts commit dd08ef0318e2b61d14bc069590d174913f7f437a.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 161 ++---
1 file changed, 127 insertions(+), 34
This reverts commit 247b18c593ec298446645af8d5d28911daf653b1.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
target/i386/cpu.c |2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
This reverts commit c24a41bb53c0854d22c96b30d57cfcaa543c409d.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
hw/i386/x86.c |1 -
include/hw/i386/topology.h |1 -
target/i386
This reverts commit 0c1538cb1a26287c072645f4759b9872b1596d79.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 16
target/i386/cpu.h |1 -
2 files changed, 17 deletions(-)
diff --git a
qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.com
Babu Moger (10):
Revert "i386: Fix pkg_id offset for EPYC cpu models"
Revert "target/i386: Enable new apic id encoding for EPYC based cpus
models"
Revert "hw/i386: Move arch_id decode
This reverts commit 7568b20a6405042f62c64af3268f4330aed5.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 100
1 file changed, 100 deletions(-)
diff
This reverts commit 7b225762c8c05fd31d4c2be116aedfbc00383f8b.
Remove the EPYC specific apicid decoding and use the generic
default decoding.
Also fix all the references of pkg_offset.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
target/i386/cpu.c |9 -
target/i386
qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.com
Babu Moger (10):
Revert "i386: Fix pkg_id offset for EPYC cpu models"
Revert "target/i386: Enable new apic id encoding for EPYC based cpus
models"
Revert "hw/i386: Move arch_id decode
> -Original Message-
> From: Igor Mammedov
> Sent: Monday, August 31, 2020 2:51 AM
> To: Gerd Hoffmann
> Cc: qemu-devel@nongnu.org; Laurent Vivier ; Peter
> Maydell ; Thomas Huth ;
> Eduardo Habkost ; Sergio Lopez
> ; Michael S. Tsirkin ; Shannon Zhao
> ; qemu-...@nongnu.org; Paolo Bon
On 8/28/20 12:27 PM, Eduardo Habkost wrote:
> On Fri, Aug 21, 2020 at 05:13:03PM -0500, Babu Moger wrote:
>> Remove the EPYC specific apicid decoding and use the generic
>> default decoding.
>>
>> This reverts commit 7568b20a6405042f62c64af3268f4330aed5.
>
Responding to Eduardo's question. Some emails are not comming to my
mailbox for some reason. Responding git send-email --in-reply-to.
>> > > > I understood that each die in EPYC chip is a numa node, which encodes
>> > > > NUMA node ID (system wide) in CPUID_Fn801E_ECX, that's why I
>> > > > w
v5 0/8] Remove EPYC mode apicid decode and use
> generic decode
>
> On Thu, 27 Aug 2020 17:58:01 -0500
> Babu Moger wrote:
>
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Thursday, August 27, 2020 4:19 PM
> > > To: Dr. Dav
at.com; r...@twiddle.net
> Subject: Re: [PATCH v5 0/8] Remove EPYC mode apicid decode and use
> generic decode
>
> On Fri, 28 Aug 2020 09:58:03 +0100
> Daniel P. Berrangé wrote:
>
> > On Thu, Aug 27, 2020 at 10:21:10PM +0200, Igor Mammedov wrote:
> > > O
David Alan Gilbert" wrote:
> > >
> > > > * Igor Mammedov (imamm...@redhat.com) wrote:
> > > > > On Tue, 25 Aug 2020 09:15:04 +0100 "Dr. David Alan Gilbert"
> > > > > wrote:
> > > > >
> > > > > > *
at.com; r...@twiddle.net
> Subject: Re: [PATCH v5 0/8] Remove EPYC mode apicid decode and use generic
> decode
>
> * Babu Moger (babu.mo...@amd.com) wrote:
> >
> > > -Original Message-
> > > From: Igor Mammedov
> > > Sent: Wednesday, August 26, 2020
bject: Re: [PATCH v5 0/8] Remove EPYC mode apicid decode and use generic
> decode
>
> On Wed, 26 Aug 2020 13:50:59 +0100
> Daniel P. Berrangé wrote:
>
> > On Wed, Aug 26, 2020 at 02:38:49PM +0200, Igor Mammedov wrote:
> > > On Fri, 21 Aug 2020 17:12:19 -0500
> &g
On 8/26/20 4:57 AM, Igor Mammedov wrote:
> On Fri, 21 Aug 2020 17:12:25 -0500
> Babu Moger wrote:
>
>> Remove node_id, nr_nodes and nodes_per_pkg from topology. Use
>> die_id, nr_dies and dies_per_pkg which is already available.
>> Removes the confusion over two va
Hi Dave,
On 8/24/20 1:41 PM, Dr. David Alan Gilbert wrote:
> * Babu Moger (babu.mo...@amd.com) wrote:
>> To support some of the complex topology, we introduced EPYC mode apicid
>> decode.
>> But, EPYC mode decode is running into problems. Also it can become quite a
>>
t; from v1. Will send
it later.
v1:
https://lore.kernel.org/qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.com
Babu Moger (8):
hw/i386: Remove node_id, nr_nodes and nodes_per_pkg from topology
Revert "i386: Fix pkg_id offset for EPYC cpu models"
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 247b18c593ec298446645af8d5d28911daf653b1.
Signed-off-by: Babu Moger
---
target/i386/cpu.c |2 --
1 file changed, 2 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index
.
Refer the Processor Programming Reference (PPR) documentation
available from the bugzilla Link below.
Link: https://bugzilla.kernel.org/show_bug.cgi?id=206537
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 81 -
1 file changed, 37
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 7568b20a6405042f62c64af3268f4330aed5.
Signed-off-by: Babu Moger
---
include/hw/i386/topology.h | 79
target/i386/cpu.c |2 +
2
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 7b225762c8c05fd31d4c2be116aedfbc00383f8b.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
target/i386/cpu.c |6 +++---
target/i386/cpu.h |1 -
3 files changed, 3 insertions
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 0c1538cb1a26287c072645f4759b9872b1596d79.
Signed-off-by: Babu Moger
---
target/i386/cpu.c | 16
target/i386/cpu.h |1 -
2 files changed, 17 deletions(-)
diff --git a
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 2e26f4ab3bf8390a2677d3afd9b1a04f015d7721.
Signed-off-by: Babu Moger
---
hw/i386/pc.c |6 +++---
hw/i386/x86.c | 37 +++--
2 files changed, 10 insertions
Remove the EPYC specific apicid decoding and use the generic
default decoding.
This reverts commit 6121c7fbfd98dbc3af1b00b56ff2eef66df87828.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |5 -
include/hw/i386/x86.h |9 -
2 files changed, 14 deletions(-)
diff --git a
://bugzilla.redhat.com/show_bug.cgi?id=1828750
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
hw/i386/x86.c |1 -
include/hw/i386/topology.h | 40 +---
target/i386/cpu.c | 24 ++--
target/i386/cpu.h
On 8/20/20 7:57 AM, Igor Mammedov wrote:
> On Wed, 19 Aug 2020 17:42:58 -0500
> Babu Moger wrote:
>
>> On 8/19/20 7:18 AM, Igor Mammedov wrote:
>>> On Fri, 14 Aug 2020 16:39:40 -0500
>>> Babu Moger wrote:
>>>
>>>> Remove node_id, nr_
On 8/19/20 7:18 AM, Igor Mammedov wrote:
> On Fri, 14 Aug 2020 16:39:40 -0500
> Babu Moger wrote:
>
>> Remove node_id, nr_nodes and nodes_per_pkg from topology. Use
>> die_id, nr_dies and dies_per_pkg which is already available.
>> Removes the confusion over two va
2/3] hw/i386: Update the EPYC topology to use
> socket/dies/core/thread model
>
> On Fri, 14 Aug 2020 16:39:33 -0500
> Babu Moger wrote:
>
> > Update the EPYC topology to use socket/dies/core/thread model. The
> > EPYC model does not use the smp dies to build the topolo
Link below.
Signed-off-by: Babu Moger
Reviewed-by: Igor Mammedov
---
target/i386/cpu.c | 77 +
1 file changed, 36 insertions(+), 41 deletions(-)
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index 588f32e136..c892432cae 100644
--- a
://bugzilla.redhat.com/show_bug.cgi?id=1828750
Signed-off-by: Babu Moger
---
hw/i386/pc.c |1 -
hw/i386/x86.c |1 -
include/hw/i386/topology.h | 40 +---
target/i386/cpu.c | 11 +++
target/i386/cpu.h |1
later.
v1:
https://lore.kernel.org/qemu-devel/159164739269.20543.3074052993891532749.st...@naples-babu.amd.com
Babu Moger (3):
i386: Simplify CPUID_8000_001E for AMD
hw/i386: Update the EPYC topology to use socket/dies/core/thread model
hw/i386: Remove node_id, nr_nodes and nodes_pe
simple to program.
Add a new check to error out when smp dies are not provided when EPYC
model is numa configured. Next task is to remove node_id, nr_nodes and
nodes_per_pkg from EPYC topology which will be done in next patch.
Signed-off-by: Babu Moger
---
hw/i386/x86.c |8
1 file
2/3] hw/i386: Add a new check to configure smp dies for
> EPYC
>
> On Tue, 11 Aug 2020 16:03:58 -0500
> Babu Moger wrote:
>
> > On 8/7/20 2:11 PM, Igor Mammedov wrote:
> > > On Fri, 7 Aug 2020 17:52:22 +0100
> > > Daniel P. Berrangé wrote:
> >
On 8/7/20 2:11 PM, Igor Mammedov wrote:
> On Fri, 7 Aug 2020 17:52:22 +0100
> Daniel P. Berrangé wrote:
>
>> On Fri, Aug 07, 2020 at 11:32:51AM -0500, Babu Moger wrote:
>>> Adding a new check to warn the users to configure 'dies' when
>>> topology is
to configure smp dies for
> EPYC
>
> On Fri, 07 Aug 2020 11:32:51 -0500
> Babu Moger wrote:
>
> > Adding a new check to warn the users to configure 'dies' when
> s/warn .../error out .../
>
> > topology is numa configured. It makes it easy to build t
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