Hi Steve,
On Wed, Mar 13, 2019 at 10:11:30AM +, Steven Price wrote:
>
> Personally I think what we need is:
>
> * Either a patch like the one from Heyi Guo (save/restore CNTVCT_EL0) or
> alternatively hooking up KVM_KVMCLOCK_CTRL to prevent the watchdog
> firing when user space explicitly st
[Adding Steven Price, who has recently looked at this, in cc]
On Tue, Mar 12, 2019 at 10:08:47AM +, Peter Maydell wrote:
> On Tue, 12 Mar 2019 at 06:10, Heyi Guo wrote:
> >
> > When we stop a VM for more than 30 seconds and then resume it, by qemu
> > monitor command "stop" and "cont", Linux
Hi Manish,
On Sat, Nov 10, 2018 at 10:18:47PM +, Manish Jaggi wrote:
>
> CCing a larger audience.
> Please review.
>
> On 10/23/2018 03:51 PM, Jaggi, Manish wrote:
> > From: Manish Jaggi
> >
> > This patch introduces an error code KVM_EINVARIANT which is returned
> > by KVM when userland tr
On Fri, Nov 02, 2018 at 04:36:35PM +, Peter Maydell wrote:
> On 2 November 2018 at 14:54, Richard Henderson
> wrote:
> > My previous patch set for replacing feature bits with id registers
> > failed to consider that these id registers are beginning to control
> > migration, and thus we must fi
Hi Philippe,
On Mon, Feb 05, 2018 at 09:10:48PM -0300, Philippe Mathieu-Daudé wrote:
>
> On 02/01/2018 05:53 PM, Christoffer Dall wrote:
> > KVM doesn't support emulating a GICv3 in userspace, only GICv2. We
> > currently attempt this anyway, and as a result a KVM gu
KVM doesn't support emulating a GICv3 in userspace, only GICv2. We
currently attempt this anyway, and as a result a KVM guest doesn't
receive interrupts and the user is left wondering why. Report an error
to the user if this particular combination is requested.
Signed-off-by: Christ
On Thu, Feb 01, 2018 at 01:25:20PM +0100, Andrew Jones wrote:
> On Thu, Feb 01, 2018 at 11:48:31AM +0100, Christoffer Dall wrote:
> > On Thu, Feb 01, 2018 at 11:42:22AM +0100, Andrew Jones wrote:
> > > On Thu, Feb 01, 2018 at 10:59:54AM +0100, Christoffer Dall wrote:
> > &g
On Thu, Feb 01, 2018 at 11:42:22AM +0100, Andrew Jones wrote:
> On Thu, Feb 01, 2018 at 10:59:54AM +0100, Christoffer Dall wrote:
> > On Thu, Feb 1, 2018 at 10:33 AM, Ard Biesheuvel
> > wrote:
> > > On 1 February 2018 at 09:17, Christoffer Dall
> > > wrote:
>
On Thu, Feb 1, 2018 at 10:33 AM, Ard Biesheuvel
wrote:
> On 1 February 2018 at 09:17, Christoffer Dall
> wrote:
>> On Wed, Jan 31, 2018 at 9:15 PM, Ard Biesheuvel
>> wrote:
>>> On 31 January 2018 at 19:12, Christoffer Dall
>>> wrote:
>>>>
On Wed, Jan 31, 2018 at 9:15 PM, Ard Biesheuvel
wrote:
> On 31 January 2018 at 19:12, Christoffer Dall
> wrote:
>> On Wed, Jan 31, 2018 at 7:00 PM, Ard Biesheuvel
>> wrote:
>>> On 31 January 2018 at 17:39, Christoffer Dall
>>> wrote:
>>>>
On Wed, Jan 31, 2018 at 7:00 PM, Ard Biesheuvel
wrote:
> On 31 January 2018 at 17:39, Christoffer Dall
> wrote:
>> On Wed, Jan 31, 2018 at 5:59 PM, Ard Biesheuvel
>> wrote:
>>> On 31 January 2018 at 16:53, Christoffer Dall
>>> wrote:
>>>>
On Wed, Jan 31, 2018 at 5:59 PM, Ard Biesheuvel
wrote:
> On 31 January 2018 at 16:53, Christoffer Dall
> wrote:
>> On Wed, Jan 31, 2018 at 4:18 PM, Ard Biesheuvel
>> wrote:
>>> On 31 January 2018 at 09:53, Christoffer Dall
>>> wrote:
>>>> On Mon
On Wed, Jan 31, 2018 at 4:18 PM, Ard Biesheuvel
wrote:
> On 31 January 2018 at 09:53, Christoffer Dall
> wrote:
>> On Mon, Jan 29, 2018 at 10:32:12AM +, Marc Zyngier wrote:
>>> On 29/01/18 10:04, Peter Maydell wrote:
>>> > On 29 January 2018 at 09:53, Dr.
On Mon, Jan 29, 2018 at 10:32:12AM +, Marc Zyngier wrote:
> On 29/01/18 10:04, Peter Maydell wrote:
> > On 29 January 2018 at 09:53, Dr. David Alan Gilbert
> > wrote:
> >> * Peter Maydell (peter.mayd...@linaro.org) wrote:
> >>> On 26 January 2018 at 19:46, Dr. David Alan Gilbert
> >>> wrote
On Fri, Jul 21, 2017 at 01:35:46PM +0200, Andrew Jones wrote:
> On Fri, Jul 21, 2017 at 01:16:07PM +0200, Christoffer Dall wrote:
> > On Wed, Jul 19, 2017 at 09:39:54AM -0400, Andrew Jones wrote:
> > > Mimicking gicv3-maintenance-interrupt, add the PMU's inter
ver happen if KVM advertises the PMU capability, because both
> attrs have been available since the capability was introduced. Let's
> just abort if this should-never-happen stuff does happen, because,
> if it does, then something is obviously horribly wrong.
>
> Signed-off-by: Andrew
s
Reviewed-by: Christoffer Dall
> ---
> hw/arm/virt.c | 3 ++-
> target/arm/kvm.c | 6 +-
> target/arm/kvm64.c | 3 +--
> 3 files changed, 8 insertions(+), 4 deletions(-)
>
> diff --git a/hw/arm/virt.c b/hw/arm/virt.c
> index 7157a028adce..a215330444da 100644
>
ately.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Christoffer Dall
> ---
> hw/arm/virt.c| 11 +--
> target/arm/kvm32.c | 8 +++-
> target/arm/kvm64.c | 52
> +---
> target/arm/kvm_arm.h | 1
On Wed, Jul 19, 2017 at 09:39:54AM -0400, Andrew Jones wrote:
> Mimicking gicv3-maintenance-interrupt, add the PMU's interrupt to
> CPU state.
>
> Signed-off-by: Andrew Jones
> Reviewed-by: Peter Maydell
> ---
> hw/arm/virt.c| 3 +++
> target/arm/cpu.c | 2 ++
> target/arm/cpu.h | 2 ++
> 3
Hi all,
Linaro is looking for a full-time engineer to work on QEMU, primarily
focused on emulating aspects of the ARM architecture.
Feel free to apply to the position or forward this to anyone you know
who has experience working with QEMU and experience with modeling
computer architecture.
The o
On Sun, Apr 30, 2017 at 01:37:56PM +0800, Dongjiu Geng wrote:
> when SError happen, kvm notifies kvmtool to generate GHES table
> to record the error, then kvmtools inject the SError with specified
again, is this really specific to kvmtool? Pleae try to explain this
mechanism in generic terms.
>
Hi Dongjiu,
Please send a cover letter for patch series with more than a single
patch.
The subject and description of these patches are also misleading.
Hopefully this is in no way tied to kvmtool, but to userspace
generically, for example also to be used by QEMU?
On Sun, Apr 30, 2017 at 01:37:5
On Wed, Mar 29, 2017 at 01:51:19PM -0700, Radha Mohan wrote:
> On Wed, Mar 29, 2017 at 11:56 AM, Christoffer Dall wrote:
> > On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
> >> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
> >> > Hi Radha
On Tue, Mar 28, 2017 at 01:24:15PM -0700, Radha Mohan wrote:
> On Tue, Mar 28, 2017 at 1:16 PM, Christoffer Dall wrote:
> > Hi Radha,
> >
> > On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan wrote:
> >> Hi,
> >> I am seeing an issue with qemu-system-
On Wed, Mar 29, 2017 at 05:37:49PM +0200, Laszlo Ersek wrote:
> On 03/29/17 16:48, Christoffer Dall wrote:
> > On Wed, Mar 29, 2017 at 10:36:51PM +0800, gengdongjiu wrote:
> >> 2017-03-29 18:36 GMT+08:00, Achin Gupta :
>
> >>> Qemu is essentially fulfilling t
On Wed, Mar 29, 2017 at 10:36:51PM +0800, gengdongjiu wrote:
> Hi Achin,
> Thanks for your mail and answer.
>
> 2017-03-29 18:36 GMT+08:00, Achin Gupta :
> > Hi gengdongjiu,
> >
> > On Wed, Mar 29, 2017 at 05:36:37PM +0800, gengdongjiu wrote:
> >>
> >> Hi Laszlo/Biesheuvel/Qemu developer,
> >>
Hi Radha,
On Tue, Mar 28, 2017 at 12:58:24PM -0700, Radha Mohan wrote:
> Hi,
> I am seeing an issue with qemu-system-aarch64 when using pflash
> (booting kernel via UEFI bios).
>
> Host kernel: 4.11.0-rc3-next-20170323
> Qemu version: v2.9.0-rc1
>
> Command used:
> ./aarch64-softmmu/qemu-system-
On Thu, Feb 2, 2017 at 3:59 PM, Marc Zyngier wrote:
> [+Christoffer]
>
> Hi Pekka,
>
> On 02/02/17 14:44, Pekka Enberg wrote:
>> Hi,
>>
>> Has anyone been able to successfully run QEMU/KVM under Raspberry Pi 3?
>>
>> I have installed 64-bit Fedora 24 by Gerd Hoffmann on the hardware:
>>
>>http
On Fri, Dec 09, 2016 at 04:30:20PM +, Peter Maydell wrote:
> The architectural timers in ARM CPUs all have level triggered interrupts
> (unless you're using KVM on a host kernel before 4.4, which misimplemented
> them as edge-triggered).
>
> We were incorrectly describing them in the device tr
On Fri, Nov 25, 2016 at 02:12:12PM +0530, Vijay Kilari wrote:
> On Fri, Nov 25, 2016 at 1:27 PM, Auger Eric wrote:
> > Hi Vijay,
> >
> > On 23/11/2016 13:39, vijay.kil...@gmail.com wrote:
> >> From: Vijaya Kumar K
> >>
> >> This temporary patch adds kernel API definitions. Use proper header updat
On Wed, Nov 02, 2016 at 04:40:35PM +0100, Alexander Graf wrote:
> On 11/01/2016 12:35 PM, Peter Maydell wrote:
> >On 29 October 2016 at 22:10, Alexander Graf wrote:
[...]
> >
> >>+cpu->timer_irq_level = run->s.regs.timer_irq_level;
> >>+}
> >>+
> >> return MEMTXATTRS_UNSPECIFIED
On Tue, Jun 28, 2016 at 8:41 AM, Auger Eric wrote:
> Dear all,
>
> On 24/11/2015 11:13, Pavel Fedin wrote:
>> This series introduces support for in-kernel GICv3 ITS emulation.
>> It is based on kernel API which is not released yet, therefore i post
>> it as an RFC.
>>
>> Kernel patch sets which im
On Tue, May 24, 2016 at 02:23:43PM +0200, Andrew Jones wrote:
> On Tue, May 24, 2016 at 01:58:19PM +0200, Christoffer Dall wrote:
> > On Mon, May 23, 2016 at 05:24:23PM +0200, Andrew Jones wrote:
> > > On Wed, May 18, 2016 at 11:07:14AM +0200, Christoffer Dall wrot
On Mon, May 23, 2016 at 05:24:23PM +0200, Andrew Jones wrote:
> On Wed, May 18, 2016 at 11:07:14AM +0200, Christoffer Dall wrote:
> > Hi Drew,
> >
> > Thanks for doing this. I'm happy to see some tests for the GIC.
> >
> > I've been pondering wi
Hi Drew,
Thanks for doing this. I'm happy to see some tests for the GIC.
I've been pondering with how to write unit tests for all the MMIO
implementations. If you have some thoughts on how that could be easily
fitted into this framework, that would probably be a good place to do it
;)
-Christo
: Christoffer Dall
---
The first version of this patch was accidentally made against the v2.5.0
release instead of master, so this is a rebased version.
util/oslib-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index 20ca141..a0c5b91
: Christoffer Dall
---
util/oslib-posix.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/oslib-posix.c b/util/oslib-posix.c
index d25f671..03b055e 100644
--- a/util/oslib-posix.c
+++ b/util/oslib-posix.c
@@ -35,7 +35,7 @@
extern int daemon(int, int);
#endif
-#if defined
On Fri, Apr 22, 2016 at 11:17:47AM +0100, Peter Maydell wrote:
> On 22 April 2016 at 11:15, Christoffer Dall
> wrote:
> > Peter just pointed me to a change I remember doing for ARM, so perhaps
> > this fix is the right one?
> >
> >
> > diff --git a/uti
On Fri, Apr 22, 2016 at 12:06:52PM +0200, Alexander Graf wrote:
> On 04/22/2016 12:01 PM, Christoffer Dall wrote:
> >On Thu, Apr 21, 2016 at 09:50:05PM +0200, Alexander Graf wrote:
> >>
> >>On 21.04.16 18:23, Christoffer Dall wrote:
> >>>Hi,
> >>
Hi Laszlo,
On Thu, Apr 21, 2016 at 11:58:07PM +0200, Laszlo Ersek wrote:
> On 04/21/16 18:23, Christoffer Dall wrote:
> > Hi,
> >
> > Commit 9fac18f (oslib: allocate PROT_NONE pages on top of RAM,
> > 2015-09-10) had the unfortunate side effect that memory slots regist
On Thu, Apr 21, 2016 at 09:50:05PM +0200, Alexander Graf wrote:
>
>
> On 21.04.16 18:23, Christoffer Dall wrote:
> > Hi,
> >
> > Commit 9fac18f (oslib: allocate PROT_NONE pages on top of RAM,
> > 2015-09-10) had the unfortunate side effect that memory slots
Hi,
Commit 9fac18f (oslib: allocate PROT_NONE pages on top of RAM,
2015-09-10) had the unfortunate side effect that memory slots registered
with KVM no longer contain a userspace address that is aligned to a 2M
boundary, causing the use of THP to fail in the kernel.
I fail to see where in the QEM
Hi Peter,
Stupid question: The subject says "SMP command". Did you mean "QMP
command" ?
Thanks,
-Christoffer
On Wed, Mar 23, 2016 at 01:32:29PM +0800, Peter Xu wrote:
> v6 changes:
> - patch 1 (squashed into patch 2)
> - explain more about the following in commit message: why we need
> th
> /* Second PCIe window, 512GB wide at the 512GB boundary */
> > [VIRT_PCIE_MMIO_HIGH] = { 0x80ULL, 0x80ULL },
> > };
> > @@ -1066,7 +1083,7 @@ static void machvirt_init(MachineState *machine)
> > vbi->smp_cpus = smp_cpus;
> >
> > if (machine->ram_size > vbi->memmap[VIRT_MEM].size) {
> > -error_report("mach-virt: cannot model more than 30GB RAM");
> > +error_report("mach-virt: cannot model more than %dGB RAM",
> > RAMLIMIT_GB);
> > exit(1);
> > }
> >
> > --
> > 1.9.1
Reviewed-by: Christoffer Dall
On Tue, Feb 2, 2016 at 4:52 PM, Eric Blake wrote:
> On 02/02/2016 07:05 AM, Christoffer Dall wrote:
>
>>>
>>> I'm not familiar enough with libvirt, nor the use of QMP, to really argue
>>> one way or another, but I find it a bit strange that we'd prefer
On Tue, Feb 02, 2016 at 01:59:26PM +0100, Andrew Jones wrote:
> On Tue, Feb 02, 2016 at 12:10:10PM +, Daniel P. Berrange wrote:
> > On Tue, Feb 02, 2016 at 12:49:33PM +0100, Christoffer Dall wrote:
> > > On Fri, Jan 22, 2016 at 02:44:32PM +, Daniel P. Berrange wrote:
>
On Fri, Jan 22, 2016 at 02:44:32PM +, Daniel P. Berrange wrote:
> On Wed, Jan 06, 2016 at 01:30:16PM +, Peter Maydell wrote:
> > On 6 January 2016 at 12:49, Andrea Bolognani wrote:
> > > That's correct, having a QMP command that lists the values gic-version
> > > can have on the current ho
On Tue, Jan 19, 2016 at 01:37:16PM +0100, Andrew Jones wrote:
> On Tue, Jan 19, 2016 at 12:49:18PM +0100, Christoffer Dall wrote:
> > The virt board has an arch timer, which is always on. Emit the
> > "always-on" property to indicate to Linux that it can switch off t
The virt board has an arch timer, which is always on. Emit the
"always-on" property to indicate to Linux that it can switch off the
periodic timer and reduces the amount of interrupts injected into a
guest.
Signed-off-by: Christoffer Dall
---
hw/arm/virt.c | 1 +
1 file changed, 1
On Thu, Nov 19, 2015 at 11:44 PM, Alex Williamson
wrote:
> On Thu, 2015-11-19 at 15:22 +, Eric Auger wrote:
>> I am resending this RFC from Oct 12, after kernel 4.4-rc1 and
>> QEMU 2.5-rc1, hoping things have calmed down a little bit.
>>
>> This RFC allows to set up AMD XGBE passthrough. This
On Wed, Oct 07, 2015 at 09:02:47AM +0100, Peter Maydell wrote:
> On 7 October 2015 at 08:57, Pavel Fedin wrote:
> > Knock-knock!
> >
> > PM: I remember we had a talk that we should settle down on migration data
> > format. Isn't it right
> > time?
>
> I think Christoffer has a patchset which s
On Thu, Aug 27, 2015 at 10:23:38AM -0400, Christopher Covington wrote:
> On 07/24/2015 08:00 AM, Matt Ma wrote:
> > Hi all,
> >
> > Linaro has developed the foundation for the new Android Emulator code
> > base based on a fairly recent upstream QEMU code base, when we
> > re-based the code, we upd
On Tue, Aug 25, 2015 at 04:43:13PM +0100, Stefan Hajnoczi wrote:
> I have created a wiki page for virtio-vsock.
>
> It links to my git repos and the draft virtio specification:
> http://qemu-project.org/Features/VirtioVsock
>
> I'll expand and update it over the coming days and weeks.
>
> Please
On Wed, Aug 12, 2015 at 4:14 PM, Eric Auger wrote:
> Hi,
> On 08/12/2015 03:23 PM, Christoffer Dall wrote:
>> On Wed, Aug 12, 2015 at 2:59 PM, Peter Maydell
>> wrote:
>>> On 12 August 2015 at 13:27, Pavel Fedin wrote:
>>>> Hello!
>>>>
>&
On Wed, Aug 12, 2015 at 2:59 PM, Peter Maydell wrote:
> On 12 August 2015 at 13:27, Pavel Fedin wrote:
>> Hello!
>>
>>> I still think this is the wrong approach -- see my remarks
>>> in the previous round of patch review.
>>
>> You know... I thought a little bit...
>> So far, test = true in KV
On Wed, Aug 12, 2015 at 1:44 PM, Pavel Fedin wrote:
> Hello!
>
>> I still think this is the wrong approach -- see my remarks
>> in the previous round of patch review.
>
> Christoffer did not reply anything to your question back then. So - what to
> do? Probe for all possible GICs? Remove the pr
On Fri, Jul 17, 2015 at 03:29:56PM +0100, Peter Maydell wrote:
> On 16 July 2015 at 12:34, Christoffer Dall
> wrote:
> > Some registers like the CNTVCT register should only be written to the
> > kernel as part of machine initialization or on vmload operations, but
> >
that should not be written back at runtime
and check this list on syncing the register state to the KVM state.
Signed-off-by: Christoffer Dall
---
Changes since RFC:
- Move cpreg_level to kvm_arm_cpreg_level and into kvm32.c and kvm64.c
- Changed struct name and declare as static const
dtc
On Fri, Jul 10, 2015 at 12:22:31PM +0100, Peter Maydell wrote:
> On 10 July 2015 at 12:00, Christoffer Dall
> wrote:
> > Some registers like the CNTVCT register should only be written to the
> > kernel as part of machine initialization or on vmload operations, but
> >
that should not be written back at runtime
and check this list on syncing the register state to the KVM state.
Signed-off-by: Christoffer Dall
---
target-arm/kvm.c | 34 +-
target-arm/kvm32.c | 2 +-
target-arm/kvm64.c | 2 +-
target-arm/kvm_arm.h | 3
On Thu, Jul 9, 2015 at 6:28 PM, Peter Maydell wrote:
> On 9 July 2015 at 17:03, Christoffer Dall wrote:
>> [whoops, re-adding qemu-devel]
>>
>> On Thu, Jul 9, 2015 at 5:07 PM, Alexander Graf wrote:
>>> On 07/09/15 16:44, Christoffer Dall wrote:
>>>>
[whoops, re-adding qemu-devel]
On Thu, Jul 9, 2015 at 5:07 PM, Alexander Graf wrote:
> On 07/09/15 16:44, Christoffer Dall wrote:
>>
>> On Thu, Jul 09, 2015 at 04:02:14PM +0200, Claudio Fontana wrote:
>>>
>>> Hello Christoffer,
>>>
>>> just o
On Fri, Jul 3, 2015 at 10:47 AM, Pavel Fedin wrote:
> Hi!
>
>> Well, it can become a little messy for everyone if Shlomo is working
>> on refactoring and respinning his patches, and meanwhile new versions
>> of his patches go out embedded as part of another patch set
>
> Exactly for this reason
On Fri, Jul 3, 2015 at 8:52 AM, Pavel Fedin wrote:
> Hi!
>
>> I think you should leave out the software emulation part for this
>> series and let's concentrate on getting this in first.
>
> Ok.
>
>> Also, you should make sure you have an agreement with Shlomo about
>> taking over his patches bef
On Thu, Jul 2, 2015 at 5:30 PM, Pavel Fedin wrote:
>> We definitely need a single virt machine, not multiple machines. I
>> don't know enough about the QEMU internals as to how to accomplish
>> this in detail.
>
> Two beat one... Okay, i surrender. :)
> I will respin this, hopefully tomorrow. I
On Thu, Jul 2, 2015 at 4:47 PM, Pavel Fedin wrote:
> Hello!
>
> I already explained this earlier:
> http://lists.nongnu.org/archive/html/qemu-devel/2015-05/msg04842.html, and i
> tried to explain this in commit message. Current qemu architecture does not
> allow doing this in a clean way.
>
On Wed, Jul 01, 2015 at 02:14:55PM +0300, Pavel Fedin wrote:
> Hello!
>
> > I think it would be good if you could re-spin this series based on
> > Eric's comments on the code, my comments on the patch style, and Peter's
> > advise on using machine properties for GICv3.
>
> There was a discussion
Hi Pavel,
On Fri, May 22, 2015 at 07:57:13PM +0300, Pavel Fedin wrote:
> Hi!
>
> > Looks GICv3 common class currently miss this security_extn field +
> > parent_fiq so it does not compile without changes. Or did I miss something?
>
> Just throw this if(...) away. It's my fault. Actually i have
On Fri, May 22, 2015 at 01:58:40PM +0300, Pavel Fedin wrote:
> This is my alternative to Ashok's vGICv3 patch
> (https://lists.gnu.org/archive/html/qemu-devel/2015-05/msg03021.html), which
> i am currently working on. It addresses vGIC capability verification issue
> (kvm_irqchip_create() / kvm_ar
Hi Pavel,
Please get rid of the trailing colon in the subject message.
On Fri, May 22, 2015 at 01:58:43PM +0300, Pavel Fedin wrote:
> - Make use of kernel_irqchip_type in kvm_arch_irqchip_create()
> - Instantiate "kvm-arm-gicv3" class (not implemented yet) for GICv3 with KVM
> acceleration
I f
Missing commit text completely?
On Fri, May 22, 2015 at 01:58:42PM +0300, Pavel Fedin wrote:
> Signed-off-by: Pavel Fedin
> ---
> hw/arm/exynos4_boards.c | 1 +
> hw/arm/realview.c | 1 +
> hw/arm/vexpress.c | 1 +
> 3 files changed, 3 insertions(+)
>
> diff --git a/hw/arm/exynos4_b
On Fri, May 22, 2015 at 01:58:41PM +0300, Pavel Fedin wrote:
> This patch introduces kernel_irqchip_type member in Machine class. Currently
> it it used only by virt machine for its internal purposes, however in future
> it is to be passed to KVM in kvm_irqchip_create(). The variable is defined a
On Thu, Jun 25, 2015 at 10:06:20AM +0100, Peter Maydell wrote:
> On 25 June 2015 at 09:00, Christoffer Dall
> wrote:
> > Of course, KVM can deny an unsupported configuration, but I am wondering
> > if we really think anybody will care about the 'model such specific
> &
Hi,
[sorry for reviving this thread late]
On Tue, Jun 09, 2015 at 12:24:13PM +0100, Peter Maydell wrote:
> On 9 June 2015 at 11:52, Marc Zyngier wrote:
> > On 08/06/15 11:52, Peter Maydell wrote:
> >> On 8 June 2015 at 11:32, Igor Mammedov wrote:
> >>> On Thu, 4 Jun 2015 18:17:39 +0100
> >>> Pe
Add a GICv2m device to the virt board to enable MSIs on the generic PCI
host controller. We allocate 64 SPIs in the IRQ space for now (this can
be increased/decreased later) and map the GICv2m right after the GIC in
the memory map.
Reviewed-by: Eric Auger
Signed-off-by: Christoffer Dall
index
into our frame of SPIs.
When instantiating a GICv2m device, tell PCI that we have instantiated
something that can deal with MSIs. We rely on the board actually wiring
up the GICv2m to the PCI host controller.
Reviewed-by: Eric Auger
Signed-off-by: Christoffer Dall
---
Changes since v3:
-
verifying MSIs going through as
expected.
Rebased on target-arm.next, see the individual patches for detailed
changelogs.
Christoffer Dall (4):
target-arm: Add GIC phandle to VirtBoardInfo
arm_gicv2m: Add GICv2m widget to support MSIs
target-arm: Extend the gic node properties
target-ar
ed-by: Eric Auger
Reviewed-by: Peter Maydell
Signed-off-by: Christoffer Dall
---
Changes since v3:
- Added reviewed-by tag
Changes since v2:
- None
Changes since v1:
- Added reviewed-by tag
hw/arm/virt.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --
child of the gic node.
Note that we must also expand the irq-map to reference the gic with the
right address-cells as a consequence of this change.
Reviewed-by: Eric Auger
Suggested-by: Shanker Donthineni
Signed-off-by: Christoffer Dall
---
Changes since v3:
- Rewrote patch and changed
Hi Pavel,
On Mon, May 25, 2015 at 04:09:58PM +0300, Pavel Fedin wrote:
> Hello!
>
> > typedef struct MemMapEntry {
> > @@ -88,6 +90,7 @@ typedef struct VirtBoardInfo {
> > int fdt_size;
> > uint32_t clock_phandle;
> > uint32_t gic_phandle;
> > +uint32_t v2m_phandle;
> > } Vi
index
into our frame of SPIs.
When instantiating a GICv2m device, tell PCI that we have instantiated
something that can deal with MSIs. We rely on the board actually wiring
up the GICv2m to the PCI host controller.
Signed-off-by: Christoffer Dall
---
Changes since v2:
- Renamed QOM type to "
to add the
v2m node as a child of the gic node.
Note that we must also expand the irq-map to reference the gic with the
right address-cells as a consequnce of this change.
Signed-off-by: Shanker Donthineni
Signed-off-by: Christoffer Dall
---
Changes since v2:
- New separate patch factoring out
Add a GICv2m device to the virt board to enable MSIs on the generic PCI
host controller. We allocate 64 SPIs in the IRQ space for now (this can
be increased/decreased later) and map the GICv2m right after the GIC in
the memory map.
Signed-off-by: Christoffer Dall
---
Changes since v2
ed-by: Peter Maydell
Signed-off-by: Christoffer Dall
---
Changes since v2:
- None
Changes since v1:
- Added reviewed-by tag
hw/arm/virt.c | 26 +++---
1 file changed, 11 insertions(+), 15 deletions(-)
diff --git a/hw/arm/virt.c b/hw/arm/virt.c
index a7f9a10..f9f7482 100644
---
verifying MSIs going through as
expected.
See the individual patches for changelogs.
Christoffer Dall (3):
target-arm: Add GIC phandle to VirtBoardInfo
arm_gicv2m: Add GICv2m widget to support MSIs
target-arm: Add the GICv2m to the virt board
Shanker Donthineni (1):
target-arm: Extend th
On Wed, May 06, 2015 at 05:39:28PM +0100, Peter Maydell wrote:
> On 6 May 2015 at 17:33, Peter Maydell wrote:
> > On 27 April 2015 at 18:31, Christoffer Dall
> > wrote:
> >> Now when we have a host generic PCIe controller in the virt board, it
> >> would be ni
On Tue, May 19, 2015 at 12:18:54PM +0100, Catalin Marinas wrote:
> On Tue, May 19, 2015 at 11:03:22AM +0100, Andrew Jones wrote:
> > On Mon, May 18, 2015 at 04:53:03PM +0100, Catalin Marinas wrote:
> > > Another way would be to split the vma containing the non-cacheable
> > > memory so that you get
On Fri, May 15, 2015 at 01:43:57PM +0200, Laszlo Ersek wrote:
> On 05/07/15 19:01, Paolo Bonzini wrote:
> >
> >
> > On 07/05/2015 18:56, Jérémy Fanguède wrote:
> >> USB devices fail with a timeout error, as if the communication between
> >> the kernel and the devices fail at a certain point:
> >>
On Thu, May 14, 2015 at 03:36:37PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 02:11:59PM +0100, Peter Maydell wrote:
> > On 14 May 2015 at 14:03, Andrew Jones wrote:
> > > On Thu, May 14, 2015 at 11:37:46AM +0100, Peter Maydell wrote:
> > >> On 14 May 2015 at 11:31, Andrew Jones wrote:
On Thu, May 14, 2015 at 03:32:13PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 12:55:49PM +0200, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
> > > When S1 and S2 memory attributes combine wrt to caching policy,
> > &g
On Thu, May 14, 2015 at 03:46:44PM +0200, Andrew Jones wrote:
> On Thu, May 14, 2015 at 01:05:09PM +0200, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
> > > Provide a method to change normal, cacheable memory to non-cacheable.
> >
On Thu, May 14, 2015 at 02:28:49PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 14:24, Christoffer Dall wrote:
> > On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
> >>
> >>
> >> On 14/05/2015 14:00, Christoffer Dall wrote:
> >>
On Thu, May 14, 2015 at 02:08:49PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 14:00, Christoffer Dall wrote:
> > So, getting back to my original question. Is the point then that UEFI
> > must assume (from ACPI/DT) the cache-coherency properties of the PCI
> >
On Thu, May 14, 2015 at 01:38:38PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 13:36, Christoffer Dall wrote:
> > > > > (It's probably worth looking at the documentation in the first hunk
> > > > > too,
> > > > > under the commi
On Thu, May 14, 2015 at 01:31:03PM +0200, Paolo Bonzini wrote:
>
>
> On 14/05/2015 13:29, Christoffer Dall wrote:
> > > (It's probably worth looking at the documentation in the first hunk too,
> > > under the commit message.)
> >
> > Why is this a hac
On Thu, May 14, 2015 at 01:09:34PM +0200, Laszlo Ersek wrote:
> On 05/14/15 12:30, Christoffer Dall wrote:
> > On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
> >> Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
> >> needed by ARM. This flag
On Wed, May 13, 2015 at 01:31:52PM +0200, Andrew Jones wrote:
> Provide a method to change normal, cacheable memory to non-cacheable.
> KVM will make use of this to keep emulated device memory regions
> coherent with the guest.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Christo
On Wed, May 13, 2015 at 01:31:54PM +0200, Andrew Jones wrote:
> When S1 and S2 memory attributes combine wrt to caching policy,
> non-cacheable types take precedence. If a guest maps a region as
> device memory, which KVM userspace is using to emulate the device
> using normal, cacheable memory, th
VM userspace access to it so that it may use it for hinting
> likely problematic regions. Also rename to KVM_MEM_UNCACHED.
>
> Signed-off-by: Andrew Jones
Reviewed-by: Christoffer Dall
On Wed, May 13, 2015 at 01:31:51PM +0200, Andrew Jones wrote:
> Introduce a new memory region flag, KVM_MEM_UNCACHED, which is
> needed by ARM. This flag informs KVM that the given memory region
> is typically mapped by the guest as non-cacheable. KVM for ARM
> then ensures that that memory is inde
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