[PATCH v2] target/riscv: Prevent lost illegal instruction exceptions

instructions instead of raising an illegal instruction exception. Instead of patching decode_RV32_64C(), we can just remove it, as it is dead code since f330433b363 anyway. Signed-off-by: Georg Kotheimer --- target/riscv/translate.c | 179 +-- 1 file changed, 1

[PATCH v2] target/riscv: Add proper two-stage lookup exception detection

translation was active when the exception was raised. However, in riscv_cpu_do_interrupt we do not have the information to reliably detect this. Therefore, when we raise a memory fault exception we have to record whether two-stage address translation is active. Signed-off-by: Georg Kotheimer

[PATCH] target/riscv: Prevent lost illegal instruction exceptions

instructions instead of raising an illegal instruction exception. Signed-off-by: Georg Kotheimer --- target/riscv/translate.c | 19 --- 1 file changed, 12 insertions(+), 7 deletions(-) diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 0f28b5f41e..8c00734252 100644

[PATCH] target/riscv: Use background registers also for MSTATUS_MPV

The current condition for the use of background registers only considers the hypervisor load and store instructions, but not accesses from M mode via MSTATUS_MPRV+MPV. Signed-off-by: Georg Kotheimer --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git

[PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions

According to the specification the "field SPVP of hstatus controls the privilege level of the access" for the hypervisor virtual-machine load and store instructions HLV, HLVX and HSV. Signed-off-by: Georg Kotheimer --- target/riscv/cpu_helper.c | 25 ++--- 1 file c

[PATCH] target/riscv: Add proper two-stage lookup exception detection

translation was active when the exception was raised. However, in riscv_cpu_do_interrupt we do not have the information to reliably detect this. Therefore, when we raise a memory fault exception we have to record whether two-stage address translation is active. Signed-off-by: Georg Kotheimer

[PATCH] target/riscv: Make VSTIP and VSEIP read-only in hip

Signed-off-by: Georg Kotheimer --- target/riscv/csr.c | 7 --- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/target/riscv/csr.c b/target/riscv/csr.c index fd2e6363f3..00a3ab72af 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -420,7 +420,8 @@ static const

[PATCH] target/riscv: Fix read and write accesses to vsip and vsie

The previous implementation was broken in many ways: - Used mideleg instead of hideleg to mask accesses - Used MIP_VSSIP instead of VS_MODE_INTERRUPTS to mask writes to vsie - Did not shift between S bits and VS bits (VSEIP <-> SEIP, ...) Signed-off-by: Georg Kotheimer --- target/riscv

[PATCH] target/riscv: Adjust privilege level for HLV(X)/HSV instructions

whether we are currently executing a hypervisor virtual-macine load or store instruction. Signed-off-by: Georg Kotheimer --- target/riscv/cpu.h| 2 ++ target/riscv/cpu_bits.h | 1 + target/riscv/cpu_helper.c | 60 ++- target/riscv/op_helper.c |

[PATCH] target/riscv: Fix update of hstatus.GVA in riscv_cpu_do_interrupt

The hstatus.GVA bit was not set if the faulting guest virtual address was zero. Signed-off-by: Georg Kotheimer --- target/riscv/cpu_helper.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 904899054d..c5852ce1b7

[PATCH] target/riscv: Fix implementation of HLVX.WU instruction

The HLVX.WU instruction is supposed to read a machine word, but prior to this change it read a byte instead. Signed-off-by: Georg Kotheimer --- target/riscv/op_helper.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c

[PATCH] target/riscv: Fix update of hstatus.SPVP

-off-by: Georg Kotheimer --- target/riscv/cpu_helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 904899054d..1d7d10377d 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -932,7 +932,7 @@ void

Re: [Qemu-devel] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions

On Tuesday, 20 August 2019 22:06:51 CEST Jim Wilson wrote: > The current XML files were identical to the XML files in gdb when > implemented. This seems to be existing practice, as this is true of all > of the other targets I looked at when I implemented this. Also, the > file names are the same

[Qemu-devel] [PATCH v3] RISC-V: Select FPU gdb xml file based on the supported extensions

to riscv_gdb_get_fpu() and riscv_gdb_set_fpu() were necessary. Signed-off-by: Georg Kotheimer --- configure | 4 ++-- target/riscv/gdbstub.c | 45 -- 2 files changed, 28 insertions(+), 21 deletions(-) diff --git a/configure b/configure index

[Qemu-devel] [PATCH v2] RISC-V: Select FPU gdb xml file based on the supported extensions

to riscv_gdb_get_fpu() and riscv_gdb_set_fpu() were necessary. In addition fflags, frm and fcsr were removed from riscv-XXbit-csr.xml, as the floating point csr registers are only available, if a FPU is present. Signed-off-by: Georg Kotheimer --- configure | 4

Re: [Qemu-devel] [PATCH] RISC-V: Select FPU gdb xml file based on the supported extensions

> While this appears reasonable, I wonder if RVF w/o RVD actually works? > > Examining the two get/set functions, they always transfer 64 bits for the fpu > registers. Wouldn't that implicate that FPU debugging has never been working properly on RV32, as prior to my changes the FPU registers on

[Qemu-devel] [PATCH] RISC-V: Select FPU gdb xml file based on the supported extensions

The size of the FPU registers depends solely on the floating point extensions supported by the target architecture. However, in the previous implementation the floating point register size was derived from whether the target architecture is 32-bit or 64-bit. Signed-off-by: Georg Kotheimer