On 5/30/24 12:18, Aditya Gupta wrote:
Hello Harsh,
On Thu, May 30, 2024 at 10:57:31AM GMT, Harsh Prateek Bora wrote:
Hi Aditya,
On 5/28/24 12:35, Aditya Gupta wrote:
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions
---
docs/about/removed-features.rst | 9 +
qapi/machine.json | 28
hw/acpi/memory_hotplug.c| 8
hw/ppc/spapr.c | 11 +--
5 files changed, 10 insertions(+), 51 deletions(-)
For spapr:
Reviewed-by: Har
On 5/28/24 12:35, Aditya Gupta wrote:
Add sPAPR CPU Core definition for Power11
Cc: David Gibson (reviewer:sPAPR (pseries))
Cc: Harsh Prateek Bora (reviewer:sPAPR (pseries))
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc: Madhavan
Hi Aditya,
On 5/28/24 12:35, Aditya Gupta wrote:
Add CPU target code to add support for new Power11 Processor.
Power11 core is same as Power10, hence reuse functions defined for
Power10.
Cc: Cédric Le Goater
Cc: Daniel Henrique Barboza
Cc: Frédéric Barrat
Cc: Mahesh J Salgaonkar
Cc:
here and we have a
different patch series (ppc64 vcpu hotplug failure fixes) depending on
this patch as well, it will be nice to see this patch getting merged
soon.
Reviewed-by: Harsh Prateek Bora
diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c
index c0be9f5eed..8f9128bb92 100644
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
POWER9 and POWER10 machines come in two variants, "big-core" and
"small-core".
Big core machines are SMT8 from the software point of view, but in the
low level platform topology ("xscom registers and pervasive
addressing"), these look more like
on below as well,
we may probably want to introduce another macro PPC_CPU_HAS_SINGLE_CORE
which checks only for nr_threads == 1. Anyways,
Reviewed-by: Harsh Prateek Bora
ppc_set_irq(cpu, PPC_INTERRUPT_HDOORBELL, 1);
return;
}
@@ -3067,21 +3067,19 @@ void helper_book3s_msg
corrected typo, it's bitwise.
On 5/28/24 14:18, Harsh Prateek Bora wrote:
- (POWERPC_CPU(cs)->env.spr_cb[SPR_PIR].default_value &
~(cs->nr_threads - 1))
+ (POWERPC_CPU(cs)->env.core_index)
Dont we want to keep the bitwise & with ~(cs->nr_threads - 1) ?
How's it taken care ?
On 5/26/24 17:56, Nicholas Piggin wrote:
The way SMT thread siblings are matched is clunky, using hard-coded
logic that checks the PIR SPR.
Change that to use a new core_index variable in the CPUPPCState,
where all siblings have the same core_index. CPU realize routines have
flexibility in
On 5/26/24 17:56, Nicholas Piggin wrote:
The chip_pir chip class method allows the platform to set the PIR
processor identification register. Extend this to a more general
ID function which also allows the TIR to be set. This is in
preparation for "big core", which is a more complicated
8) {
+error_report("Cannot support more than 8 threads/core "
+ "on a powernv POWER8 machine");
We could use mc->desc for machine name above, so that ..
+exit(1);
+}
with this patch, we can reuse p8 init for both p9 and p10 (and not just
reuse p9 for p10
Hi Nick,
On 5/26/24 17:56, Nicholas Piggin wrote:
SPRC/SPRD were recently added to all BookS CPUs supported, but
they are only tested on POWER9 and POWER10, so restrict them to
those CPUs.
Hope you mean to restrict to P9/10 for both spapr and pnv or just pnv ?
SPR indirect scratch
RMWARE_CONTROL_ERROR;
-env->pnv_tod_tbst.tb_ready_for_tod = 0;
+pnv_tod_tbst->tb_ready_for_tod = 0;
}
}
@@ -361,6 +371,8 @@ target_ulong helper_load_tfmr(CPUPPCState *env)
void helper_store_tfmr(CPUPPCState *env, target_ulong val)
{
+Pow
might be more intuitive with the most of its usage,
although I see few usage as "pnv_core" as well.
Reviewed-by: Harsh Prateek Bora
Object *intc;
} PnvCPUState;
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index f40ab721d6..7b0ea7812b 100644
--- a/hw/ppc/pnv_core.c
++
Signed-off-by: Harsh Prateek Bora
---
include/exec/cpu-common.h | 2 ++
cpu-common.c | 7 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6d5318895a..0386f1ab29 100644
--- a/include/exec/cpu-common.h
with kvm_create_vcpu at an early stage.
Based on api refactoring to create/park vcpus introduced in 1/8 of patch series:
https://lore.kernel.org/qemu-devel/2024052221.232114-1-salil.me...@huawei.com/
Suggested-by: Nicholas Piggin
Signed-off-by: Harsh Prateek Bora
---
accel/kvm/kvm-cpus.h | 8
v2: Addressed review comments from Nick
v1: Initial patch
Harsh Prateek Bora (3):
accel/kvm: Introduce kvm_create_and_park_vcpu() helper
cpu-common.c: export cpu_get_free_index to be reused later
target/ppc: handle vcpu hotplug failure gracefully
accel/kvm/kvm-cpus.h | 8
hotplug 40
#virsh setvcpus hotplug 70
error: internal error: unable to execute QEMU command 'device_add':
kvmppc_cpu_realize: vcpu hotplug failed with -12
Reported-by: Anushree Mathur
Suggested-by: Shivaprasad G Bhat
Suggested-by: Vaibhav Jain
Signed-off by: Harsh Prateek Bora
Tested
Hi Salil,
On 5/23/24 02:41, Salil Mehta wrote:
+void kvm_park_vcpu(CPUState *cpu);
+
+/**
+ * kvm_unpark_vcpu - unpark QEMU KVM vCPU context
+ * @s: KVM State
+ * @cpu: Architecture vCPU ID of the parked vCPU
s/@cpu/@vcpuid ?
Thanks
Harsh
+ *
+ * @returns: KVM fd
+ */
+int
The second if-condition can be true only if the first one above is true.
Enclose the latter into the former to avoid un-necessary check if first
condition fails.
Signed-off-by: Harsh Prateek Bora
Reviewed-by: BALATON Zoltan
---
target/ppc/helper_regs.c | 6 +++---
1 file changed, 3 insertions
Hi BALATON,
On 5/20/24 17:22, BALATON Zoltan wrote:
On Mon, 20 May 2024, Harsh Prateek Bora wrote:
Power9/10 initialization code consists of a lot of logical OR of
various flag bits as supported by respective Power platform during its
initialization, most of which is duplicated and only
Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple
conditions to avoid multiple indirect accesses.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/helper_regs.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/helper_regs.c b/tar
Historically, the registration of sprs have been inherited alongwith
every new Power arch support being added leading to a lot of code
duplication. It's time to do necessary cleanups now to avoid further
duplication with newer arch support being added.
Signed-off-by: Harsh Prateek Bora
code and share using common macros.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/cpu_init.h | 77 ++
target/ppc/cpu_init.c | 123 ++
2 files changed, 92 insertions(+), 108 deletions(-)
create mode 100644 target/ppc/cpu_init.h
Prateek Bora (7):
target/ppc: use locally stored msr and avoid indirect access
target/ppc: optimize hreg_compute_pmu_hflags_value
target/ppc: optimize hreg_compute_pmu_hflags_value
target/ppc: optimize p9 exception handling routines
target/ppc: optimize p9 exception handling routines for lpcr
Currently, p9 exception handling has multiple if-condition checks where
it does an indirect access to pending_interrupts via env. Pass the
value during entry to avoid multiple indirect accesses.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 47
Like pending_interrupts, env->spr[SPR_LPCR] is being used at multiple
places across p9 exception handlers. Pass the value during entry and
avoid multiple indirect accesses.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 33 ++---
1 file changed,
hreg_compute_hflags_value already stores msr locally to be used in most
of the logic in the routine however some instances are still using
env->msr which is unnecessary. Use locally stored value as available.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/helper_regs.c | 4 ++--
1 f
code and share using common macros.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/cpu_init.h | 79 +++
target/ppc/cpu_init.c | 123 ++
2 files changed, 94 insertions(+), 108 deletions(-)
create mode 100644 target/ppc/cpu_init.h
The second if-condition can be true only if the first one above is true.
Enclose the latter into the former to avoid un-necessary check if first
condition fails.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/helper_regs.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff
Currently, p9 exception handling has multiple if-condition checks where
it does an indirect access to pending_interrupts via env. Cache the
value during entry and reuse later to avoid multiple indirect accesses.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 39
Cache env->spr[SPR_POWER_MMCR0] in a local variable as used in multiple
conditions to avoid multiple indirect accesses.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/helper_regs.c | 9 +
1 file changed, 5 insertions(+), 4 deletions(-)
diff --git a/target/ppc/helper_regs.c b/tar
hreg_compute_hflags_value already stores msr locally to be used in most
of the logic in the routine however some instances are still using
env->msr which is unnecessary. Use locally stored value as available.
Signed-off-by: Harsh Prateek Bora
---
target/ppc/helper_regs.c | 4 ++--
1 f
This a set of misc ppc arch specific code improvements/optimizations.
Although there exists similar instances for potential improvements in
the legacy ppc code, however, that can be taken up later as well.
Harsh Prateek Bora (6):
target/ppc: use locally stored msr and avoid indirect access
Historically, the registration of sprs have been inherited alongwith
every new Power arch support being added leading to a lot of code
duplication. It's time to do necessary cleanups now to avoid further
duplication with newer arch support being added.
Signed-off-by: Harsh Prateek Bora
On 5/17/24 09:30, Nicholas Piggin wrote:
On Thu May 16, 2024 at 2:31 PM AEST, Harsh Prateek Bora wrote:
Hi Nick,
On 5/14/24 08:39, Nicholas Piggin wrote:
On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
+ qemu-devel
On 4/23/24 11:40, Harsh Prateek Bora wrote:
On ppc64
-by: Harsh Prateek Bora
---
hw/ppc/spapr.c | 27 +++
1 file changed, 27 insertions(+)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 611a9e5184..6891d91e6e 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -353,6 +353,31 @@ static void spapr_dt_pa_features
Hi Salil,
On 5/16/24 19:05, Salil Mehta wrote:
From: Harsh Prateek Bora
Sent: Thursday, May 16, 2024 2:07 PM
Hi Salil,
On 5/16/24 17:42, Salil Mehta wrote:
> Hi Harsh,
>
>> From: Harsh Prateek Bora
>> Sent: Thursday, May 16, 2024 11:15 AM
Hi Salil,
On 5/16/24 17:42, Salil Mehta wrote:
Hi Harsh,
From: Harsh Prateek Bora
Sent: Thursday, May 16, 2024 11:15 AM
Hi Salil,
Thanks for your email.
Your patch 1/8 is included here based on review comments on my previous
patch from one of the maintainers
is part of and you can rebase your patch-set from there. I'm
hopeful that it will get accepted in this cycle.
Many thanks
Salil.
From: Harsh Prateek Bora
Sent: Thursday, May 16, 2024 6:32 AM
From: Salil Mehta
KVM vCPU creation is done once during the vCPU realization when Qemu
vCPU
with kvm_create_vcpu at an early stage.
Based on api refactoring to create/park vcpus introduced in 1/8 of patch series:
https://lore.kernel.org/qemu-devel/2024031202.12992-2-salil.me...@huawei.com/
Suggested-by: Nicholas Piggin
Signed-off-by: Harsh Prateek Bora
---
include/sysemu/kvm.h | 8
accel
Signed-off-by: Harsh Prateek Bora
---
include/exec/cpu-common.h | 2 ++
cpu-common.c | 7 ---
2 files changed, 6 insertions(+), 3 deletions(-)
diff --git a/include/exec/cpu-common.h b/include/exec/cpu-common.h
index 6d5318895a..0386f1ab29 100644
--- a/include/exec/cpu-common.h
]
Signed-off-by: Harsh Prateek Bora
---
include/sysemu/kvm.h | 15 ++
accel/kvm/kvm-all.c| 64 --
accel/kvm/trace-events | 5 +++-
3 files changed, 68 insertions(+), 16 deletions(-)
diff --git a/include/sysemu/kvm.h b/include/sysemu/kvm.h
index
-by: Shivaprasad G Bhat
Suggested-by: Vaibhav Jain
Signed-off by: Harsh Prateek Bora
Tested-by: Anushree Mathur
---
target/ppc/kvm.c | 24
1 file changed, 24 insertions(+)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 63930d4a77..25f0cf0ba8 100644
--- a/target/ppc/kvm.c
with this series for better review purpose only.
Changelog:
v2: Addressed review comments from Nick
v1: Initial patch
Harsh Prateek Bora (3):
accel/kvm: Introduce kvm_create_and_park_vcpu() helper
cpu-common.c: export cpu_get_free_index to be reused later
target/ppc: handle vcpu hotplug failure
Hi Nick,
On 5/14/24 08:39, Nicholas Piggin wrote:
On Tue Apr 23, 2024 at 4:30 PM AEST, Harsh Prateek Bora wrote:
+ qemu-devel
On 4/23/24 11:40, Harsh Prateek Bora wrote:
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl
pport for
H_SET_MODE hcall")
Signed-off-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h | 1 +
hw/ppc/spapr.c | 1 +
hw/ppc/spapr_caps.c| 1 +
3 files changed, 3 insertions(+)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spa
-26bbaa627...@linux.ibm.com/T/#u
On 3/22/24 13:45, Harsh Prateek Bora wrote:
+ Vaibhav, Shiva
Hi Salil,
I came across your patch while trying to solve a related problem on
spapr. One query below ..
On 3/12/24 07:29, Salil Mehta via wrote:
KVM vCPU creation is done once during the vCPU realization
+ qemu-devel
On 4/23/24 11:40, Harsh Prateek Bora wrote:
On ppc64, the PowerVM hypervisor runs with limited memory and a VCPU
creation during hotplug may fail during kvm_ioctl for KVM_CREATE_VCPU,
leading to termination of guest since errp is set to _fatal while
calling kvm_init_vcpu
cel/tcg/translator.c | 1 +
hw/arm/boot.c | 1 +
hw/arm/npcm7xx.c| 1 +
hw/mips/fuloong2e.c | 1 +
hw/mips/malta.c | 1 +
hw/ppc/sam460ex.c | 1 +
hw/ppc/spapr.c | 1 +
For spapr:
Reviewed-by: Harsh Prateek Bora
h
RIx, start);
^
1 warning generated.
Signed-off-by: Philippe Mathieu-Daudé
With the typo fixed,
Reviewed-by: Harsh Prateek Bora
---
hw/ppc/spapr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index e9bc97fee0..9e97992c79 100644
--- a/hw/p
Check for flag bit in H_GUEST_GETSET_STATE_FLAG_GUEST_WIDE need to use
bitwise NOT operator to ensure no other flag bits are set.
Reported by Coverity as CID 1540008, 1540009.
Reported-by: Peter Maydell
Signed-off by: Harsh Prateek Bora
---
hw/ppc/spapr_nested.c | 2 +-
1 file changed, 1
On 3/28/24 20:55, Peter Maydell wrote:
On Wed, 27 Mar 2024 at 05:41, Harsh Prateek Bora wrote:
On 3/26/24 21:32, Peter Maydell wrote:
On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin wrote:
From: Harsh Prateek Bora
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which
On 3/26/24 21:32, Peter Maydell wrote:
On Tue, 12 Mar 2024 at 17:11, Nicholas Piggin wrote:
From: Harsh Prateek Bora
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which is used to get state of a nested guest or
a guest VCPU. The value field for each element
On 3/25/24 19:44, Paolo Bonzini wrote:
Add 9.1 machine types for arm/i440fx/m68k/q35/s390x/spapr.
Cc: Cornelia Huck
Cc: Thomas Huth
Cc: Harsh Prateek Bora
Cc: Gavin Shan
Signed-off-by: Paolo Bonzini
---
include/hw/boards.h| 3 +++
include/hw/i386/pc.h | 3 +++
hw/arm
d later do not support implicit function declarations
[-Wimplicit-function-declaration]
if (tcg_enabled()) {
^
Signed-off-by: Philippe Mathieu-Daudé
Reviewed-by: Harsh Prateek Bora
---
hw/ppc/spapr.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/ppc/spapr.c b/hw/p
event supervisor from modifying MSR[ME]")
Signed-off-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
---
target/ppc/excp_helper.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 80f584f933..674c05a
+ Vaibhav, Shiva
Hi Salil,
I came across your patch while trying to solve a related problem on
spapr. One query below ..
On 3/12/24 07:29, Salil Mehta via wrote:
KVM vCPU creation is done once during the vCPU realization when Qemu vCPU thread
is spawned. This is common to all the
On 3/12/24 18:44, Nicholas Piggin wrote:
Copy the pa-features arrays from spapr, adjusting slightly as
described in comments.
Signed-off-by: Nicholas Piggin
Although future re-org is expected per discussion on v1, but for now:
Reviewed-by: Harsh Prateek Bora
---
hw/ppc/pnv.c | 67
On 3/12/24 18:44, Nicholas Piggin wrote:
This allows different pa-features for powernv8/9/10.
Signed-off-by: Nicholas Piggin
Reviewed-by: Harsh Prateek Bora
---
hw/ppc/pnv.c | 41 +
1 file changed, 29 insertions(+), 12 deletions(-)
diff --git
Hi Nick,
Updated incremental fix below:
On 3/12/24 18:21, Harsh Prateek Bora wrote:
On 3/12/24 18:17, Harsh Prateek Bora wrote:
Hi Nick,
On 3/12/24 17:41, Harsh Prateek Bora wrote:
Hi Nick,
On 3/12/24 17:21, Nicholas Piggin wrote:
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora
On 3/12/24 18:17, Harsh Prateek Bora wrote:
Hi Nick,
On 3/12/24 17:41, Harsh Prateek Bora wrote:
Hi Nick,
On 3/12/24 17:21, Nicholas Piggin wrote:
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API
Hi Nick,
On 3/12/24 17:41, Harsh Prateek Bora wrote:
Hi Nick,
On 3/12/24 17:21, Nicholas Piggin wrote:
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API for nested guests. This new API is to enable support
Hi Nick,
On 3/12/24 17:21, Nicholas Piggin wrote:
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API for nested guests. This new API is to enable support for KVM on PowerVM
and the support in Linux kernel has
On 3/12/24 17:11, Nicholas Piggin wrote:
On Fri Mar 8, 2024 at 9:19 PM AEST, Harsh Prateek Bora wrote:
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() via
helper.
Signed-off-by: Michael Neuling
Signed
;msr & (1 << MSR_ME);
+}
Reviewed-by: Harsh Prateek Bora
if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
cpu_interrupt_exittb(cs);
}
On 3/12/24 00:21, Nicholas Piggin wrote:
The initial MSR state for PAPR specifies MSR[ME] and MSR[FP] are set.
Signed-off-by: Nicholas Piggin
It would be good to mention PAPR section numbers suggesting the same.
Anyways,
Reviewed-by: Harsh Prateek Bora
---
hw/ppc/spapr_cpu_core.c
support needed, instead of having local arrays bloat this
routine.
For now, with cosmetic fixes,
Reviewed-by: Harsh Prateek Bora
@@ -280,6 +310,10 @@ static void spapr_dt_pa_features(SpaprMachineState *spapr,
pa_features = pa_features_300;
pa_size = sizeof(pa_features_300
On 3/12/24 00:21, Nicholas Piggin wrote:
"MMR" and "SPR SO" are not implemented in POWER9, so clear those bits.
HTM is not set by default, and only later if the cap is set, so remove
the comment that suggests otherwise.
Signed-off-by: Nicholas Piggin
Reviewed-by
On 3/12/24 14:29, Nicholas Piggin wrote:
On Tue Mar 12, 2024 at 2:55 PM AEST, Harsh Prateek Bora wrote:
On 3/12/24 10:20, Harsh Prateek Bora wrote:
On 3/12/24 00:21, Nicholas Piggin wrote:
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove
On 3/12/24 14:18, Nicholas Piggin wrote:
On Tue Mar 12, 2024 at 4:38 PM AEST, Harsh Prateek Bora wrote:
Hi Nick,
One minor comment below:
On 2/24/24 13:03, Nicholas Piggin wrote:
PPC_VIRTUAL_HYPERVISOR_GET_CLASS is used in critical operations like
interrupts and TLB misses and is quite
them but it has no accelerator drivers which are usable,
+ * so there isn't much need for it anyway.
*/
If doing a re-spin, you may consider comments on prev patch applicable
above as well. Either ways, with prev typo fixed:
Reviewed-by: Harsh Prateek Bora
if (ppc_hash64_has
it, a cap would have
+ * to be added, or support implemented for MTTCG.
+ */
+
This comment could go in the beginning where we are actually disabling it.
Otherwise,
Reviewed-by: Harsh Prateek Bora
if (ppc_hash64_has(cpu, PPC_HASH64_CI_LARGEPAGE)) {
/*
* Note
|
-(1ull << MSR_TM) |
(1ull << MSR_VR) |
(1ull << MSR_VSX) |
(1ull << MSR_EE) |
Otherwise,
Reviewed-by: Harsh Prateek Bora
et/ppc/mmu-book3s-v3.h
@@ -108,9 +108,7 @@ static inline hwaddr ppc_hash64_hpt_mask(PowerPCCPU *cpu)
uint64_t base;
if (cpu->vhyp) {
All the checks for cpu->vhyp needs to be changed to check for
cpu->vhyp_class now, for all such instances.
With that,
On 3/12/24 10:20, Harsh Prateek Bora wrote:
On 3/12/24 00:21, Nicholas Piggin wrote:
The POWER9 DD1 and POWER10 DD1 chips are not public and are no longer of
any use in QEMU. Remove them.
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_cpu_core.c | 2 --
target/ppc/cpu-models.c | 4
,
CPU_POWERPC_POWER9_DD22= 0x004E1202,
CPU_POWERPC_POWER10_BASE = 0x0080,
With that,
Reviewed-by: Harsh Prateek Bora
regards,
Harsh
diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c
index 40b7c52f7f..50523ead25 100644
--- a/hw/ppc/spapr_cpu_core.c
+++ b/hw/ppc
Adding initial documentation about Nested PAPR API to describe the set
of APIs and its usage. Also talks about the Guest State Buffer elements
and it's format which is used between L0/L1 to communicate L2 state.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
docs/devel
a deleteAll flag.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h| 4 +-
include/hw/ppc/spapr_nested.h | 7 +++
hw/ppc/spapr_nested.c | 103 ++
3 files changed, 113 insertions(+), 1 deletion(-)
diff
the state of a guest or
a guest VCPU. On success, guest (or its VCPU) state shall be
updated as per the value field for the requested element(s).
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h| 3 +
include/hw/ppc/spapr_nested.h
spapr_exit_nested and spapr_get_pate_nested_hv contains code which
is specific to nested-hv API. Isolating code flows based on API
helps extending it to be used with different API as well.
Signed-off-by: Harsh Prateek Bora
Suggested-by: Nicholas Piggin
---
include/hw/ppc/spapr_nested.h | 3
-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h| 2 ++
include/hw/ppc/spapr_nested.h | 8 +
hw/ppc/spapr_nested.c | 61 +++
3 files changed, 71 insertions(+)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h
index 13416fc3d7
Currently, nested_ppc_state stores a certain set of registers and works
with nested_[load|save]_state() for state transfer as reqd for nested-hv API.
Extending these with additional registers state as reqd for nested PAPR API.
Signed-off-by: Harsh Prateek Bora
Suggested-by: Nicholas Piggin
-registeration of hypercalls would hit assert otherwise.
Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
---
include/hw/ppc/spapr.h| 4
include/hw/ppc/spapr_nested.h | 1 -
hw/ppc/spapr.c| 1 +
hw/ppc/spapr_hcall.c | 24 ++--
hw/ppc
Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
---
include/hw/ppc/spapr.h| 3 ++-
include/hw/ppc/spapr_nested.h | 5 +
hw/ppc/spapr_nested.c | 8
3 files changed, 11 insertions(+), 5 deletions(-)
diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc
exchange of each of the nested guest state elements for which get/set state
should be supported by the API.
[amachhiw: set the PCR whenever logical PVR is set]
Signed-off-by: Michael Neuling
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Amit Machhiwal
Signed-off-by: Harsh Prateek Bora
---
include
compat mode and return register bug fixes]
Signed-off-by: Michael Neuling
Signed-off-by: Amit Machhiwal
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr.h| 7 ++-
include/hw/ppc/spapr_nested.h | 12
hw/ppc/spapr_nested.c | 112
-devel/2023090604.448244-1-hars...@linux.ibm.com/
Harsh Prateek Bora (14):
spapr: nested: register nested-hv api hcalls only for cap-nested-hv
spapr: nested: move nested part of spapr_get_pate into spapr_nested.c
spapr: nested: Introduce SpaprMachineStateNested to store related
info
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() via
helper.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc/spapr_nested.h | 4
hw/ppc/spapr.c| 6
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API for nested guests. This new API is to enable support for KVM on PowerVM
and the support in Linux kernel has already merged upstream.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
include/hw/ppc
Most of the nested code has already been moved to spapr_nested.c
This logic inside spapr_get_pate is related to nested guests and
better suited for spapr_nested.c, hence moving there.
Signed-off-by: Harsh Prateek Bora
Reviewed-by: Nicholas Piggin
---
include/hw/ppc/spapr_nested.h | 3 ++-
hw
exceptions, or an outstanding Host Partition Interrupt.
The reason that the Guest VCPU stopped running is communicated through
R4 and the output buffer will be filled in with any relevant state.
Signed-off-by: Michael Neuling
Signed-off-by: Harsh Prateek Bora
---
target/ppc/cpu.h | 2 +
hw
On 2/27/24 15:53, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
From: Amit Machhiwal
In APIv1, KVM L0 sets the PCR, while in the nested papr APIv2, this
doesn't work as the PCR can't be set via the guest state buffer; the
logical PVR is set via
On 2/27/24 15:52, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Introduce a SPAPR capability cap-nested-papr which enables nested PAPR
API for nested guests. This new API is to enable support for KVM on PowerVM
and the support in Linux kernel has
Hi Nick,
On 2/27/24 15:46, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
For nested PAPR API, we use SpaprMachineStateNestedGuest struct to store
partition table info, use the same in spapr_get_pate_nested() via
helper.
Signed-off-by: Michael Neuling
Hi Nick,
On 2/27/24 15:40, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Introduce the nested PAPR hcalls:
- H_GUEST_GET_STATE which is used to get state of a nested guest or
a guest VCPU. The value field for each element in the request
On 2/27/24 15:32, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Nested PAPR API provides a standard Guest State Buffer (GSB) format
with unique IDs for each guest state element for which get/set state is
supported by the API. Some of the elements
On 2/27/24 15:29, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Currently, nested_ppc_state stores a certain set of registers and works
with nested_[load|save]_state() for state transfer as reqd for nested-hv API.
Extending these with additional
On 2/27/24 15:21, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:36 PM AEST, Harsh Prateek Bora wrote:
Introduce the nested PAPR hcall H_GUEST_CREATE_VCPU which is used to
create and initialize the specified VCPU resource for the previously
created guest. Each guest can have multiple VCPUs
On 2/27/24 16:09, Nicholas Piggin wrote:
On Tue Feb 27, 2024 at 7:31 PM AEST, Harsh Prateek Bora wrote:
On 2/27/24 14:59, Nicholas Piggin wrote:
On Tue Feb 20, 2024 at 6:35 PM AEST, Harsh Prateek Bora wrote:
Adding initial documentation about Nested PAPR API to describe the set
of APIs
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