On Mon, Oct 22, 2012 at 01:40:21PM +0200, Kevin Wolf wrote:
> >> From: Jason Baron
> >>
> >> Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
> >> This allows q35 to specify its default disk type. It also allows q35 to
> >> d
On Mon, Oct 22, 2012 at 01:26:29PM +0200, Kevin Wolf wrote:
> Am 22.10.2012 12:47, schrieb Michael S. Tsirkin:
> > On Fri, Oct 19, 2012 at 04:43:26PM -0400, Jason Baron wrote:
> >> From: Jason Baron
> >>
> >> The current QEMUMachine definition has a 'use_
From: Jan Kiszka
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/lpc_ich9.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/lpc
From: Jason Baron
This allows q35 to pass/set the size of the pcie window in its update routine.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 21 -
hw/pcie_host.h |8 +---
2 files changed, 17 insertions(+), 12 deletions(-)
diff
From: Jason Baron
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is
From: Isaku Yamahata
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Reviewed-by: Paolo Bonzini
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c |6 +++---
1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c
From: Jason Baron
Lay the groundwork for subsequent ich9 support.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c| 315 +
hw/acpi_ich9.h| 47
hw/i386/Makefile.objs |1 +
hw/ich9.h
-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c | 18 ++
hw/pci.h |2 ++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index b1b105d..0bcb45e 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1121,6 +1121,24 @@ void
From: Jason Baron
This fills out the usb slots on q35, when -usb is passed.
We now have (lspci output):
00:1d.0 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #1 (rev 03)
00:1d.1 USB Controller: Intel Corporation 82801I (ICH9 Family) USB UHCI
Controller #2 (rev 03
From: Jason Baron
Let's use PCIExpressHost with QOM.
Reviewed-by: Paolo Bonzini
Acked-by: Andreas Färber
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 14 ++
hw/pcie_host.h |4
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c
From: Jason Baron
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc.c | 19 +++
hw/pc.h |2 ++
hw/pc_q35.c |7
From: Jason Baron
This adds support for the DECchip 21154 PCI bridge.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/Makefile.objs |2 +-
hw/i21154.c | 113 ++
hw/i21154.h |9
3 files changed, 123
From: Jason Baron
Add the dmi-to-pci i82801b11 bridge chip. This is the pci bridge chip
that q35 uses on its host bus for PCI bus arbitration.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/Makefile.objs |1 +
hw/i82801b11.c | 125
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
Reviewed-by: Paolo Bonzini
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff
From: Jason Baron
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c |
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Reviewed-by: Paolo Bonzini
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h
From: Jan Kiszka
[jba...@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
hw/pci_ids.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
From: Jason Baron
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
This field should be initialized by the ma
From: Jason Baron
Fills out support for the pci assignment API. Added:
PCIINTxRoute ich9_route_intx_pin_to_irq(void *opaque, int pirq_pin)
Add calls to pci_bus_fire_intx_routing_notifier() when routing changes
are made.
Signed-off-by: Jason Baron
---
hw/ich9.h |1 +
hw/lpc_ich9.c
From: Jan Kiszka
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
From: Jan Kiszka
Reviewed-by: Paolo Bonzini
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 630739f..82ad4e8 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6
From: Jason Baron
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Reviewed-by: Paolo Bonzini
Signed-off-by: Jason Baron
---
vl.c | 36
From: Isaku Yamahata
pc q35 based chipset emulator to support pci express natively.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |2 +-
hw/pc.h |2 +
hw/pc_piix.c |4 +-
hw/pc_q35.c | 316
From: Jason Baron
Add support for the ich9 LPC chip.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |2 +-
hw/lpc_ich9.c | 523 +
2 files changed, 524 insertions(+), 1 deletions(-)
create mode
From: Jason Baron
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 172 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 181 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
Reviewed-by: Paolo Bonzini
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c
From: Jason Baron
Add support for the ich9 smbus chip.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |2 +-
hw/smbus_ich9.c | 159 +
2 files changed, 160 insertions(+), 1 deletions(-)
create mode
xc05 as 'SMBus'
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and
PCI_STATUS_DETECTED_PARITY from w1cmask
q35: Add kvmclock support
Jason Baron (15):
blockdev: Introduce
On Thu, Oct 11, 2012 at 04:53:24PM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 11:30:36PM -0400, Jason Baron wrote:
> > From: Jan Kiszka
> >
> > Both bits are added to the write-1-to-clear mask by default. As the
> > smbus device does not allow writes a
On Fri, Oct 12, 2012 at 12:06:44PM +0200, Gerd Hoffmann wrote:
> Hi,
>
> >>> I just tried out getting rid of the bridges by default.
> >>
> >> That clearly raises the question which devices should be created
> >> automatically by -M q35. I think the devices which are part of the ich9
> >> chips
On Thu, Oct 11, 2012 at 10:40:04PM +0200, Michael S. Tsirkin wrote:
> > Windows and Linux guests seem fine with either layout. Slots 1-2 are
> > specific to my setup. So this is a pretty minimal set.
>
> I guess we can remove the PCI bridge too?
>
maybe. Perhaps, we can have a very basic set of
On Thu, Oct 11, 2012 at 04:54:53PM +0200, Paolo Bonzini wrote:
> Il 11/10/2012 16:46, Michael S. Tsirkin ha scritto:
> > Yes. Reason I ask is because q35 is adding bridges by default now.
> > Would it be possible to only add them if requested on command line by user
> > instead?
>
> Can you just u
On Thu, Oct 11, 2012 at 04:46:56PM +0200, Michael S. Tsirkin wrote:
> On Thu, Oct 11, 2012 at 10:21:22AM -0400, Jason Baron wrote:
> > On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> > > On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> &g
On Thu, Oct 11, 2012 at 12:57:06PM +0200, Michael S. Tsirkin wrote:
> On Mon, Oct 08, 2012 at 11:30:39PM -0400, Jason Baron wrote:
> > From: Jason Baron
> >
> > Add piix style acpi hotplug to q35.
> >
> > Signed-off-by: Jason Baron
>
> Something I d
On Tue, Oct 09, 2012 at 10:02:50AM +0200, Paolo Bonzini wrote:
> Il 09/10/2012 05:30, Jason Baron ha scritto:
> > From: Jason Baron
> >
> > Automatically, locate the required q35 dsdt table on load. Otherwise we
> > error
> > out. This could be done in the bios,
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 120
From: Jason Baron
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 172 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 181 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
From: Jan Kiszka
[jba...@redhat.com: add PCI_CLASS_SERIAL_SMBUS definition]
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
hw/pci_ids.h |1 +
2 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index c457d50..62276ef 100644
n Kiszka (5):
pci: Add class 0xc05 as 'SMBus'
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and
PCI_STATUS_DETECTED_PARITY from w1cmask
q35: Add kvmclock support
Jason Ba
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
[jba...@redhat.com: move #define PCI_CLASS_SERIAL_SMBUS to another patch]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a
From: Isaku Yamahata
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw
From: Jason Baron
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 21 -
hw/pcie_host.h |8 +---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h |1 +
hw/pc_piix.c
From: Jason Baron
Introduce IF_AHCI so that q35 can differentiate between ide and ahci disks.
This allows q35 to specify its default disk type. It also allows q35 to
differentiate between ahci and ide disks, such that -drive if=ide does not
result in the creating of an ahci disk. This is
From: Jan Kiszka
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index ff570ce..5d
From: Isaku Yamahata
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index f855cf3..85
Signed-off-by: Jason Baron
---
hw/pci.c | 18 ++
hw/pci.h |2 ++
2 files changed, 20 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 85ebef6..c457d50 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1121,6 +1121,24 @@ void pci_device_set_intx_routing_notifier
From: Jason Baron
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc.c | 19 +++
hw/pc.h |2 ++
hw/pc_piix.c
From: Jason Baron
Let's use PCIExpressHost with QOM.
Acked-by: Andreas Färber
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 14 ++
hw/pcie_host.h |4
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2
From: Jan Kiszka
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35_smbus.c |4
From: Jason Baron
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
3 files chan
From: Jason Baron
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron
---
vl.c | 36 +---
1
From: Jason Baron
The current QEMUMachine definition has a 'use_scsi' field to indicate if a
machine type should use scsi by default. However, Q35 wants to use ahci by
default. Thus, introdue a new field in the QEMUMachine defintion, mach_if.
This field should be initialized by the ma
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index b6a619a..48083bb 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include
On Wed, Sep 26, 2012 at 10:15:39AM +0200, Markus Armbruster wrote:
> Jason Baron writes:
>
> > On Mon, Sep 24, 2012 at 06:52:29PM +0200, Markus Armbruster wrote:
> >> Jason Baron writes:
> >>
> >> > On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Arm
On Mon, Sep 24, 2012 at 06:52:29PM +0200, Markus Armbruster wrote:
> Jason Baron writes:
>
> > On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
> >> Jason Baron writes:
> >>
> >> > From: Isaku Yamahata
> >> >
> >>
On Fri, Sep 21, 2012 at 04:05:14PM +0200, Markus Armbruster wrote:
> Jason Baron writes:
>
> > From: Isaku Yamahata
> >
> > Introduce a helper function which initializes the ahci port with ide
> > devices.
> > It will be used by q35 support.
> >
> &
On Sat, Sep 15, 2012 at 02:34:18AM +0900, Isaku Yamahata wrote:
> On Fri, Sep 14, 2012 at 11:23:29AM -0400, Jason Baron wrote:
> > On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> > > On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > >
On Sat, Sep 15, 2012 at 12:14:01AM +0900, Isaku Yamahata wrote:
> On Thu, Sep 13, 2012 at 04:12:34PM -0400, Jason Baron wrote:
> > 2) hotplug
> > I've added piix acpi style hotplug to ich9.
>
> What's the point of this?
> Its design is ad-hoc and shpc/pcie hotplu
On Fri, Sep 14, 2012 at 03:26:30PM +0300, Michael S. Tsirkin wrote:
> I think it's best to smash the following patch into this one
> otherwise review becomes painful. Some short notes:
>
ok.
> > ---
> > hw/acpi_ich9.c| 315 ++
> > hw/acpi_ich9.h| 53 +++
> > h
On Fri, Sep 14, 2012 at 09:05:10AM +0200, Paolo Bonzini wrote:
> Il 13/09/2012 22:12, Jason Baron ha scritto:
> > From: Isaku Yamahata
> >
> > This was totally off: The CC registers are 16 bit (stored as little
> > endian), their offsets run in reverse order, and D26I
On Fri, Sep 14, 2012 at 09:04:06AM +0200, Paolo Bonzini wrote:
> Il 13/09/2012 22:12, Jason Baron ha scritto:
> > From: Jan Kiszka
> >
> > Signed-off-by: Jan Kiszka
> > Signed-off-by: Jason Baron
> > ---
> > hw/pci.c |1 +
> > 1 files changed,
On Fri, Sep 14, 2012 at 09:37:03AM +0200, Gerd Hoffmann wrote:
> On 09/13/12 22:12, Jason Baron wrote:
> > +if (ram_size >= 0xe000) {
> > +above_4g_mem_size = ram_size - 0xe000;
> > +below_4g_mem_size = 0xe000;
>
> We should make the h
On Fri, Sep 14, 2012 at 03:56:17PM +0200, Alexander Graf wrote:
> On 14.09.2012, at 15:50, Jason Baron wrote:
>
> > On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
> >> On 13.09.2012, at 22:12, Jason Baron wrote:
> >>
> >>> Hi,
> >
On Fri, Sep 14, 2012 at 12:29:17AM +0200, Alexander Graf wrote:
> On 13.09.2012, at 22:12, Jason Baron wrote:
>
> > Hi,
> >
> > Qemu bits for q35 support, I'm posting the seabios changes separately. The
> > patches require '-M pc_q35' and -L 'sea
From: Isaku Yamahata
Introduce a helper function which initializes the ahci port with ide devices.
It will be used by q35 support.
Cc: Alexander Graf
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/ide.h |3 +++
hw/ide/ahci.c | 16
2 files changed
Rebase q35 to 1.2 - memory api updates, acpi updates, qom...
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 65
hw/acpi_ich9.h |9 +-
hw/pc.h|2 +
hw/pc_piix.c |4 +-
hw/pc_q35.c| 189 +++---
hw/q35.c | 477
Add piix style acpi hotplug to q35.
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c | 173 +++-
hw/acpi_ich9.h | 10 +++
2 files changed, 182 insertions(+), 1 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw/acpi_ich9.c
index 570ce0c..ba463a0
]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/apb_pci.c|4 ++--
hw/bonito.c |2 +-
hw/dec_pci.c|2 +-
hw/grackle_pci.c|2 +-
hw/gt64xxx.c|2 +-
hw/pci.c|4 ++--
hw/pci.h|2 +-
hw
From: Isaku Yamahata
Factor out smram/pam logic for later use.
Which will be used by q35 too.
[jba...@redhat.com: changes for updated memory API]
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/i386/Makefile.objs |1 +
hw/pam.c | 121
From: Isaku Yamahata
This was totally off: The CC registers are 16 bit (stored as little
endian), their offsets run in reverse order, and D26IR as well as D25IR
have 4 bytes offset to their successors.
Reported-by: Jan Kiszka
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pc_q35.c |3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/hw/pc_q35.c b/hw/pc_q35.c
index 9d58519..b8c1196 100644
--- a/hw/pc_q35.c
+++ b/hw/pc_q35.c
@@ -69,6 +69,7 @@
#include
From: Jan Kiszka
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/pci.c |1 +
1 files changed, 1 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 55e4ad3..3727afa 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -1203,6 +1203,7 @@ static const pci_class_desc
From: Isaku Yamahata
Introduce pci_swizzle_map_irq_fn() for interrupt pin swizzle which is
standardized. PCI bridge swizzle is common logic, by introducing
this function duplicated swizzle logic will be avoided later.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c
From: Isaku Yamahata
Adds pci id constants which will be used by q35.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci_ids.h |2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pci_ids.h b/hw/pci_ids.h
index 301bf1c..6deeac0 100644
--- a/hw
Move ioapic_init from pc_piix.c to pc.c, to make it a common function.
Rename ioapic_init -> ioapic_init_gsi.
Signed-off-by: Jason Baron
---
hw/pc.c | 24
hw/pc.h |2 ++
hw/pc_piix.c | 25 +
3 files changed, 27 insertions(+),
If -L is specified, and qemu does not find the bios file in , then
the search fails. Add infrastructure such that the search will continue in
the default paths, if not found in the -L path.
Signed-off-by: Jason Baron
---
vl.c | 28 +---
1 files changed, 21 insertions
. Its valid
to update these bits and we must restore this state across migration.
Signed-off-by: Jason Baron
v2:
- Based on Michael Tsirkin's feedback:
-updated changelog 'wmask' -> 'cmask'
-Cleaned up comments
-Make cmask set more readable
---
hw/pcie
: Alexander Graf
Cc: Jason Baron
Cc: Kevin Wolf
Cc: Juan Quintela
Cc: Igor Mitsyanko
Signed-off-by: Jason Baron
---
v3:
-map command list base addr and fis base addr at destination
-drop port_no
-make use of VMSTATE_STRUCT_VARRAY_POINTER_INT32
hw/ide/ahci.c | 64
From: Isaku Yamahata
Factor out pc nic initialization.
This simplifies the pc initialization and will reduce the code
duplication of q35 pc initialization.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pc.c | 15 +++
hw/pc.h |1 +
hw/pc_piix.c
From: Isaku Yamahata
pci capability must be in PCI space.
It can't lay in PCIe extended config space.
Signed-off-by: Isaku Yamahata
Signed-off-by: Jason Baron
---
hw/pci.c |5 ++---
1 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 4d95984..b3
From: Jan Kiszka
Both bits are added to the write-1-to-clear mask by default. As the
smbus device does not allow writes at all, we have to remove it from
that mask, also to avoid triggering a runtime assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35_smbus.c |4
pset emulator
q35: Fix irr initialization for slots 25..31
Jan Kiszka (5):
q35: Suppress SMM BIOS initialization under KVM
q35: Fix non-PCI IRQ processing in ich9_lpc_update_apic
q35: smbus: Remove PCI_STATUS_SIG_SYSTEM_ERROR and
PCI_STATUS_DETECTED_PARITY from w1cmask
pci: Add cl
Let's use PCIExpressHost with QOM.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 14 ++
hw/pcie_host.h |4
2 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index e2fd276..027ba05 100644
--- a/hw/pcie_host.c
+++
t they continue to work with
this change.
Signed-off-by: Jason Baron
changes in v2:
-From Kevin Wolf:
-continue to set PORT_CMD_SPIN_UP, PORT_CMD_POWER_ON on reset
---
hw/ide/ahci.c |2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/hw/ide/ahci.c b/hw/ide/ahci.
From: Jan Kiszka
Same as for i44fx: KVM does not support SMM yet. Signal it initialized
to Seabios to avoid failures.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/acpi_ich9.c |7 +++
1 files changed, 7 insertions(+), 0 deletions(-)
diff --git a/hw/acpi_ich9.c b/hw
Automatically, locate the required q35 dsdt table on load. Otherwise we error
out. This could be done in the bios, but its harder to produce a good error
message.
Signed-off-by: Jason Baron
---
hw/pc_q35.c | 26 ++
1 files changed, 26 insertions(+), 0 deletions
27;t storing the vmsd version id of the source in the
migration stream?
This patch also renames the 'name' field of vmstate_pcie_device from:
PCIDevice -> PCIEDevice to differentiate it from vmstate_pci_device.
Signed-off-by: Jason Baron
---
hw/pci.c |2 +-
hw/pcie.h |1 -
From: Jan Kiszka
Avoid passing a non-PCI IRQ to ich9_gsi_to_pirq. It's wrong and triggers
an assertion.
Signed-off-by: Jan Kiszka
Signed-off-by: Jason Baron
---
hw/q35.c |6 --
1 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/hw/q35.c b/hw/q35.c
index 09e8bd7..8b
This allows q35 to pass/set the size of the pcie window in its update routine.
Signed-off-by: Jason Baron
---
hw/pcie_host.c | 21 -
hw/pcie_host.h |8 +---
2 files changed, 17 insertions(+), 12 deletions(-)
diff --git a/hw/pcie_host.c b/hw/pcie_host.c
index
On Fri, Aug 31, 2012 at 11:43:31AM -0400, Jason Baron wrote:
> On Fri, Aug 31, 2012 at 06:35:13PM +0300, Michael S. Tsirkin wrote:
> > On Fri, Aug 31, 2012 at 10:45:52AM -0400, Jason Baron wrote:
> > > On Fri, Aug 31, 2012 at 11:42:27AM +0300, Michael S. Tsirkin wrote:
>
On Fri, Aug 31, 2012 at 11:25:52PM -0700, Alexander Graf wrote:
> On 31.08.2012, at 13:54, Jason Baron wrote:
>
> > On Fri, Aug 31, 2012 at 01:29:46PM -0700, Alexander Graf wrote:
> >> On 31.08.2012, at 12:15, Jason Baron wrote:
> >>
> >>> On Fri, A
7 to verify that they continue to work with
this change.
Signed-off-by: Jason Baron
---
changes in v2:
-continue to set PORT_CMD_SPIN_UP, PORT_CMD_POWER_ON on reset (Kevin Wolf)
-drop cmd init in ahci_init() (Alexander Graf)
hw/ide/ahci.c |2 +-
1 files changed, 1 insertions(+), 1 d
On Fri, Aug 31, 2012 at 01:29:46PM -0700, Alexander Graf wrote:
> On 31.08.2012, at 12:15, Jason Baron wrote:
>
> > On Fri, Aug 31, 2012 at 12:04:59PM -0700, Alexander Graf wrote:
> >> On 31.08.2012, at 07:23, Jason Baron wrote:
> >>
> >>> On Fri, Au
On Fri, Aug 31, 2012 at 01:29:46PM -0700, Alexander Graf wrote:
> On 31.08.2012, at 12:15, Jason Baron wrote:
>
> > On Fri, Aug 31, 2012 at 12:04:59PM -0700, Alexander Graf wrote:
> >> On 31.08.2012, at 07:23, Jason Baron wrote:
> >>
> >>> On Fri, Au
On Fri, Aug 31, 2012 at 12:04:59PM -0700, Alexander Graf wrote:
> On 31.08.2012, at 07:23, Jason Baron wrote:
>
> > On Fri, Aug 31, 2012 at 12:12:22PM +0200, Kevin Wolf wrote:
> >> Am 23.08.2012 23:09, schrieb Jason Baron:
> >>> While testing q35, I found that w
On Fri, Aug 31, 2012 at 05:55:45PM +0200, Andreas Färber wrote:
> Am 30.08.2012 20:00, schrieb Jason Baron:
> > Add support for ahci migration. This patch builds upon the patches posted
> > previously by Andreas Faerber:
> >
> > http://lists.gnu.org/archive/html/qemu-
On Fri, Aug 31, 2012 at 06:35:13PM +0300, Michael S. Tsirkin wrote:
> On Fri, Aug 31, 2012 at 10:45:52AM -0400, Jason Baron wrote:
> > On Fri, Aug 31, 2012 at 11:42:27AM +0300, Michael S. Tsirkin wrote:
> > > Some minor nits below. If you dont get to it I will tweak this patch
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