compare with immediate and scalar operand)
Reviewed-by: Liu Zhiwei
---
tcg/tcg-op-gvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 0308732d9b..78ee1ced80 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -3939,7 +3939,7
From: TANG Tiancheng
This patch set introduces support for the RISC-V vector extension
in TCG backend for RISC-V targets.
v2:
1. Remove [PATCH v1 03/15] and use a simpler approach with fixed
constraints at initialization in the backend instead of modifying
register allocation constraints i
On 2024/8/14 18:15, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b
On 2024/8/14 17:55, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
+ case INDEX_op_shli_vec:
+ if (a2 > 31) {
+ t2 = tcg_temp_new_i32();
+ tcg_gen_movi_i32(t2, (int32_t)a2);
+ tcg_gen_shls_vec(vece, v0, v1, t2);
Drop the movi, j
On 2024/8/14 17:45, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
@@ -2312,6 +2314,12 @@ static void tcg_out_vec_op(TCGContext *s,
TCGOpcode opc,
case INDEX_op_xor_vec:
tcg_out_opc_vv(s, OPC_VXOR_VV, a0, a1, a2, true);
break;
+ case
On 2024/8/14 17:39, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
1.Address immediate value constraints in RISC-V Vector Extension 1.0 for
comparison instructions.
2.Extend comparison results from mask registers to SEW-width elements,
following
On 2024/8/20 17:00, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
+ case TCG_TYPE_V64:
+ case TCG_TYPE_V128:
+ case TCG_TYPE_V256:
+ tcg_debug_assert(ret > TCG_REG_V0 && arg > TCG_REG_V0);
+ tcg_target_set_vec_config(s, t
On 2024/8/14 17:17, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
+ OPC_VADD_VV = 0x57 | V_OPIVV,
+ OPC_VSUB_VV = 0x857 | V_OPIVV,
+ OPC_VAND_VV = 0x2457 | V_OPIVV,
+ OPC_VOR_VV = 0x2857 | V_OPIVV,
+ OPC_VXOR_VV = 0x2c57 | V_OPIVV,
Immediate
On 2024/8/14 17:13, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 33 +
2 files changed
On 2024/8/19 10:35, Richard Henderson wrote:
On 8/19/24 11:34, LIU Zhiwei wrote:
@@ -1914,6 +2029,11 @@ static void tcg_out_vec_op(TCGContext *s,
TCGOpcode opc,
const TCGArg args[TCG_MAX_OP_ARGS],
const int const_args[TCG_MAX_OP_ARGS
On 2024/8/14 17:01, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
@@ -827,14 +850,59 @@ static void tcg_out_ldst(TCGContext *s,
RISCVInsn opc, TCGReg data,
static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg,
TCGReg arg1, intptr_t arg2
On 2024/8/14 16:24, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
In RISC-V, vector operations require initial configuration using
the vset{i}vl{i} instruction.
This instruction:
1. Sets the vector length (vl) in bytes
2. Configures the vtype
On 2024/8/14 17:11, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
@@ -641,6 +645,13 @@ static bool tcg_out_mov(TCGContext *s, TCGType
type, TCGReg ret, TCGReg arg)
case TCG_TYPE_I64:
tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0);
break;
+ case
On 2024/8/14 12:18, Richard Henderson wrote:
On 8/14/24 13:30, LIU Zhiwei wrote:
On 2024/8/14 11:08, Richard Henderson wrote:
On 8/14/24 12:27, LIU Zhiwei wrote:
On 2024/8/14 10:04, Richard Henderson wrote:
On 8/14/24 10:58, LIU Zhiwei wrote:
Thus if we want to use all registers of
On 2024/8/14 11:08, Richard Henderson wrote:
On 8/14/24 12:27, LIU Zhiwei wrote:
On 2024/8/14 10:04, Richard Henderson wrote:
On 8/14/24 10:58, LIU Zhiwei wrote:
Thus if we want to use all registers of vectors, we have to add a
dynamic constraint on register allocation based on IR types
On 2024/8/14 10:04, Richard Henderson wrote:
On 8/14/24 10:58, LIU Zhiwei wrote:
Thus if we want to use all registers of vectors, we have to add a
dynamic constraint on register allocation based on IR types.
My comment vs patch 4 is that you can't do that, at least not without
On 2024/8/13 19:52, Richard Henderson wrote:
On 8/13/24 21:34, LIU Zhiwei wrote:
From: TANG Tiancheng
When allocating registers for input and output, ensure they match
the available registers to avoid allocating illeagal registers.
We should respect RISC-V vector extension's variable-l
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.h | 10 +++---
1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index eb5129a976..fe6c50e49e 100644
--- a/tcg/riscv/tcg-target.h
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 107 -
tcg/riscv/tcg-target.h | 8 +--
tcg/riscv/tcg-target.opc.h | 3 ++
3 files changed, 113 insertions(+), 5 deletions(-)
diff --git a
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 38 ++
tcg/riscv/tcg-target.h | 4 ++--
3 files changed, 41 insertions(+), 2 deletions(-)
diff --git
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 25 +
tcg/riscv/tcg-target.h | 2 +-
2 files changed, 26 insertions(+), 1 deletion(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 32
tcg/riscv/tcg-target.h | 4 ++--
2 files changed, 34 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 13 +
tcg/riscv/tcg-target.h | 4 ++--
3 files changed, 16 insertions(+), 2 deletions(-)
diff --git a/tcg/riscv/tcg
x27;s cmp_vec behavior by expanding compare results to
full element width: all 1s for true, all 0s for false.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 2 +
tcg/riscv/tcg-target-con-str.h | 1 +
tcg/riscv/tcg-target.c.inc
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 1 +
tcg/riscv/tcg-target.c.inc | 33 +
2 files changed, 34 insertions(+)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 43 ++
1 file changed, 43 insertions(+)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index f17d679d71..f60913e805 100644
From: TANG Tiancheng
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-set.h | 2 +
tcg/riscv/tcg-target.c.inc | 92 --
2 files changed, 91 insertions(+), 3 deletions(-)
diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg
: Weiwei Li
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target.c.inc | 121 +
1 file changed, 121 insertions(+)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index ca9bafcb3c..d17f523187 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg
each group.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tcg/riscv/tcg-target-con-str.h | 1 +
tcg/riscv/tcg-target.c.inc | 151 ++---
tcg/riscv/tcg-target.h | 78 ++---
tcg/riscv/tcg-target.opc.h | 12 +++
4 files changed
f-by: TANG Tiancheng
Fixes: 29f5e92502 (tcg: Introduce paired register allocation)
Reviewed-by: Liu Zhiwei
---
tcg/tcg.c | 20 +---
1 file changed, 13 insertions(+), 7 deletions(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index 34e3056380..d26b42534d 100644
--- a/tcg/tcg.c
+++ b/tcg/tcg.c
compare with immediate and scalar operand)
Reviewed-by: Liu Zhiwei
---
tcg/tcg-op-gvec.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg-op-gvec.c b/tcg/tcg-op-gvec.c
index 0308732d9b..78ee1ced80 100644
--- a/tcg/tcg-op-gvec.c
+++ b/tcg/tcg-op-gvec.c
@@ -3939,7 +3939,7
stead.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
host/include/riscv/host/cpuinfo.h | 1 +
util/cpuinfo-riscv.c | 20 ++--
2 files changed, 19 insertions(+), 2 deletions(-)
diff --git a/host/include/riscv/host/cpuinfo.h
b/host/include/riscv/host/cpui
From: TANG Tiancheng
This patch set introduces support for the RISC-V vector extension
in TCG backend for RISC-V targets.
Key features of this patch series include:
1. Improved register allocation constraints for vector registers.
2. Implementation of vset{i}vli instructions for vector confi
o relax it to
MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 18 ++
1 file changed, 14 insertions(+), 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index 49682292b8..8a46124f98
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q
extensions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv
Compressed encodings also applies to zama16b.
https://github.com/riscv/riscv-isa-manual/pull/1557
Suggested-by: Alistair Francis
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
target/riscv/insn_trans
. Fix not clean split in patch 1.
3. Explicitly specified aligment for fld/fsd under all cases.
v2<-v1:
1. Add mxlen check for fld when applies zama16b.
2. Relax fld/fsd alignment for MO_ATOM_IFALIGN to MO_ATOM_NONE.
LIU Zhiwei (3):
target/riscv: Remove redundant insn length check
On 2024/8/2 14:45, Richard Henderson wrote:
On 8/2/24 16:21, LIU Zhiwei wrote:
By the way, the MXL is const now in recently updated RISC-V
specification.
Oh yes?
Yes. In 1.13 privileged specification about MISA CSR:
"The MXL field is read-only. If misa is nonzero, the MXL
On 2024/8/2 13:47, Richard Henderson wrote:
On 8/2/24 13:16, LIU Zhiwei wrote:
Zama16b loads and stores of no more than MXLEN bits defined in the F,
D, and Q
extensions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2
On 2024/8/2 13:38, Richard Henderson wrote:
On 8/2/24 13:16, LIU Zhiwei wrote:
@@ -47,7 +47,12 @@ static bool trans_fld(DisasContext *ctx, arg_fld *a)
REQUIRE_FPU;
REQUIRE_EXT(ctx, RVD);
- if (ctx->cfg_ptr->ext_zama16b && (ctx->cur_insn_len != 2)) {
+ /
On 2024/8/2 13:52, Richard Henderson wrote:
On 8/2/24 13:16, LIU Zhiwei wrote:
According to the risc-v specification:
"FLD and FSD are only guaranteed to execute atomically if the effective
address is naturally aligned and XLEN≥64."
We currently implement fld as MO_ATOM_IFALIGN
On 2024/8/2 13:47, Richard Henderson wrote:
On 8/2/24 13:16, LIU Zhiwei wrote:
Zama16b loads and stores of no more than MXLEN bits defined in the F,
D, and Q
extensions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2
o relax it to
MO_ATOM_NONE.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 26 ++---
1 file changed, 19 insertions(+), 7 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv/insn_trans/trans_rvd.c.inc
index dbe508c7e0..458d
Zama16b loads and stores of no more than MXLEN bits defined in the F, D, and Q
extensions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvd.c.inc
b/target/riscv
Compressed encodings also applies to zama16b.
https://github.com/riscv/riscv-isa-manual/pull/1557
Suggested-by: Alistair Francis
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 9 +++--
target/riscv/insn_trans/trans_rvf.c.inc | 4 ++--
target/riscv/insn_trans
gnment for MO_ATOM_IFALIGN to MO_ATOM_NONE.
LIU Zhiwei (3):
target/riscv: Remove redundant insn length check for zama16b
target/riscv: Add MXLEN check for F/D/Q applies to zama16b
target/riscv: Relax fld alignment requirement
target/riscv/insn_trans/trans_rvd.c.in
On 2024/7/31 17:38, Alistair Francis wrote:
On Thu, Jul 25, 2024 at 11:53 AM LIU Zhiwei
wrote:
On 2024/7/23 13:59, Richard Henderson wrote:
On 7/23/24 15:29, LIU Zhiwei wrote:
The more detailed information about its meaning is in priviledged
1.13 specification. More exactly, in 3.6.4
On 2024/7/29 14:07, Alvin Che-Chia Chang(張哲嘉) wrote:
Hi Zhiwei,
-Original Message-
From: LIU Zhiwei
Sent: Monday, July 29, 2024 1:47 PM
To: Alvin Che-Chia Chang(張哲嘉) ;
qemu-ri...@nongnu.org; qemu-devel@nongnu.org
Cc: alistair.fran...@wdc.com; bin.m...@windriver.com;
liwei1
On 2024/7/27 12:27, Alvin Chang wrote:
The function of riscv_cpu_claim_interrupts() was introduced in commit
e3e7039 ("RISC-V: Allow interrupt controllers to claim interrupts") to
enforce hardware controlled of SEIP signal when there is an attached
external interrupt controller.
In later RISC-
On 2024/7/24 23:01, Andrew Jones wrote:
On Sat, Jul 20, 2024 at 07:11:48AM GMT, LIU Zhiwei wrote:
We may need 32-bit max or 32-bit any CPU for RV64 QEMU. Thus we add
these two CPUs for RV64 QEMU.
The reason we don't expose them to RV32 QEMU is that we already have
max or any cpu wit
On 2024/7/23 13:59, Richard Henderson wrote:
On 7/23/24 15:29, LIU Zhiwei wrote:
The more detailed information about its meaning is in priviledged
1.13 specification. More exactly, in 3.6.4. Misaligned Atomicity
Granule PMA.
The specification said:
"The misaligned atomicity granul
On 2024/7/23 13:59, Richard Henderson wrote:
On 7/23/24 15:29, LIU Zhiwei wrote:
The more detailed information about its meaning is in priviledged
1.13 specification. More exactly, in 3.6.4. Misaligned Atomicity
Granule PMA.
The specification said:
"The misaligned atomicity granul
On 2024/7/23 10:11, Richard Henderson wrote:
On 7/23/24 11:30, LIU Zhiwei wrote:
Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
translation function for compressed instructions, thus we can
remove instruction length check for them.
Suggested-by: Alistair Francis
Signed-off-by
Both trans_fld/fsd/flw/fsw and gen_load/store will never be a
translation function for compressed instructions, thus we can
remove instruction length check for them.
Suggested-by: Alistair Francis
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_rvd.c.inc | 4 ++--
target/riscv
On 2024/7/23 7:32, Alistair Francis wrote:
On Thu, Jul 18, 2024 at 12:10 PM Alistair Francis wrote:
From: LIU Zhiwei
Zama16b is the property that misaligned load/stores/atomics within
a naturally aligned 16-byte region are atomic.
According to the specification, Zama16b applies only to
make check-avocado AVOCADO_TESTS=tests/avocado/tuxrun_baselines.py: \
TuxRunBaselineTest:test_riscv64_rv32
Signed-off-by: LIU Zhiwei
Suggested-by: Daniel Henrique Barboza
---
tests/avocado/tuxrun_baselines.py | 16
1 file changed, 16 insertions(+)
diff --git a/tests/avocado
ction doesn't
exist in RV32 CPU.
Signed-off-by: LIU Zhiwei
Suggested-by: Daniel Henrique Barboza
---
target/riscv/cpu-qom.h | 2 ++
target/riscv/cpu.c | 13 -
2 files changed, 10 insertions(+), 5 deletions(-)
diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h
index
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 17 -
1
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h |
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b
TCH v1 4/6.
Add an avocado test.
v1:
https://mail.gnu.org/archive/html/qemu-riscv/2024-06/msg00501.html
LIU Zhiwei (2):
target/riscv: Add any32 and max32 CPU for RV64 QEMU
tests/avocado: Boot Linux for RV32 cpu on RV64 QEMU
TANG Tiancheng (6):
target/riscv: Add fw_dynamic_info32 for booting R
On 2024/7/12 17:57, Daniel Henrique Barboza wrote:
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
From: 甲一
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an
On 2024/7/12 17:52, Daniel Henrique Barboza wrote:
On 7/9/24 11:24 PM, LIU Zhiwei wrote:
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Acked-by: Alista
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 17 -
1
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h |
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu
From: 甲一
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
# make check-avocado
AVOCADO_TESTS=/home/jenkins/git/qemu/tests/avoca
On 2024/7/10 9:31, Alistair Francis wrote:
On Mon, Jul 8, 2024 at 11:22 PM LIU Zhiwei wrote:
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
disas/riscv.c | 60 +++
1 file changed, 60 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index d29cb1ff7d..c8364c2b07 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -954,6
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5219b44176..8cd52e6801 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -117,6 +117,7 @@ const
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/insn32.decode | 2 ++
target/riscv/insn_trans/trans_rvzabha.c.inc | 14 ++
2 files changed, 16 insertions(+)
diff --git a/target/riscv/insn32.decode b/target/riscv/insn32.decode
index
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rvzacas.c.inc | 13 -
target/riscv/translate.c| 13 +
2 files changed, 13 insertions(+), 13 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvzacas.c.inc
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn32.decode | 20 +++
target/riscv/insn_trans/trans_rvzabha.c.inc | 131
target/riscv/translate.c| 4 +-
4
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
---
target/riscv/insn_trans/trans_rva.c.inc | 21 -
target/riscv/translate.c| 21 +
2 files changed, 21 insertions(+), 21 deletions(-)
diff --git a/target/riscv/insn_trans
of RVWMO—i.e., it will execute atomically.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv/insn_trans/trans_rva.c.inc | 42 ++---
target/riscv/insn_trans
Although in QEMU disassemble, we usually lift compressed instruction
to an normal format when display the instruction name. For C.MOP.n,
it is more reasonable to directly display its compressed name, because
its behavior can be redefined by later extension.
Signed-off-by: LIU Zhiwei
Acked-by
. zama16b
https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00212.html
3. zabha
https://mail.gnu.org/archive/html/qemu-riscv/2024-05/msg00214.html
LIU Zhiwei (11):
target/riscv: Add zimop extension
disas/riscv: Support zimop disassemble
target/riscv: Add zcmop extensio
register.
In current implementation, C.MOP.n only has an check function, without any
other more behavior.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Deepak Gupta
---
target/riscv/cpu.c | 2 ++
target/riscv/cpu_cfg.h | 1
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
Reviewed-by: Deepak Gupta
---
disas/riscv.c | 98 +++
1 file changed, 98 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
index 90d6b26de9..0b82ab2322 100644
--- a/disas/riscv.c
+++ b
initially are defined to simply write zero to x[rd],
but are designed to be redefined by later extensions to perform some
other action.
Signed-off-by: LIU Zhiwei
Reviewed-by: Alistair Francis
Reviewed-by: Deepak Gupta
---
target/riscv/cpu.c | 2 ++
target/riscv
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Acked-by: Alista
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a
From: TANG Tiancheng
Ensure correct bit width based on sxl when running RV32 on RV64 QEMU.
This is required as MMU address translations run in S-mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu_helper.c | 17 -
1
From: TANG Tiancheng
Ensure that riscv_cpu_sxl returns MXL_RV32 when runningRV32 in an
RV64 QEMU.
Signed-off-by: TANG Tiancheng
Fixes: 05e6ca5e156 ("target/riscv: Ignore reserved bits in PTE for RV64")
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/cpu.h |
From: TANG Tiancheng
Ensure pmp_size is correctly determined using mxl for RV32
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
Reviewed-by: Alistair Francis
---
target/riscv/pmp.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/pmp.c b
From: TANG Tiancheng
RV32 OpenSBI need a fw_dynamic_info parameter with 32-bit fields instead
of target_ulong.
In RV64 QEMU, target_ulong is 64. So it is not right for booting RV32 OpenSBI.
We create a fw_dynmaic_info32 struct for this purpose.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu
From: TANG Tiancheng
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And add an avocado test in tests/avocado.
The recent commit 9b91879b51 ("hw/riscv/virt.c: Make block
ed mode not supported\n");
+}
By the way, you can get the all the reviewers mail by checking the
patch with scripts/getmaintainer.pl.
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
return RISCV_EXCP_NONE;
}
On 2024/7/3 21:08, Philippe Mathieu-Daudé wrote:
Hi,
On 3/7/24 14:34, LIU Zhiwei wrote:
From: TANG Tiancheng
This patch set aims to expose 32-bit RISC-V cpu to RV64 QEMU. Thus
qemu-system-riscv64 can directly boot a RV32 Linux.
This patch set has been tested with 6.9.0 Linux Image.
And
From: TANG Tiancheng
To regularly test booting Linux with rv32 on QEMU RV64,
we have added a test to boot_linux_console.py to retrieve
cpuinfo and verify if it shows 'rv32' when using RV64 to
boot rv32 CPUs.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
tes
From: TANG Tiancheng
Add gdb XML files and adjust CPU initialization to allow running RV32 CPUs
in RV64 QEMU.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
configs/targets/riscv64-softmmu.mak | 2 +-
target/riscv/cpu.c | 17 +
2 files changed, 14
From: TANG Tiancheng
Ensure mcause high bit is correctly set by using 32-bit width for RV32
mode and 64-bit width for RV64 mode.
Signed-off-by: TANG Tiancheng
Reviewed-by: Liu Zhiwei
---
target/riscv/cpu_helper.c | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git a
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