-} else {
-error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
-return;
-}
-} else {
-qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-}
-set_vext_version(env, vext_version);
Reviewed-by: LIU Zhiwei
Zhiwei
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
On 2023/3/17 22:02, Richard Henderson wrote:
On 3/16/23 19:57, LIU Zhiwei wrote:
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about
(env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
} else {
tlb_flush(cs);
@@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
-if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
}
Reviewed-by: LIU Zhiwei
Zhiwei
fer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
0);
+} else if (strstr(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+} else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+return 0;
+}
Reviewed-by: LIU Zhiwei
Zhiwei
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about the sequence.
1)Write_global_temp_0 // 0->TS_DEAD, but not recorded in arg_life
for XTHEAD*. I once sent a multiple disassemble path patch set for
custom extensions.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg906222.html
We may continue this work based on that patch set.
Zhiwei
Co-developed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
disas/riscv.c
On 2023/3/11 2:03, Alex Bennée wrote:
This replaces the previous attempt to add c-sky.com so I've dropped
the review/ack tags. Group everything under Alibaba now.
Added as requested by LIU Zhiwei.
Signed-off-by: Alex Bennée
Cc: LIU Zhiwei
Cc: Xuan Zhuo
Cc: Guo Ren
---
contrib/gitdm
On 2023/3/10 17:08, CHEN Yi wrote:
-Original Messages-
*From:*"LIU Zhiwei"
*Sent Time:*2023-03-10 10:12:10 (Friday)
*To:* chenyi2...@zju.edu.cn, qemu-devel@nongnu.org
*Cc:* "Palmer Dabbelt" , "Alistair Francis"
, "Bin Meng&qu
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
By the way, do you know why mstatus_tvm and hstatus_tvm are needed?
The specification said,
The TVM mechanism
On 2023/3/9 15:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel
On 2023/2/23 2:51, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to properly write this CSR, has
always been a no-op as well
On 2023/3/9 11:05, Jim Shu wrote:
On Mon, Mar 6, 2023 at 7:26 PM LIU Zhiwei wrote:
On 2023/3/5 17:42, Jim Shu wrote:
This patch also enables debugger to set current privilege mode to
VU/VS-mode.
Extend previous commit 81d2929c41d32af138f3562f5a7b309f6eac7ca7 to
support H-extension
On 2023/3/5 22:34, ~abordado wrote:
From: Afonso Bordado
RISC-V does not expose all extensions via hwcaps, thus some userspace
applications may want to query these via /proc/cpuinfo.
Currently when querying this file the host's file is shown instead
which is slightly confusing. Emulate a
On 2023/3/6 20:10, liweiwei wrote:
On 2023/3/6 19:00, LIU Zhiwei wrote:
On 2023/3/6 17:03, Weiwei Li wrote:
Add signature and signature-granularity properties in spike to
specify the target
signatrue file and the line size for signature data.
Recgonize the signature section between
rt = ldtul_p(mem_buf) & 0x1;
+if ((cs->priv == PRV_M) && (virt == true)) {
+/* M-mode only supports V=0. */
+virt = false;
+}
+riscv_cpu_set_virt_enabled(cs, virt);
return sizeof(target_ulong);
Same error here. Ot
ot;, 0);
break;
case MXL_RV64:
case MXL_RV128:
gdb_register_coprocessor(cs, riscv_gdb_get_virtual,
riscv_gdb_set_virtual,
- 1, "riscv-64bit-virtual.xml", 0);
+ 2, "
+if (i + j <= sig_len) {
+fprintf(signature, "%02x",
+ sig_data[i + j - 1] & 0xff);
Not sure about the order. Otherwise,
Reviewe
ate *env,
* illegal instruction exception should be triggered instead of virtual
* instruction exception. Hence this comes after the read / write check.
*/
+g_assert(csr_ops[csrno].predicate != NULL);
Reviewed-by: LIU Zhiwei
Zhiwei
RISCVException ret = csr_ops[csrno].p
check.
+ */
Reviewed-by: LIU Zhiwei
Zhiwei
RISCVException ret = csr_ops[csrno].predicate(env, csrno);
if (ret != RISCV_EXCP_NONE) {
return ret;
riscv_set_csr_ops(int csrno, riscv_csr_operations *ops)
csr_ops[csrno & (CSR_TABLE_SIZE - 1)] = *ops;
}
-/* Predicates */
Don't remove this comment. Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
-#if !defined(CONFIG_USER_ONLY)
-static RISCVException smstateen_acc_ok(CPURISCVState *env,
RISCVException pmp(CPURISCVState *env, int csrno)
static RISCVException epmp(CPURISCVState *env, int csrno)
{
-if (env->priv == PRV_M && riscv_cpu_cfg(env)->epmp) {
+if (riscv_cpu_cfg(env)->epmp) {
Reviewed-by: LIU Zhiwei
Zhiwei
return RISCV_EXCP_NONE;
}
static RISCVException sstc(CPURISCVState *env, int csrno)
}
}
-if ((csrno == CSR_VSTIMECMP) || (csrno == CSR_VSTIMECMPH)) {
-hmode_check = true;
-}
-
-return hmode_check ? hmode(env, csrno) : smode(env, csrno);
+return RISCV_EXCP_NONE;
Reviewed-by: LIU Zhiwei
n(CPURISCVState *env, int
csrno)
}
}
-return smode(env, csrno);
+return RISCV_EXCP_NONE;
Reviewed-by: LIU Zhiwei
Zhiwei
}
/* Checks if PointerMasking registers could be accessed */
On 2023/3/2 8:30, Bin Meng wrote:
On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt wrote:
On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei wrote:
On 2023/2/28 18:40, Bin Meng wrote:
There is no need to generate the CSR XML if the Zicsr
On 2023/2/28 18:40, Bin Meng wrote:
There is no need to generate the CSR XML if the Zicsr extension
is not enabled.
Should we generate the FPU XML or Vector XML when Zicsr is not enabled?
Zhiwei
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
---
(no changes
target_ulong val)
{
-if (!riscv_feature(env, RISCV_FEATURE_MISA)) {
+if (!riscv_cpu_cfg(env)->misa_w) {
Reviewed-by: LIU Zhiwei
Zhiwei
/* drop write to misa */
return RISCV_EXCP_NONE;
}
On 2023/2/22 2:22, Daniel Henrique Barboza wrote:
On 2/21/23 14:06, Andrew Jones wrote:
On Tue, Feb 21, 2023 at 12:49:11PM -0300, Daniel Henrique Barboza wrote:
Hey,
On 2/16/23 22:42, LIU Zhiwei wrote:
On 2023/2/17 5:55, Daniel Henrique Barboza wrote:
At this moment, and apparently
Hi folks,
I am trying to do some tests on replay-input devices. One of input device
is the PL050 keyboard. But I don't understand how to use the PL050 keyboard
from a QEMU command line.
Should I compile the arm into softmmu mode and enable the graphic
display for using it? Can I see a graphic
;rs == a->rd1 || a->rs == a->rd2 || a->rd1 == a->rd2) {
-return false;
-}
-
Reviewed-by: LIU Zhiwei
Zhiwei
TCGv data1 = get_gpr(ctx, a->rd1, EXT_NONE);
TCGv data2 = get_gpr(ctx, a->rd2, EXT_NONE);
TCGv addr1 = tcg_temp_new();
ONE;
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
/*
* With a CSR read-write instruction:
* 1) The seed CSR is always available in machine mode as normal.
On 2023/2/17 5:55, Daniel Henrique Barboza wrote:
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza
---
urn RISCV_EXCP_NONE;
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
if (env->priv < PRV_M && !get_field(env->mcounteren, ctr_mask)) {
return RISCV_EXCP_ILLEGAL_INST;
}
uot;, "vxrm", "vcsr",
-"vl", "vtype", "vlenb"
-};
-
-for (i = 0; i < 7; i++) {
-g_string_append_printf(s,
- "",
- vector_csrs[i], TARGET_LONG_BITS, base
tring_free(s, false);
+
+#if !defined(CONFIG_USER_ONLY)
+env->debugger = false;
+#endif
+
Reviewed-by: LIU Zhiwei
Zhiwei
return CSR_TABLE_SIZE;
}
42,11 @@ static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
-static bool check_pmp_reg_index(CPURISCVState *env, uint32_t reg_index)
-{
-/* TODO: RV128 restriction check */
Should keep this comment. Otherwise,
Reviewed-by: LIU
nction.
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
if (env->misa_ext & RVV ||
cpu->cfg.ext_zve32f || cpu->cfg.ext_zve64f) {
@@ -108,8 +106,7 @@ static RISCVException vs(CPURISCVState *env, int csrno)
static RISCVException ctr(CPURISCVState *env, int csrno)
;
}
-pmpcfg_csr_write(env, csrno - CSR_PMPCFG0, val);
+pmpcfg_csr_write(env, reg_index, val);
Reviewed-by: LIU Zhiwei
Zhiwei
return RISCV_EXCP_NONE;
}
if check fails */
-int read_only = get_field(csrno, 0xC00) == 3;
+bool read_only = get_field(csrno, 0xC00) == 3;
Reviewed-by: LIU Zhiwei
Zhiwei
int csr_min_priv = csr_ops[csrno].min_priv_ver;
/* ensure the CSR extension is enabled. */
7 +3340,7 @@ static RISCVException read_mseccfg(CPURISCVState *env,
int csrno,
}
static RISCVException write_mseccfg(CPURISCVState *env, int csrno,
- target_ulong val)
+target_ulong val)
Reviewed-by: LIU Zhiwei
Zhiwei
{
mseccfg_csr_write(env, val);
return RISCV_EXCP_NONE;
, riscv_gdb_set_csr,
+ riscv_gen_dynamic_csr_xml(cs, base_reg),
+ "riscv-csr.xml", 0);
+ }
Reviewed-by: LIU Zhiwei
Zhiwei
}
n_dynamic_vector_xml(cs,
-
cs->gdb_num_regs),
+ ricsv_gen_dynamic_vector_xml(cs, base_reg),
Reviewed-by: LIU Zhiwei
Zhiwei
"riscv-vector.xml", 0);
}
switch (env->misa_mxl_max) {
On 2023/2/17 9:50, LIU Zhiwei wrote:
On 2023/2/17 5:55, Daniel Henrique Barboza wrote:
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off
;& read_only) {
+return RISCV_EXCP_ILLEGAL_INST;
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
#if !defined(CONFIG_USER_ONLY)
int csr_priv, effective_priv = env->priv;
+if (env->priv_ver < csr_ops[i].min_priv_ver) {
+continue;
+}
Reviewed-by: LIU Zhiwei
Zhiwei
predicate = csr_ops[i].predicate;
if (predicate && (predicate(env, i) == RISCV_EXCP_NONE)) {
if (csr_ops[i].name) {
INT32(env.misa_ext, RISCVCPU),
VMSTATE_UINT32(env.misa_mxl_max, RISCVCPU),
VMSTATE_UINT32(env.misa_ext_mask, RISCVCPU),
-VMSTATE_UINT32(env.features, RISCVCPU),
Reviewed-by: LIU Zhiwei
Zhiwei
VMSTATE_UINTTL(env.priv, RISCVCPU),
VMSTATE_UINTTL(env
if (riscv_feature(env, RISCV_FEATURE_MMU)) {
+ if (riscv_cpu_cfg(env)->mmu) {
Reviewed-by: LIU Zhiwei
Zhiwei
/*
* If size is unknown (0), assume that all bytes
* from addr to the end of the page will be accessed.
(is_32_bit) ? "riscv,sv32" :
"riscv,sv48");
} else {
qemu_fdt_setprop_string(ms->fdt, cpu_name, "mmu-type",
"riscv,none");
}
-name = riscv_isa_string(>soc[so
_hart_has_privs_default(CPURISCVState *env,
target_ulong addr,
}
}
-if ((!riscv_feature(env, RISCV_FEATURE_PMP)) || (mode == PRV_M)) {
+if (!riscv_cpu_cfg(env)->pmp || (mode == PRV_M)) {
Reviewed-by: LIU Zhiwei
Zhiwei
/*
* Privileged spec v1.10 states if HW doesn't implement an
ddr,
{
bool ret;
-if (riscv_feature(env, RISCV_FEATURE_EPMP)) {
+if (riscv_cpu_cfg(env)->epmp) {
Reviewed-by: LIU Zhiwei
Zhiwei
if (MSECCFG_MMWP_ISSET(env)) {
/*
* The Machine Mode Whitelist Policy (mseccfg.MMWP) is set
TURE_EPMP);
+if (!cpu->cfg.pmp) {
+error_setg(errp, "Invalid configuration: EPMP requires PMP
support");
+return;
Reviewed-by: LIU Zhiwei
Zhiwei
}
}
+ b/target/riscv/machine.c
@@ -226,9 +226,8 @@ static const VMStateDescription vmstate_kvmtimer = {
static bool debug_needed(void *opaque)
{
RISCVCPU *cpu = opaque;
-CPURISCVState *env = >env;
-return riscv_feature(env, RISCV_FEATURE_DEBUG);
+ return cpu->cfg.debug;
}
On 2023/2/17 5:55, Daniel Henrique Barboza wrote:
We're going to do changes that requires accessing the RISCVCPUConfig
struct from the RISCVCPU, having access only to a CPURISCVState 'env'
pointer. Add a helper to make the code easier to read.
Signed-off-by: Daniel Henrique Barboza
---
riscv_cpu_mxl_bits(env) (1UL << (4 + riscv_cpu_mxl(env)))
+static inline const RISCVCPUConfig *riscv_cpu_cfg(CPURISCVState *env)
+{
+return _archcpu(env)->cfg;
+}
+
#if defined(TARGET_RISCV32)
#define cpu_recompute_xl(env) ((void)(env), MXL_RV32)
#else
Reviewed-by: LIU Zhiwei
Zhiwei
On 2023/2/17 5:55, Daniel Henrique Barboza wrote:
At this moment, and apparently since ever, we have no way of enabling
RISCV_FEATURE_MISA. This means that all the code from write_misa(), all
the nuts and bolts that handles how to write this CSR, has always been a
no-op as well because
On 2023/2/16 8:02, Deepak Gupta wrote:
On Wed, Feb 15, 2023 at 12:55 AM LIU Zhiwei
wrote:
On 2023/2/9 14:24, Deepak Gupta wrote:
zisslpcfi protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpcll`
short for landing pad
On 2023/2/16 7:57, Deepak Gupta wrote:
`On Wed, Feb 15, 2023 at 12:43 AM LIU Zhiwei
wrote:
On 2023/2/9 14:24, Deepak Gupta wrote:
zisslpcfi protects returns(back cfi) using shadow stack. If compiled with
enabled compiler, function prologs will have `sspush ra` instruction to
push return
On 2023/2/16 4:47, Deepak Gupta wrote:
On Tue, Feb 14, 2023 at 6:52 PM LIU Zhiwei wrote:
On 2023/2/9 14:23, Deepak Gupta wrote:
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI
On 2023/2/9 14:24, Deepak Gupta wrote:
This patch implements instruction encodings for zisslpcfi instructions.
Additionally this patch implements zimops encodings as well. If Zisslpcfi
is supported by CPU but not enabled then all Zisslpcfi instructions
default to Zimops instuction behavior
On 2023/2/9 14:24, Deepak Gupta wrote:
zisslpcfi protects forward control flow (if enabled) by enforcing all
indirect call and jmp must land on a landing pad instruction `lpcll`
short for landing pad and check lower label value. If target of an
indirect call or jmp is not `lpcll` then cpu/hart
On 2023/2/9 14:24, Deepak Gupta wrote:
zisslpcfi protects returns(back cfi) using shadow stack. If compiled with
enabled compiler, function prologs will have `sspush ra` instruction to
push return address on shadow stack and function epilogs will have
`sspop t0; sschckra` instruction
On 2023/2/9 14:23, Deepak Gupta wrote:
Implementation for forward cfi and backward cfi needs helper function
to determine if currently fcfi and bcfi are enabled. Enable depends on
privilege mode and settings in sstatus/menvcfg/henvcfg/mseccfg CSRs.
Signed-off-by: Deepak Gupta
Signed-off-by:
I don't find the modification for read_mstatus.
Zhiwei
On 2023/2/15 13:47, LIU Zhiwei wrote:
On 2023/2/9 14:23, Deepak Gupta wrote:
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch
allows
access to these CSRs. A predicate routine handles access to these CSR as
per
can occur
before target instruction is executed. In such a case this state must be
preserved so that it can be restored later. zisslpcfi saves elp state in
`sstatus` CSR.
And mstatus CSR.
Otherwise,
Reviewed-by: LIU Zhiwei
This patch saves elp state in sstatus CSR on trap delivery
while
On 2023/2/9 14:23, Deepak Gupta wrote:
CSR_SSP and CSR_LPLR are new CSR additions to cpu/hart. This patch allows
access to these CSRs. A predicate routine handles access to these CSR as
per specification.
This patch also implments new bit definitions in menvcfg/henvcfg/mstatus/
sstatus CSRs
On 2023/2/9 14:23, Deepak Gupta wrote:
`zisslpcfi` extension adds two new CSRs. CSR_SSP and CSR_LPLR.
- CSR_SSP: This CSR holds shadow stack pointer for current privilege mode
CSR_SSP is accessible in all modes. Each mode must establish
it's own CSR_SSP.
- CSR_LPLR:
On 2023/2/9 14:23, Deepak Gupta wrote:
Introducing riscv `zisslpcfi` extension to riscv target. `zisslpcfi`
extension provides hardware assistance to riscv hart to enable control
flow integrity (CFI) for software.
`zisslpcfi` extension expects hart to implement `zimops`. `zimops` stands
for
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these instructions on qemu-riscv32.
Signed-off-by: LIU Zhiwei
---
target/riscv
On 2023/2/13 13:21, Himanshu Chauhan wrote:
On 13/02/23 09:52, LIU Zhiwei wrote:
On 2023/2/9 13:52, Himanshu Chauhan wrote:
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied
On 2023/2/9 13:52, Himanshu Chauhan wrote:
When MSECCFG.MML is set, after checking the address range in PMP if the
asked permissions are not same as programmed in PMP, the default
permissions are applied. This should only be the case when there
is no matching address is found.
This patch
96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,6 +287,9 @@ RISC-V TCG CPUs
M: Palmer Dabbelt
M: Alistair Francis
M: Bin Meng
+R: Weiwei Li
+R: Daniel Henrique Barboza
+R: Liu Zhiwei
Acked-by: LIU Zhiwei
Zhiwei
L: qemu-ri...@nongnu.org
S: Supported
F
{ "vlenb",vs, read_vlenb },
/* User Timers and Counters */
[CSR_CYCLE]= { "cycle",ctr,read_hpmcounter },
[CSR_INSTRET] = { "instret", ctr,read_hpmcounter },
Reviewed-by: LIU Zhiwei
Zhiwei
On 2023/1/31 3:03, Richard Henderson wrote:
On 1/29/23 22:41, LIU Zhiwei wrote:
On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local
TCG temps first.
Do you think we should probe all the memory
On 2023/1/25 5:26, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+++ b/target/riscv/cpu.h
@@ -27,6 +27,7 @@
#include "qom/object.h"
#include "qemu/int128.h"
#include "cpu_bits.h"
+#include "cpu_vendorid.h"
I don't see that this ID is required for all users of
On 2023/1/25 5:21, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+/* XTheadMemIdx */
+
+/*
+ * Load with memop from indexed address and add (imm5 << imm2) to rs1.
+ * If !preinc, then the load address is rs1.
+ * If preinc, then the load address is rs1 + (imm5) <<
On 2023/1/30 13:43, Richard Henderson wrote:
On 1/29/23 16:03, LIU Zhiwei wrote:
Thanks. It's a bug. We should load all memory addresses to local TCG
temps first.
Do you think we should probe all the memory addresses for the store
pair instructions? If so, can we avoid the use of a helper
On 2023/1/25 4:44, Richard Henderson wrote:
On 1/24/23 09:59, Christoph Muellner wrote:
+static bool gen_loadpair_tl(DisasContext *ctx, arg_th_pair *a, MemOp
memop,
+ int shamt)
+{
+ TCGv rd1 = dest_gpr(ctx, a->rd1);
+ TCGv rd2 = dest_gpr(ctx, a->rd2);
+
On 2022/12/20 16:23, Alex Bennée wrote:
LIU Zhiwei writes:
The c-sky domain mail is no longer being used for Guo Ren and me.
C-SKY company and C-SKY arch is still existing, but its website domain
has been moved tohttps://www.t-head.cn/.
Is this the new corporate entity for the C-SKY
The c-sky domain mail is no longer being used for Guo Ren and me.
C-SKY company and C-SKY arch is still existing, but its website domain
has been moved to https://www.t-head.cn/.
Otherwise,
Reviewed-by: LIU Zhiwei
Thanks,
Zhiwei
On 2022/12/19 20:19, Alex Bennée wrote:
Although
| cpu->cfg.vlen < 8) {
+ if (cpu->cfg.elen > 64 || cpu->cfg.elen < 8) {
Oops. You are right.
Reviewed-by: LIU Zhiwei
Zhiwei
error_setg(errp,
"Vector extension implementation only
supports ELEN "
"in the range [8, 64]");
--
2.17.1
On 2022/9/8 15:29, Richard Henderson wrote:
On 9/6/22 13:22, Christoph Muellner wrote:
+NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS)
+NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU)
+NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU)
+NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU)
On 2022/9/8 15:29, Richard Henderson wrote:
On 9/6/22 13:22, Christoph Muellner wrote:
+NOP_PRIVCHECK(th_sfence_vmas, REQUIRE_PRIV_MHS)
+NOP_PRIVCHECK(th_sync, REQUIRE_PRIV_MHSU)
+NOP_PRIVCHECK(th_sync_i, REQUIRE_PRIV_MHSU)
+NOP_PRIVCHECK(th_sync_is, REQUIRE_PRIV_MHSU)
We may should rename cpu_mmu_index to cpu_mem_idx and
TB_FLAGS_PRIV_MMU_MASK to TB_FLAGS_PRIV_MEM_MASK.
We can also remove the TB_FLAGS_PRIV_MMU_MASK as the position of MEM_IDX
in tb_flags may change in the future.
Otherwise, this patch looks good to me,
Reviewed-by: LIU Zhiwei
On 2022/11/10 6:55, Alistair Francis wrote:
On Thu, Oct 13, 2022 at 4:51 PM LIU Zhiwei wrote:
Avoid calling riscv_itrigger_enabled() when calculate the tbflags.
As the itrigger enable status can only be changed when write
tdata1, migration load or itrigger fire, update env->itrigger_enab
On 2022/11/7 23:58, Alex Bennée wrote:
LIU Zhiwei writes:
On 2022/11/7 9:37, Alistair Francis wrote:
On Thu, Oct 13, 2022 at 4:32 PM LIU Zhiwei wrote:
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way
On 2022/11/7 9:37, Alistair Francis wrote:
On Thu, Oct 13, 2022 at 4:32 PM LIU Zhiwei wrote:
When icount is not enabled, there is no API in QEMU that can get the
guest instruction number.
Translate the guest code in a way that each TB only has one instruction.
I don't think this is a great
-extend, and it keeps the register usage clear.
Set base after each step of the address arithmetic instead of before.
Return the base register used from tcg_out_tlb_load, so as to
keep that register choice localized to that function.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
When guest base is zero, we should use addr_regl as base regiser instead of
the initial register TCG_REG_TMP0. Besides, we can remove the
unnecessary use of base register.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 20
1 file changed, 8 insertions(+), 12
On 2022/10/22 17:58, Richard Henderson wrote:
We were matching a signed 13-bit range, not a 12-bit range.
Expand the commentary within the function and be explicit
about all of the ranges.
Reported-by: LIU Zhiwei
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
---
tcg/riscv
On 2022/10/20 19:22, Richard Henderson wrote:
On 10/20/22 20:41, LIU Zhiwei wrote:
TYPE-I immediate can only represent a signed 12-bit value. If immediate
exceed, mov it to an register.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 28 +++-
1 file
ping
On 2022/10/12 14:00, LIU Zhiwei wrote:
Only the pmp index that be checked by pmp_hart_has_privs can be used
by pmp_get_tlb_size to avoid an error pmp index.
Before modification, we may use an error pmp index. For example,
we check address 0x4fc, and the size 0x4 in pmp_hart_has_privs
On 2022/10/20 19:31, Richard Henderson wrote:
On 10/20/22 20:41, LIU Zhiwei wrote:
It's not clear what it is doing here. And it's wrong because bl and
al are both register, so we can't add them by an ADDI instruction.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 3 ---
1
On 2022/10/20 19:18, Richard Henderson wrote:
On 10/20/22 20:41, LIU Zhiwei wrote:
When guest base is zero, we should use addr_regl as base regiser
instead of
the initial register TCG_REG_TMP0.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 4
1 file changed, 4
On 2022/10/20 19:22, Richard Henderson wrote:
On 10/20/22 20:41, LIU Zhiwei wrote:
TYPE-I immediate can only represent a signed 12-bit value. If immediate
exceed, mov it to an register.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 28 +++-
1 file
On 2022/10/20 19:26, Philippe Mathieu-Daudé wrote:
On 20/10/22 12:41, LIU Zhiwei wrote:
When guest base is zero, we should use addr_regl as base regiser
instead of
Typo "register" here and in patch subject.
the initial register TCG_REG_TMP0.
Signed-off-by: LIU Zhiwei
---
tcg
It's not clear what it is doing here. And it's wrong because bl and
al are both register, so we can't add them by an ADDI instruction.
Signed-off-by: LIU Zhiwei
---
tcg/riscv/tcg-target.c.inc | 3 ---
1 file changed, 3 deletions(-)
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg
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