-off-by: Christoph Müllner
Reviewed-by: LIU Zhiwei
Zhiwei
---
disas/riscv.c | 270 +---
disas/riscv.h | 280 ++
2 files changed, 281 insertions(+), 269 deletions(-)
create mode 100644 disas/riscv.h
if (dec.op != rv_op_illegal)
+break;
+}
+}
+
+if (dec.op == rv_op_illegal)
+dec.opcode_data = rvi_opcode_data;
Always enclose the if sentence.
Otherwise,
Reviewed-by: LIU Zhiwei
+
decode_inst_operands(&dec, isa);
decode_inst_decompress(&
On 2023/6/1 1:47, Richard Henderson wrote:
On 5/30/23 23:54, LIU Zhiwei wrote:
We missed these functions when upstreaming the bfloat16 support.
Signed-off-by: LIU Zhiwei
They look ok, so far as it goes. What will they be used for?
T-Head Xuantie CPUs custom extension need these
On 2023/5/31 15:59, Alex Bennée wrote:
LIU Zhiwei writes:
On 2023/5/30 22:24, Yeqi Fu wrote:
This patch introduces a set of feature instructions for native calls
and provides helpers to translate these instructions to corresponding
native functions. A shared library is also implemented
We missed these functions when upstreaming the bfloat16 support.
Signed-off-by: LIU Zhiwei
---
fpu/softfloat.c | 58 +
include/fpu/softfloat.h | 12 +
2 files changed, 70 insertions(+)
diff --git a/fpu/softfloat.c b/fpu/softfloat.c
index
On 2023/5/30 22:24, Yeqi Fu wrote:
This patch introduces a set of feature instructions for native calls
and provides helpers to translate these instructions to corresponding
native functions. A shared library is also implemented, where native
functions are rewritten as feature instructions. At
+DEFINE_PROP_BOOL("zcmp", RISCVCPU, cfg.ext_zcmp, false),
+DEFINE_PROP_BOOL("zcmt", RISCVCPU, cfg.ext_zcmt, false),
+
Reviewed-by: LIU Zhiwei
Zhiwei
/* Vendor-specific custom extensions */
DEFINE_PROP_BOOL("xtheadba", RISCVCPU, cfg.ext_xtheadba, false),
DEFI
report("Number of CPUs used by NUMA nodes (%d)"
+ " cannot exceed the number of available CPUs (%d).",
+ ms->numa_state->num_nodes, ms->smp.max_cpus);
+ exit(EXIT_FAILURE);
+}
Reviewed-by: LIU Zhiwei
Zhiwei
if
_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_reg);
+tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addr_adj);
Reviewed-by: LIU Zhiwei
Zhiwei
*pbase = TCG_REG_TMP0;
#else
if (a_mask) {
size, access_type, mode);
+tlb_size = pmp_get_tlb_size(env, pa);
Reviewed-by: LIU Zhiwei
Zhiwei
qemu_log_mask(CPU_LOG_MMU,
"%s PMP address=" HWADDR_FMT_plx " ret %d prot"
~0x80001FFF, RWX) write access to 0x8000 will
match PMP1.
Typo here.
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
However we cannot cache the translation result in the TLB since
this will make the write access to 0x8008 bypass the check of PMP0. So we
should check all of them instead of
djacent to the VIRT_UART0, such as 0x1100?
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
[VIRT_FW_CFG] = { 0x1010, 0x18 },
[VIRT_FLASH] ={ 0x2000, 0x400 },
[VIRT_IMSIC_M] = { 0x2400, VIRT_IMSIC_MAX_SIZE },
@@ -1508,6 +1509,9 @@ s
On 2023/4/19 11:27, Weiwei Li wrote:
We needn't check the PMP entries if there is no PMP rules.
This commit doesn't give much information. If you are fixing a bug, you
should point it out why the original implementation is wrong.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
nv->pmp_state.pmp[addr_index].addr_reg != val) {
+env->pmp_state.pmp[addr_index].addr_reg = val;
+pmp_update_rule(env, addr_index);
+tlb_flush(env_cpu(env));
+}
Reviewed-by: LIU Zhiwei
Zhiwei
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
pmp[addr_index].addr_reg = val;
pmp_update_rule(env, addr_index);
+tlb_flush(env_cpu(env));
Reviewed-by: LIU Zhiwei
Zhiwei
} else {
qemu_log_mask(LOG_GUEST_ERROR,
"ignoring pmpaddr write - locked\n");
On 2023/4/19 11:27, Weiwei Li wrote:
pmp_get_tlb_size can be separated from get_physical_address_pmp and is only
needed when ret == TRANSLATE_SUCCESS.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu_helper.c | 21 +++--
target/riscv/pmp.c
On 2023/4/19 11:27, Weiwei Li wrote:
PMP entries before the matched PMP entry(including the matched PMP entry)
may overlap partial of the tlb page, which may make different regions in
that page have different permission rights, such as for
PMP0(0x8008~0x800F, R) and PMP1(0x80001000~0x80
_code() => get_page_addr_code_hostp(): the TLB host address will be
cached, and the following instructions can use this host address directly
which may lead to the bypass of PMP related check.
We can add a link to the issue in the commit message,
https://gitlab.com/qemu-project/qemu/-/issues/1542
Reviewed-by: LI
On 2023/4/13 17:01, Weiwei Li wrote:
The translation block may also be affected when PMP entry changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index aced23c
On 2023/4/13 17:01, Weiwei Li wrote:
TLB needn't be flushed when pmpcfg/pmpaddr don't changes.
If we flush the tlb in pmp_update_rules, we don't need this patch.
Zhiwei
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 24
1 file
On 2023/4/13 17:01, Weiwei Li wrote:
TLB should be flushed not only for pmpcfg csr changes, but also for
pmpaddr csr changes.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/pmp.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/pmp.c b/target/riscv/
On 2023/4/18 14:09, Weiwei Li wrote:
On 2023/4/18 13:18, LIU Zhiwei wrote:
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li
wrote:
Not only the matched PMP entry, Any PMP entry that overlap with
partial of
the
On 2023/4/18 11:05, Weiwei Li wrote:
On 2023/4/18 10:53, Alistair Francis wrote:
On Thu, Apr 13, 2023 at 7:04 PM Weiwei Li wrote:
Not only the matched PMP entry, Any PMP entry that overlap with
partial of
the tlb page may make the regions in that page have different
permission
rights. So
On 2023/4/18 11:36, Weiwei Li wrote:
On 2023/4/18 11:07, LIU Zhiwei wrote:
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of this issue here.
By the way, I think
On 2023/4/13 17:01, Weiwei Li wrote:
This patchset tries to fix the PMP bypass problem issue
https://gitlab.com/qemu-project/qemu/-/issues/1542
Please add your analysis of this issue here.
By the way, I think this problem is introduced by
https://www.mail-archive.com/qemu-devel@nongnu.org/
predicate() must be
provided for an implemented CSR.
Reported-by: Fei Wu
Signed-off-by: Bin Meng
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/csr.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index d522efc0b6
On 2023/4/1 2:28, Christoph Muellner wrote:
From: Christoph Müllner
This patch introduces the RISC-V Zfa extension, which introduces
additional floating-point extensions:
* fli (load-immediate) with pre-defined immediates
* fminm/fmaxm (like fmin/fmax but with different NaN behaviour)
* froun
On 2023/4/4 16:48, liweiwei wrote:
On 2023/4/4 15:07, LIU Zhiwei wrote:
On 2023/4/4 11:46, liweiwei wrote:
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by
et/riscv: Reduce overhead of MSTATUS_SUM change
LIU Zhiwei (4):
target/riscv: Extract virt enabled state from tb flags
target/riscv: Add a general status enum for extensions
target/riscv: Encode the FS and VS on a normal way for tb flags
target/riscv: Add a tb flags field for vsta
On 2023/4/4 11:46, liweiwei wrote:
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula
On 2023/4/4 11:12, LIU Zhiwei wrote:
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula:
real_pc = (old)env->pc + d
On 2023/4/4 10:06, Weiwei Li wrote:
Add a base pc_save for PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
We can get pc-relative address from following formula:
real_pc = (old)env->pc + diff, where diff = target_pc - ctx->pc_save.
Use
On 2023/4/4 10:06, Weiwei Li wrote:
Compute the target address before storing it into badaddr
when mis-aligned exception is triggered.
Use a target_pc temp to store the target address to avoid
the confusing operation that udpate target address into
cpu_pc before misalign check, then update it i
2b64129 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -3518,8 +3518,6 @@ static RISCVException write_mmte(CPURISCVState *env, int
csrno,
/* for machine mode pm.current is hardwired to 1 */
wpri_val |= MMTE_M_PM_CURRENT;
-/* hardwiring pm.instruction bit to 0, since it'
On 2023/4/4 10:13, liweiwei wrote:
On 2023/4/4 09:58, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb relat
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_pc
Use gen_get_
On 2023/4/2 16:17, liweiwei wrote:
On 2023/4/2 08:34, LIU Zhiwei wrote:
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated
On 2023/4/1 20:49, Weiwei Li wrote:
Add a base save_pc For
pc_save for
PC-relative translation(CF_PCREL).
Diable the directly sync pc from tb by riscv_cpu_synchronize_from_tb.
Sync pc before it's used or updated from tb related pc:
real_pc = (old)env->pc + target_pc(from tb) - ctx->save_p
*dev, Error
**errp)
#ifndef CONFIG_USER_ONLY
+cs->tcg_cflags |= CF_PCREL;
+
Reviewed-by: LIU Zhiwei
Zhiwei
if (cpu->cfg.ext_sstc) {
riscv_timer_init(cpu);
}
te.c
@@ -551,6 +551,7 @@ static void gen_jal(DisasContext *ctx, int rd, target_ulong
imm)
next_pc = ctx->base.pc_next + imm;
if (!has_ext(ctx, RVC)) {
if ((next_pc & 0x3) != 0) {
+gen_set_pc_imm(ctx, next_pc);
I think this patch is better than it in v
mpute_xl(env);
+riscv_cpu_update_mask(env);
+}
Reviewed-by: LIU Zhiwei
Zhiwei
return RISCV_EXCP_NONE;
}
On 2023/3/28 11:33, liweiwei wrote:
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on
the
generation of effective
On 2023/3/28 11:18, Richard Henderson wrote:
On 3/27/23 19:48, liweiwei wrote:
On 2023/3/28 10:20, LIU Zhiwei wrote:
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation
s.h"
+/*
+ * The current MMU Modes are:
+ * - U 0b000
+ * - S 0b001
+ * - S+SUM 0b010
+ * - M 0b011
+ * - HLV/HLVX/HSV adds 0b100
Reviewed-by: LIU Zhiwei
Zhiwei
+ */
+#define MMUIdx_U0
+#define MMUIdx_S
dx & TB_FLAGS_PRIV_MMU_MASK;
-#endif
+return ctx->priv;
}
Could you remove the priv_level and use ctx->priv directly in this file
Otherwise,
Reviewed-by: LIU Zhiwei
Zhiwei
/* Test if priv level is M, S, or U (cannot fail). */
On 2023/3/25 18:54, Richard Henderson wrote:
Merge with mstatus_{fs,vs}. We might perform a redundant
assignment to one or the other field, but it's a trivial
and saves 4 bits from TB_FLAGS.
Signed-off-by: Richard Henderson
Reviewed-by: LIU Zhiwei
Zhiwei
---
target/riscv/
On 2023/3/28 9:55, liweiwei wrote:
On 2023/3/28 02:04, Richard Henderson wrote:
On 3/27/23 03:00, Weiwei Li wrote:
@@ -1248,6 +1265,10 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr
address, int size,
qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d
mmu_idx %d\n",
On 2023/3/27 18:00, Weiwei Li wrote:
Sign-extend the vector address when xl = 32.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/vector_helper.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
*env, target_ulong addr)
{
-return (addr & env->cur_pmmask) | env->cur_pmbase;
+return (addr & ~env->cur_pmmask) | env->cur_pmbase;
It's my typo. Thanks.
Reviewed-by: LIU Zhiwei
Zhiwei
}
/*
On 2023/3/27 18:00, Weiwei Li wrote:
Since pointer mask works on effective address, and the xl works on the
generation of effective address, so xl related calculation should be done
before pointer mask.
Incorrect. It has been done.
When updating the pm_mask, we have already considered the e
On 2023/3/27 18:00, Weiwei Li wrote:
Currently, the pc use signed-extend(in gen_set_pc*) when xl = 32. And
data address should use the same memory address space with it when
xl = 32. So we should change their address calculation to use sign-extended
address when xl = 32.
Incorrect. PC sign-ext
On 2023/3/28 9:33, LIU Zhiwei wrote:
On 2023/3/28 0:29, Richard Henderson wrote:
On 3/26/23 19:07, LIU Zhiwei wrote:
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
Can we re
On 2023/3/28 0:29, Richard Henderson wrote:
On 3/26/23 19:07, LIU Zhiwei wrote:
+static inline int mmuidx_priv(int mmu_idx)
+{
+ int ret = mmu_idx & 3;
+ if (ret == MMUIdx_S_SUM) {
+ ret = PRV_S;
+ }
+ return ret;
+}
+
Can we remove the PRIV from the tb flags afte
On 2023/3/27 16:08, Weiwei Li wrote:
Directly use env->virt_enabled instead.
Suggested-by: LIU Zhiwei
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/cpu.c| 2 +-
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c |
On 2023/3/25 18:54, Richard Henderson wrote:
Use the priv level encoded into the mmu_idx, rather than
starting from env->priv. We have already checked MPRV+MPP
in riscv_cpu_mmu_index -- no need to repeat that.
Signed-off-by: Richard Henderson
---
target/riscv/internals.h | 9 +
t
the riscv_cpu_virt_enabled
which has been called so many times.
you can pick it up into this patch set if you desire.
No matter what you choose, after small fix for patch 6, for this whole
patch set
Reviewed-by: LIU Zhiwei
Zhiwei
The port is available here:
https://github.com/plctlab/plct-qemu/t
Currently we only use the env->virt to encode the virtual mode enabled
status. Let's make it a bool type.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h| 2 +-
target/riscv/cpu_bits.h | 3 ---
target/riscv/cpu_helper.c | 6 +++---
target/riscv/machine.c| 6 +++---
targ
On 2023/3/24 20:38, Weiwei Li wrote:
Fix identation problems, and try to use the same indentation strategy
in the same file.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
---
target/riscv/arch_dump.c| 4 +-
target/riscv/cpu.c | 4 +-
targe
structions.
Signed-off-by: LIU Zhiwei
---
target/riscv/insn_trans/trans_privileged.c.inc | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/insn_trans/trans_privileged.c.inc
b/target/riscv/insn_trans/trans_privileged.c.inc
index 59501b2780..e3bee971c6 100644
--- a/target/riscv/
Virt enabled state is not a constant. So we should put it into tb flags.
Thus we can use it like a constant condition at translation phase.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h| 2 ++
target/riscv/cpu_helper.c | 2 ++
target/riscv
Reuse the MSTATUS_FS and MSTATUS_VS for the tb flags positions is not a normal
way.
It will make us change the tb flags layout difficult. And even worse, if we
want to keep tb flags for a same extension togather without a hole.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 2 +-
target/riscv
Once we mistook the vstart directly from the env->vstart. As env->vstart is not
a constant, we should record it in the tb flags if we want to use
it in translation.
Reported-by: Richard Henderson
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.h
We have found two places that misuse the fields from env.
The patch set fixes two of them. The first is virt_enabled. And another is
vstart.
And for easy moving the tb flag fields, I also make the FS and VS in tb flags
positions changable.
LIU Zhiwei (4):
target/riscv: Extract virt enabled
On 2023/3/24 20:53, liweiwei wrote:
On 2023/3/24 13:59, LIU Zhiwei wrote:
The pointer masking is the only extension that directly use status.
The vector or float extension uses the status in an indirect way.
Replace the pointer masking extension special status fields with
the general status
On 2023/3/23 14:00, Wu, Fei wrote:
On 3/23/2023 1:37 PM, LIU Zhiwei wrote:
On 2023/3/23 10:44, Fei Wu wrote:
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx.
For patch set has more than 1 patc
On 2023/3/23 10:44, Fei Wu wrote:
Currently it's assumed the 2 low bits of mmu_idx map to privilege mode,
this assumption won't last as we are about to add more mmu_idx.
For patch set has more than 1 patch, usually add a cover letter.
Signed-off-by: Fei Wu
---
target/riscv/cpu.h
Hi Daniel,
I want to share my opinions about the cpu->cfg and misa.
Two suggestions:
1) The cpu->cfg should be set only once in cpu initialization
phrase(cpu_init_fn or cpu_realize_fn), and never changes any more in
other times(for example write_misa).
2) Set the misa only when cpu->cfg is
On 2023/3/23 10:14, LIU Zhiwei wrote:
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
set_misa() is setting all 'misa' related env states and nothing else.
But other functions, namely riscv_cpu_validate_set_extensions(), uses
the config object to do its job.
This creates a need to set the single letter extensions in the cfg
obje
sa(env, env->misa_mxl, ext);
+env->misa_ext_mask = env->misa_ext = ext;
Reviewed-by: LIU Zhiwei
Zhiwei
}
#ifndef CONFIG_USER_ONLY
() */
+cpu->cfg.ext_ifencei = true;
+cpu->cfg.ext_icsr = true;
+cpu->cfg.pmp = true;
}
#endif
@@ -1384,11 +1425,6 @@ static void riscv_cpu_init(Object *obj)
{
RISCVCPU *cpu = RISCV_CPU(obj);
-cpu->cfg.ext_ifencei = true;
-cpu->cfg.ext_icsr = true;
-cpu->cfg.mmu = true;
-cpu->cfg.pmp = true;
-
Reviewed-by: LIU Zhiwei
Zhiwei
cpu_set_cpustate_pointers(cpu);
#ifndef CONFIG_USER_ONLY
static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
#ifndef CONFIG_USER_ONLY
+if (cpu->cfg.ext_sstc) {
+riscv_timer_init(cpu);
+}
+
Reviewed-by: LIU Zhiwei
Zhiwei
if (cpu->cfg.pmu_num) {
if (!riscv_pmu_init(cpu, cpu-&g
On 2023/3/23 6:19, Daniel Henrique Barboza wrote:
In the near future, write_misa() will use a variation of what we have
now as riscv_cpu_validate_set_extensions(). The pmp and epmp validation
will be required in write_misa()
I don't know why pmp and epmp should be checked in write_misa().
As
;
-break;
-#endif
-case MXL_RV32:
-cc->gdb_core_xml_file = "riscv-32bit-cpu.xml";
- break;
-default:
-g_assert_not_reached();
-}
-assert(env->misa_mxl_max == env->misa_mxl);
-
Reviewed-by: LIU Zhiwei
Zhiwei
riscv_cpu_validate_set_extensions(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
On 2023/3/22 14:40, Wu, Fei wrote:
On 3/22/2023 11:36 AM, Wu, Fei wrote:
On 3/22/2023 11:31 AM, Richard Henderson wrote:
On 3/21/23 19:47, Wu, Fei wrote:
You should be making use of different softmmu indexes, similar to how
ARM uses a separate index for PAN (privileged access never) mode. I
On 2023/3/22 10:47, Wu, Fei wrote:
On 3/22/2023 9:58 AM, LIU Zhiwei wrote:
On 2023/3/22 0:10, Richard Henderson wrote:
On 3/20/23 23:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited
On 2023/3/22 0:10, Richard Henderson wrote:
On 3/20/23 23:37, fei2...@intel.com wrote:
From: Fei Wu
Kernel needs to access user mode memory e.g. during syscalls, the window
is usually opened up for a very limited time through MSTATUS.SUM, the
overhead is too much if tlb_flush() gets called f
On 2023/3/21 14:06, Richard Henderson wrote:
On 3/20/23 21:53, LIU Zhiwei wrote:
TS_DEAD means we will release the register allocated for this
temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
Test case?
I have run an Ubuntu image
TS_DEAD means we will release the register allocated for this temporary. But
at basic block ending, we can still use the allocted register.
Signed-off-by: LIU Zhiwei
---
tcg/tcg.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/tcg/tcg.c b/tcg/tcg.c
index bb52bc060b
patch, this patch looks good to me.
Reviewed-by: LIU Zhiwei
Zhiwei
A
better place to put this code is at the end of
riscv_cpu_validate_set_extensions() after all the validations are
completed.
Add a new helper, riscv_cpu_disable_priv_spec_isa_exts(), to disable the
extesions after the validati
Vector implicitly enables zve64d, zve64f, zve32f sub extensions. As vector
only requires PRIV_1_10_0, these sub extensions should not require priv version
higher than that.
The same for Zfh.
Signed-off-by: LIU Zhiwei
---
target/riscv/cpu.c | 8
1 file changed, 4 insertions(+), 4
0,
+
+PRIV_VERSION_LATEST = PRIV_VERSION_1_12_0,
Reviewed-by: LIU Zhiwei
Zhiwei
};
#define VEXT_VERSION_1_00_0 0x0001
cfg.mmu = false;
#ifndef CONFIG_USER_ONLY
set_satp_mode_max_supported(cpu, VM_1_10_MBARE);
@@ -1160,7 +1156,7 @@ static void riscv_cpu_realize(DeviceState *dev, Error
**errp)
}
if (priv_version >= PRIV_VERSION_1_10_0) {
-set_priv_version(env, priv_ve
not specified, "
"use the default value v1.0\n");
}
-set_vext_version(env, vext_version);
+env->vext_ver = vext_version;
Reviewed-by: LIU Zhiwei
Zhiwei
}
/*
-vext_version = VEXT_VERSION_1_00_0;
-} else {
-error_setg(errp,
- "Unsupported vector spec version '%s'",
- cpu->cfg.vext_spec);
-return;
-}
-} else {
-qemu_log("vector version is not specified, "
- "use the default value v1.0\n");
-}
-set_vext_version(env, vext_version);
Reviewed-by: LIU Zhiwei
Zhiwei
}
if (cpu->cfg.ext_j) {
ext |= RVJ;
On 2023/3/17 22:02, Richard Henderson wrote:
On 3/16/23 19:57, LIU Zhiwei wrote:
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about the
(env->priv == PRV_U || get_field(env->hstatus, HSTATUS_VTVM))) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
} else {
tlb_flush(cs);
@@ -403,7 +403,7 @@ void helper_hyp_tlb_flush(CPURISCVState *env)
{
CPUState *cs = env_cpu(env);
-if (env->priv == PRV_S && riscv_cpu_virt_enabled(env)) {
+if (riscv_cpu_virt_enabled(env)) {
riscv_raise_exception(env, RISCV_EXCP_VIRT_INSTRUCTION_FAULT,
GETPC());
}
Reviewed-by: LIU Zhiwei
Zhiwei
p(buffer, "isa\t\t: rv64imafdc_zicsr_zifencei\n") ==
0);
+} else if (strstr(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+} else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+return 0;
+}
Reviewed-by: LIU Zhiwei
Zhiwei
Hi Richard,
When I read the tcg code, I find a corner case which may be a bug in
liveness_pass_1.
I see all TEMP_TBs or global temps are set to TS_DEAD | TS_MEM when
enter liveness_pass_1. Think about the sequence.
1)Write_global_temp_0 // 0->TS_DEAD, but not recorded in arg_life
2)INDEX
k for XTHEAD*. I once sent a multiple disassemble path patch set for
custom extensions.
https://www.mail-archive.com/qemu-devel@nongnu.org/msg906222.html
We may continue this work based on that patch set.
Zhiwei
Co-developed-by: LIU Zhiwei
Signed-off-by: Christoph Müllner
---
disas/ri
On 2023/3/11 2:03, Alex Bennée wrote:
This replaces the previous attempt to add c-sky.com so I've dropped
the review/ack tags. Group everything under Alibaba now.
Added as requested by LIU Zhiwei.
Signed-off-by: Alex Bennée
Cc: LIU Zhiwei
Cc: Xuan Zhuo
Cc: Guo Ren
---
contrib/
On 2023/3/10 17:08, CHEN Yi wrote:
-Original Messages-
*From:*"LIU Zhiwei"
*Sent Time:*2023-03-10 10:12:10 (Friday)
*To:* chenyi2...@zju.edu.cn, qemu-devel@nongnu.org
*Cc:* "Palmer Dabbelt" , "Alistair Francis"
, "Bin Meng&qu
On 2023/3/8 20:34, chenyi2...@zju.edu.cn wrote:
From: Yi Chen
Trap accesses to hgatp if MSTATUS_TVM is enabled.
Don't trap accesses to vsatp even if MSTATUS_TVM is enabled.
By the way, do you know why mstatus_tvm and hstatus_tvm are needed?
The specification said,
The TVM mechanism improves
On 2023/3/9 15:27, LIU Zhiwei wrote:
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
PRIV_VERSION_LATEST, at this moment assigned to PRIV_VERSION_1_12_0, is
used in all generic CPUs:
- riscv_any_cpu_init()
- rv32_base_cpu_init()
- rv64_base_cpu_init()
- rv128_base_cpu_init()
When a new PRIV version is made available we can just
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
The setter is doing nothing special. Just set env->priv_ver directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 30 +-
1 file changed
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This setter is doing nothing else but setting env->vext_ver. Assign the
value directly.
IMHO, No better than the older implementation.
Zhiwei
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu.c | 7 +--
1 file changed, 1 i
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
write_misa() must use as much common logic as possible, only specifying
the bits that are exclusive to the CSR write operation and TCG
internals.
Rewrite write_misa() to work as follows:
- supress RVC right after verifying that we're not updati
On 2023/3/9 4:19, Daniel Henrique Barboza wrote:
This restriction is found at the current implementation of write_misa()
in csr.c. Add it in riscv_cpu_validate_set_extensions() as well, while
also removing the checks we're doing considering that I or E can be
enabled.
Signed-off-by: Daniel Hen
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