While testing mttcg I noticed that VP0 gets stuck in a loop waiting
for other VPs to come up (which never actually happens). To fix this
kick VPs while they are being powered up by Cluster Power Controller.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c |1 +
1 files changed, 1 insertions
On Wed, Sep 21, 2016 at 01:16:28PM -0700, Richard Henderson wrote:
> On 09/21/2016 01:07 AM, Leon Alrae wrote:
> >+tcg_gen_brcond_tl(TCG_COND_EQ, addr, cpu_lladdr, l1);
> >+tcg_temp_free(addr);
> >+tcg_gen_movi_tl(t0, 0);
> >+tcg_gen_br(done);
&g
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
linux-user/main.c | 58 --
target-mips/cpu.h | 4
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
Richard's comments
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxchg
linux-user/main.c | 58 -
target-mips/cpu.h | 7 +--
target-mips/helper.c| 6 +--
target-mips/hel
patch also fixes some fcntl()-related LTP tests for Qemu
user mode for Mips.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall_defs.h | 2 +-
1 file
arch/mips/include/uapi/asm/sockios.h#L19
for reference.
This patch also a fixes LTP test failure for test sockioctl01, for
mips, alpha, and sh4.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Sig
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
Reviewed-by: Richard Henderson
---
target-mips/translate.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b/target-mips/translate.c
, for 64-bit Mips architectures there is no such rearrangement,
and this patch reflects it.
Signed-off-by: Aleksandar Rikalo
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall.c | 2 +-
1
cept4(3,1996486000,1996486016,128,0,0) = 5
Such output may be further improved by providing strace-related functions
that handle only particular syscalls, but this is beyond the scope of
this patch.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Acked-by: Riku Voipio
Signed-off-by: Leon
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/syscall_defs.h | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h
index 925feda..9fdbe86 100644
--- a/linux-user/syscall_defs.h
+++ b/linux-user
these syscalls are not yet supported in Qemu, but once they are
supported, they will need correct EDQUOT handling.)
Signed-off-by: Aleksandar Markovic
Reviewed-by: Laurent Vivier
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/mips/target_syscall.h | 2 ++
linux-user/mips64
executed in Qemu user mode for any Mips platform.
Signed-off-by: Miodrag Dinic
Signed-off-by: Aleksandar Markovic
Reviewed-by: Peter Maydell
Reviewed-by: Laurent Vivier
Reviewed-by: Leon Alrae
Acked-by: Riku Voipio
Signed-off-by: Leon Alrae
---
linux-user/mips/target_structs.h | 16
From: André Draszik
Define a new CPU definition supporting 24KEc cores, similar to
the existing 24Kc, but with added support for DSP instructions
and MIPS16e (and without FPU).
Signed-off-by: André Draszik
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 22
alignment cases for Mips64
linux-user: Add missing TARGET_EDQUOT error code for Mips
linux-user: Add missing Mips syscalls items in strace.list
André Draszik (1):
target-mips: add 24KEc CPU definition
Leon Alrae (1):
target-mips: generate fences
linux-user/mips/targ
Yongbok Kim takes over the target-mips maintenance from me.
Signed-off-by: Leon Alrae
---
Hi,
September is my last month in ImgTec, and therefore soon I won't be able to
look after target-mips code. I would like to nominate Yongbok Kim as the new
co-maintainer. Yongbok contributed qu
On Wed, Sep 21, 2016 at 07:12:20PM +, Riku Voipio wrote:
> On Wed, Sep 21, 2016 at 02:16:54PM +0100, Leon Alrae wrote:
> > On Mon, Sep 19, 2016 at 01:44:37PM +0200, Aleksandar Markovic wrote:
> > > From: Aleksandar Markovic
> > >
> > > v6->v7:
>
On Mon, Sep 19, 2016 at 01:44:37PM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> v6->v7:
>
> - Rebased to the latest code.
> - Patch 1/1 expanded to act on alpha and sh4.
> - Naming in patch 4/7 synced with kernel naming.
> - Change code style of patch 5/7.
> - Corr
Hi,
What's the procedure to update / who can update QEMU's dtc mirror
git://git.qemu.org/dtc.git which is used as submodule?
There's a patch series relying on the dtc v1.4.2 tag:
https://lists.nongnu.org/archive/html/qemu-devel/2016-09/msg01815.html
but the dtc mirror is outdated and that tag is
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
---
linux-user/main.c | 58 --
target-mips/cpu.h | 4 --
target-mips/helper.c
this is a missing piece in atomic helpers rather
than a problem in the code gen.
v2:
* improved and simplified SC implementation according to Richard's comments
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxc
On Fri, Sep 16, 2016 at 09:48:51AM -0700, Richard Henderson wrote:
> On 09/15/2016 01:44 AM, Leon Alrae wrote:
> > /* Store conditional */
> >+static void gen_st_cond(DisasContext *ctx, int rt, int base, int offset,
> >+int size)
> > {
On Mon, Sep 12, 2016 at 09:40:02PM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> Structure flock is defined for Mips in a way different from any
> other platform. For reference, see Linux kernel source code files:
>
> arch/mips/include/uapi/asm/fcntl.h#L63 (for Mips)
> includ
uce CP0_LLAddr which is
the actual Coperocessor 0 LLAddr register that guest can access.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
target-mips/machine.c | 7 ---
target-mips/op_helper.c | 29 +
target-mips/translate.c | 4 ++--
4 files changed,
This patch completely rewrites conditional stores. Now we use cmpxchg and
no longer need separate implementations for user and system emulation.
Signed-off-by: Leon Alrae
---
linux-user/main.c | 58 -
target-mips/cpu.h | 4 --
target-mips/helper.c| 6
this is a missing piece in atomic helpers rather
than a problem in the code gen.
Leon Alrae (2):
target-mips: compare virtual addresses in LL/SC sequence
target-mips: reimplement SC instruction and use cmpxchg
linux-user/main.c | 58 -
target-mips/cpu.h
On Mon, Sep 12, 2016 at 09:13:10AM -0700, Richard Henderson wrote:
> On 09/12/2016 12:59 AM, Leon Alrae wrote:
> >On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote:
> >>On 09/09/2016 07:46 AM, Leon Alrae wrote:
> >>>Wouldn't it be useful if tcg.
On Fri, Sep 09, 2016 at 09:26:29AM -0700, Richard Henderson wrote:
> On 09/09/2016 07:46 AM, Leon Alrae wrote:
> >Wouldn't it be useful if tcg.h provided also aliases for _le/_be atomic
> >helpers (equivalent to helper_ret_X_mmu) so that in target-* code we wouldn't
On Sat, Sep 03, 2016 at 09:39:41PM +0100, Richard Henderson wrote:
> --- a/tcg/tcg.h
> +++ b/tcg/tcg.h
> @@ -1175,6 +1175,59 @@ uint64_t helper_be_ldq_cmmu(CPUArchState *env,
> target_ulong addr,
> # define helper_ret_ldq_cmmu helper_le_ldq_cmmu
> #endif
>
> +uint32_t helper_atomic_cmpxchgb_m
> +#define GEN_ATOMIC_HELPER(NAME, OP, NEW)\
> +static void * const table_##NAME[16] = {\
> +[MO_8] = gen_helper_atomic_##NAME##b, \
> +[MO_16 | MO_LE] = gen_helper_atomic_##NAME##w_le,
On Sat, Sep 03, 2016 at 09:39:33PM +0100, Richard Henderson wrote:
> Allows Int128 to be used more generally, rather than having to
> begin with 64-bit inputs and accumulate.
>
> Signed-off-by: Richard Henderson
> ---
> include/qemu/int128.h | 20 +++-
> 1 file changed, 15 insert
On Thu, Sep 08, 2016 at 10:04:05AM -0700, Richard Henderson wrote:
> > +static void gen_sync(int stype)
> > +{
> > +TCGOrder tcg_mo = TCG_BAR_SC;
> > +
> > +switch (stype) {
> > +case 0x4: /* SYNC_WMB */
> > +tcg_mo |= TCG_MO_ST_ST;
> > +break;
> > +case 0x10: /* SYN
On Mon, Sep 05, 2016 at 04:02:05PM +0200, Aleksandar Markovic wrote:
> From: Aleksandar Markovic
>
> For some reason, Qemu's TARGET_F_GETOWN constant for Mips does not
> match the correct value of correspondant F_GETOWN. This patch fixes
> this problem.
>
> For reference, see Mips' F_GETOWN defi
On Thu, Sep 08, 2016 at 11:46:38AM +0100, Paul Burton wrote:
> On 08/09/16 09:57, Leon Alrae wrote:
> > On Fri, Aug 19, 2016 at 08:40:32PM +0100, Paul Burton wrote:
> >> On 19/08/16 20:25, no-re...@patchew.org wrote:
> >>> Hi,
> >>>
> >>> Yo
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
---
v2:
* generate weaker barriers according to stype
---
target-mips/translate.c | 32 ++--
1 file changed, 30 insertions(+), 2 deletions(-)
diff --git a/target-mips/translate.c b
On Fri, Aug 19, 2016 at 08:40:32PM +0100, Paul Burton wrote:
> On 19/08/16 20:25, no-re...@patchew.org wrote:
> > Hi,
> >
> > Your series failed automatic build test. Please find the testing commands
> > and
> > their output below. If you have docker installed, you can probably
> > reproduce it
Make use of memory barrier TCG opcode in MIPS front end.
Signed-off-by: Leon Alrae
---
This patch complements the following series:
https://lists.nongnu.org/archive/html/qemu-devel/2016-07/msg03283.html
---
target-mips/translate.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff
ps/cpu.h | 1 +
> target-mips/translate.c | 10 ++
> 2 files changed, 11 insertions(+)
Reviewed-by: Leon Alrae
ons(+), 25 deletions(-)
Reviewed-by: Leon Alrae
on
> ---
> hw/timer/mips_gictimer.c | 5 +
> include/hw/timer/mips_gictimer.h | 1 +
> 2 files changed, 6 insertions(+)
Reviewed-by: Leon Alrae
break;
> diff --git a/include/hw/misc/mips_cmgcr.h b/include/hw/misc/mips_cmgcr.h
> index a209d91..31bda6a 100644
> --- a/include/hw/misc/mips_cmgcr.h
> +++ b/include/hw/misc/mips_cmgcr.h
> @@ -41,6 +41,9 @@
> #define GCR_L2_CONFIG_BYPASS_SHF20
> #define GCR_L2_CONFIG_BYPASS_MSK((0x1ULL) << GCR_L2_CONFIG_BYPASS_SHF)
>
> +/* GCR_BASE register fields */
> +#define GCR_BASE_GCRBASE_MSK 0x8000ULL;
Unnecessary semicolon?
Otherwise
Reviewed-by: Leon Alrae
While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 1 +
1 file changed, 1 insertion(+)
diff
4:02 +0100)
MIPS patches 2016-07-29
Changes:
* bug fixes
----
Leon Alrae (1):
target-mips: fix EntryHi.EHINV being cleared on TLB exception
Paul Burton (1):
hw/mips_malta: Fix YAMON API print routine
wind up printing a continuous stream of the letter E.
Signed-off-by: Paul Burton
Cc: Aurelien Jarno
Cc: Leon Alrae
Reviewed-by: Aurelien Jarno
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
hw/mips/mips_malta.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a
While implementing TLB invalidation feature we forgot to modify
part of code responsible for updating EntryHi during TLB exception.
Consequently EntryHi.EHINV is unexpectedly cleared on the exception.
Signed-off-by: Leon Alrae
---
target-mips/helper.c |1 +
1 files changed, 1 insertions
get-mips/op_helper.c | 18 +-
> translate-all.c | 1 +
> 6 files changed, 24 insertions(+), 48 deletions(-)
Looks good to me:
Reviewed-by: Leon Alrae
Thanks,
Leon
On Tue, Jul 26, 2016 at 12:42:45AM +0100, André Draszik wrote:
> Define a new CPU definition supporting 24KEc cores, similar to
> the existing 24Kc, but with added support for DSP instructions
> and MIPS16e (and without FPU).
>
> Signed-off-by: André Draszik
> ---
> target-mips/translate_init.c
t; indicating the configuration mismatch but QEMU would previously
> incorrectly jump & wind up printing a continuous stream of the letter E.
>
> Signed-off-by: Paul Burton
> Cc: Aurelien Jarno
> Cc: Leon Alrae
> ---
> hw/mips/mips_malta.c | 2 +-
> 1 file changed,
On Thu, Jul 14, 2016 at 04:43:42PM +0300, Marcel Apfelbaum wrote:
> Delay the host-bridge 'realization' until the
> PCI root bus is attached.
>
> Signed-off-by: Marcel Apfelbaum
> ---
> hw/mips/gt64xxx_pci.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-
From: Paul Burton
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 ++
target-mips/helper.c| 10 +-
target-mips/op_helper.c | 27 +++
target-mips/translate.c | 1 +
4 files changed, 23
From: Paul Burton
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
target-mips
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7
will start execution.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cmgcr.c | 54 +++-
include/hw/misc/mips_cmgcr.h | 18 +++
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index e6cf17
sharing
global settings and registers such as GIC_SH_CONFIG.COUTNSTOP and
GIC_SH_COUNTER.
MIPS GIC Interval Timer does support upto 64 bits of Count register but
in this implementation it is limited to 32 bits only.
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
---
hw/timer/Makefile.objs
internal data is converted back into the
original format as the specification.
Limitations:
Level triggering only
GIC CounterHi not implemented (Countbits = 32bits)
DINT not implemented
Local WatchDog, Fast Debug Channel, Perf Counter not implemented
Signed-off-by: Yongbok Kim
Signed-off-by: Leon Alrae
Replace hardcoded 0xbfc0 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2
From: Paul Burton
The read-only Config4.AE bit set denotes extended 10 bits ASID.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
in CM GCR
----
Leon Alrae (6):
hw/mips/cps: create GIC block inside CPS
target-mips: add exception base to MIPS CPU
hw/mips_cpc: make VP correctly start from the reset vector
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
t
Add GIC to CPS and expose its interrupt pins instead of CPU's.
Signed-off-by: Leon Alrae
---
hw/mips/cps.c| 25 ++---
hw/mips/mips_malta.c | 4 +---
hw/misc/mips_cmgcr.c | 33 +
include/hw/mips/
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a
CPU_INTERRUPT_HALT to halt a VP.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd..6d34574 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void
Hi,
This commit causes regressions in my MIPS tests. QEMU segfaults when
booting Linux on Malta board; this can be easily reproduced with
Aurelien's Debian images:
wget https://people.debian.org/~aurel32/qemu/mipsel/vmlinux-3.2.0-4-5kc-malta
wget
https://people.debian.org/~aurel32/qemu/mipsel/de
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b/target-mips/translate_init.c
index c43bdb7..39ed5c4 100644
--- a/target-mips/translate_init.c
+++ b/target-mips/translate_init.c
@@ -685,7
From: Paul Burton
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 ++
target-mips/helper.c| 10 +-
target-mips/op_helper.c | 27 +++
target-mips/translate.c | 1 +
4 files changed, 23
From: Paul Burton
ASID currently has uint8_t type which is too small since some processors
support more than 8 bits ASID. Therefore change its type to uint16_t.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2 +-
target-mips
series is based on the patch adding I6400 CPU:
https://lists.gnu.org/archive/html/qemu-devel/2016-06/msg07604.html
Thanks,
Leon
Leon Alrae (1):
target-mips: enable 10-bit ASIDs in I6400 CPU
Paul Burton (3):
target-mips: add ASID mask field and replace magic values
target-mips: change ASID
From: Paul Burton
The read-only Config4.AE bit set denotes extended 10 bits ASID.
Signed-off-by: Paul Burton
Signed-off-by: James Hogan
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 1 +
target-mips/translate.c | 3 ++-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a
MIPS64R6-generic gradually gets closer to I6400 CPU, feature-wise. Rename
it to make it clear which MIPS processor it is supposed to emulate.
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 20 +---
1 file changed, 9 insertions(+), 11 deletions(-)
diff --git a
ot needed.
[1] "IEEE Standard for Floating-Point Arithmetic",
IEEE Computer Society, August 29, 2008.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Tested-by: Bastian Koppelmann
Reviewed-by: Leon Alrae
Tested-by: Leon Alr
anual",
Imagination Technologies LTD, Revision 6.04, November 13, 2015
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate.c | 26 ++
1 file c
From: Aleksandar Markovic
Add preprocessor definition of FCR31's FS bit, and update related
code for setting this bit.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
propagate NaNs.
* FCLASS.D ans FCLASS.S will now correcty detect NaN flavors.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/translate_init.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/target-mips/translate_init.c b
The MIPS32 SIMD Architecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
[leon.al...@imgtec.com:
* reworded the subject of the patch
* swapped if/else code blocks
From: Aleksandar Markovic
Missing values EF_MIPS_FP64 and EF_MIPS_NAN2008 added.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
include/elf.h | 2 ++
1
after
appropriate SoftFloat library function is called.
Related MSA instructions FTRUNC_S and FTINT_S already handle well
all cases, in the fashion similar to the code from this patch.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
[leon.al...@imgtec.com:
* removed a statement from the
tables for Mips, in relation to the
bit EF_MIPS_NAN2008 from ELF header, that is in turn related to
reading and writing to FCR31.
- Modify gdb behavior in relation to FCR31.
Signed-off-by: Thomas Schwinge
Signed-off-by: Maciej W. Rozycki
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Al
debug and maintain.
Signed-off-by: Aleksandar Markovic
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
fpu/softfloat-specialize.h | 57 +++---
1 file changed, 28 insertions(+), 29 deletions(-)
diff --git a/fpu/softfloat-specialize.h b/fpu/softfloat
chitecture Module",
Imagination Technologies LTD, Revision 1.12, February 3, 2016
Signed-off-by: Aleksandar Markovic
Reviewed-by: Leon Alrae
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
fpu/softfloat-specialize.h | 12
1 file changed, 12 insertions(+)
diff
Hi,
This pull request contains patches from Aleksandar which unlock
the IEEE 754-2008 support for MIPS.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit c7288767523f6510cf557707d3eb5e78e519b90d:
Merge remote-tracking branch 'remotes/dgibson/tags/ppc-for-
On Thu, Jun 23, 2016 at 04:46:14PM +0100, Peter Maydell wrote:
> On 10 June 2016 at 10:57, Aleksandar Markovic
> wrote:
> > From: Aleksandar Markovic
> >
> > This patch series provides number of IEEE 754-2008-related features to
> > Mips platform. It addresses the most sensitive changes that requ
On Fri, Jun 10, 2016 at 09:12:12PM +0100, Maciej W. Rozycki wrote:
> On Fri, 10 Jun 2016, Aleksandar Markovic wrote:
>
> > The changes that make QEMU behavior the same as hardware behavior (in
> > relation to CEIL, CVT, FLOOR, ROUND, TRUNC Mips instructions) are
> > already contained in this pat
| 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Leon Alrae
t-mips/cpu.h | 5 +
> target-mips/helper.h | 4 +-
> target-mips/msa_helper.c | 88 +++
> target-mips/op_helper.c | 17 +-
> target-mips/translate.c | 5 +-
> target-mips/translate_init.c | 2 +
> target-ppc/fpu_helper.c |
t; target-mips/gdbstub.c| 8 +++-
> target-mips/op_helper.c | 14 +++---
> target-mips/translate.c | 5 ++---
> target-mips/translate_init.c | 26 ++
> 6 files changed, 56 insertions(+), 19 deletions(-)
Reviewed-by: Leon Alrae
will start execution.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cmgcr.c | 54 +++-
include/hw/misc/mips_cmgcr.h | 18 +++
2 files changed, 71 insertions(+), 1 deletion(-)
diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c
index e6cf17
Replace hardcoded 0xbfc0 with exception_base which is initialized with
this default address so there is no functional change here.
However, it is now exposed and consequently it will be possible to modify
it from outside of the CPU.
Signed-off-by: Leon Alrae
---
target-mips/cpu.h | 2
CPU_INTERRUPT_HALT to halt a VP.
Signed-off-by: Leon Alrae
---
hw/misc/mips_cpc.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c
index e6a35dd..6d34574 100644
--- a/hw/misc/mips_cpc.c
+++ b/hw/misc/mips_cpc.c
@@ -37,7 +37,7 @@ static void
:
https://lists.nongnu.org/archive/html/qemu-devel/2016-03/msg06223.html
Thanks,
Leon
Leon Alrae (3):
target-mips: add exception base to MIPS CPU
hw/mips_cpc: make VP correctly start from the reset vector
hw/mips_cmgcr: implement RESET_BASE register in CM GCR
hw/misc/mips_cmgcr.c
> @@ -110,9 +110,11 @@ struct CPUMIPSFPUContext {
> #define FCR0_PRID 8
> #define FCR0_REV 0
> /* fcsr */
> +uint32_t fcr31_rw_bitmask;
> uint32_t fcr31;
> -#define FCR31_ABS2008 19
> -#define FCR31_NAN2008 18
> +#define FCR31_NAN2008 18
> +#define FCR31_ABS2008 19
Now the
/translate_init.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
Reviewed-by: Leon Alrae
same patch:
http://wiki.qemu.org/Contribute/SubmitAPatch#Don.27t_include_irrelevant_changes
If you drop the adjustment of surrounding code then feel free to add:
Reviewed-by: Leon Alrae
Thanks,
Leon
>
> Signed-off-by: Thomas Schwinge
> Signed-off-by: Maciej W. Rozycki
> Signe
> diff --git a/target-mips/translate.c b/target-mips/translate.c
> index e934884..2cdd2bd 100644
> --- a/target-mips/translate.c
> +++ b/target-mips/translate.c
> @@ -20129,7 +20129,11 @@ void cpu_state_reset(CPUMIPSState *env)
> env->CP0_PageGrain = env->cpu_model->CP0_PageGrain;
> env->
> - Add preprocessor constants for all bits of FCR31 and related masks
> for its subfields.
Introducing all these constants for fcr31_rw_bitmask doesn't seem necessary
or useful
>
> - Modify handling of CFC1 and CTC1 instructions (cases 25, 26, 28)
> so that they utilize newly-defind constan
ch.
>
> Signed-off-by: Aleksandar Markovic
> ---
> target-mips/helper.h| 18 +--
> target-mips/op_helper.c | 369
> +++++---
> target-mips/translate.c | 122 +---
> 3 files changed, 461 insertions(+), 48 deletions(-)
Reviewed-by: Leon Alrae
and due to a wrong usage of sizeof(). Fix that.
Cc: Stefan Weil
Cc: Leon Alrae
Cc: qemu-sta...@nongnu.org
LP: https://bugs.launchpad.net/qemu/+bug/1577841
Signed-off-by: Aurelien Jarno
Reviewed-by: Stefan Weil
Reviewed-by: Leon Alrae
Signed-off-by: Leon Alrae
---
target-mips/helper.c | 2 +-
1
From: "xiaoqiang.zhao"
* Drop the old SysBus init function and use instance_init
* Move graphic_console_init into realize stage
Signed-off-by: xiaoqiang zhao
Reviewed-by: Peter Maydell
Signed-off-by: Leon Alrae
---
hw/display/jazz_led.c | 18 +++---
1 file changed, 11
Hi,
Just two patches in the first target-mips pullreq for 2.7.
Thanks,
Leon
Cc: Peter Maydell
Cc: Aurelien Jarno
The following changes since commit bfc766d38e1fae5767d43845c15c79ac8fa6d6af:
Update version for v2.6.0 release (2016-05-11 16:44:26 +0100)
are available in the git repository a
On Thu, May 05, 2016 at 01:46:13PM +0100, Peter Maydell wrote:
> On 5 May 2016 at 04:04, xiaoqiang zhao wrote:
> > * Drop the old SysBus init function and use instance_init
> > * Move graphic_console_init into realize stage
> >
> > Signed-off-by: xiaoqiang zhao
> > ---
> > hw/display/jazz_led.c
tion by element size
> [-Wmemset-elt-size]
>
> This is indeed correct and due to a wrong usage of sizeof(). Fix that.
>
> Cc: Stefan Weil
> Cc: Leon Alrae
> LP: https://bugs.launchpad.net/qemu/+bug/1577841
> Signed-off-by: Aurelien Jarno
> ---
> target-mips/helper.
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