ions that suggested in tcg-op doc).
I will provide next version with the helper function implementation like
sve_ldN_r in ARM target.
Thank you,
Max
On 2024/6/3 1:45 AM, Richard Henderson wrote:
On 5/31/24 12:44, Max Chou wrote:
The vector unit-stride load/store instructions (e.g. vle8.v/vs
endian
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 196 +++-
1 file changed, 194 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index bbac73bb12b..44763ccec06 100644
This commit separate the helper function implementations of vector
segment load/store instructions from other vector load/store
instructions.
This can improve performance by avoiding unnecessary segment operation
when NF = 1.
Signed-off-by: Max Chou
---
target/riscv/helper.h
The helper_check_probe_[read|write] functions wrap the probe_pages
function to perform virtual address resolution for continuous vector
load/store instructions.
Signed-off-by: Max Chou
---
target/riscv/helper.h| 4
target/riscv/vector_helper.c | 12
2 files changed
* Without mask
* Without tail agnostic
* Both host and target are little endian
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 197 +++-
1 file changed, 195 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
In the vector unit-stride load/store helper functions. the vext_ldst_us
function corresponding most of the execution time. Inline the functions
can avoid the function call overhead to improve the helper function
performance.
Signed-off-by: Max Chou
Reviewed-by: Richard Henderson
---
target
) on QEMU user mode.
PS: This RFC patch set only focuses on the vle8.v/vse8.v/vl8re8.v/vs8r.v
instructions. The next version will try to complete other instructions.
Series based on riscv-to-apply.next branch (commit 1806da7).
Max Chou (6):
target/riscv: Separate vector segment ld/st instructions
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
accel/tcg/ldst_common.c.inc | 8 ++--
1 file changed, 6 insertions(+), 2 deletions(-)
diff --git
Reviewed-by: Max Chou
Max
On 2024/5/11 7:26 PM, Yangyu Chen wrote:
This code has a typo that writes zvkb to zvkg, causing users can't
enable zvkb through the config. This patch gets this fixed.
Signed-off-by: Yangyu Chen
Fixes: ea61ef7097d0 ("target/riscv: Move vector crypto exten
[PATCH] target/riscv: rvv: Check single width operator for vector fp
widen instructions
[PATCH] target/riscv: rvv: Check single width operator for
vfncvt.rod.f.f.w
[PATCH] target/riscv: rvv: Remove redudant SEW checking for vector fp
narrow/widen instructions
Max Chou (4
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-by: Max Chou
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
---
target/riscv/insn_trans
Thanks for the notification.
I'll resend this series and rebase on the riscv-to-apply.next branch.
Max
On 2024/3/22 12:12 PM, Alistair Francis wrote:
On Wed, Mar 20, 2024 at 5:28 PM Max Chou wrote:
When SEW is 16, we need to check whether the Zvfhmin is enabled for the
single width operator
According to the Zvfbfmin definition in the RISC-V BF16 extensions spec,
the Zvfbfmin extension only requires either the V extension or the
Zve32f extension.
Signed-off-by: Max Chou
---
target/riscv/tcg/tcg-cpu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/tcg/tcg-cpu.c
The opfv_narrow_check needs to check the single width float operator by
require_rvf.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 1 +
1 file changed, 1 insertion(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index
If the checking functions check both the single and double width
operators at the same time, then the single width operator checking
functions (require_rvf[min]) will check whether the SEW is 8.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 16
1 file
width float, so the opfxv_widen_check function doesn’t
need require_rvf for the single width operator(integer).
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv
instructions.
Max Chou (4):
target/riscv: rvv: Fix Zvfhmin checking for vfwcvt.f.f.v and
vfncvt.f.f.w instructions
target/riscv: rvv: Check single width operator for vector fp widen
instructions
target/riscv: rvv: Check single width operator for vfncvt.rod.f.f.w
target/riscv: rvv: Remove
According v spec 18.4, only the vfwcvt.f.f.v and vfncvt.f.f.w
instructions will be affected by Zvfhmin extension.
And the vfwcvt.f.f.v and vfncvt.f.f.w instructions only support the
conversions of
* From 1*SEW(16/32) to 2*SEW(32/64)
* From 2*SEW(32/64) to 1*SEW(16/32)
Signed-off-by: Max Chou
Reviewed-by: Max Chou
On 2024/3/15 1:56 AM, Daniel Henrique Barboza wrote:
Commit 8ff8ac6329 added a conditional to guard the vext_ldst_whole()
helper if vstart >= evl. But by skipping the helper we're also not
setting vstart = 0 at the end of the insns, which is incorrect.
We'll m
According v spec section 7.9. Vector Load/Store Whole Register Instructions
"The instructions operate with an effective vector length,
evl=NFIELDS*VLEN/EEW, regardless of current settings in vtype and vl.
The usual property that no elements are written if vstart ≥ vl does not
apply to these
Hi Daniel,
According the v spec section 15.2 & 15.3.
"The vcpop.m instruction writes x[rd] even if vl=0 (with the value 0,
since no mask elements are active).
Traps on vcpop.m are always reported with a vstart of 0. The vcpop.m
instruction will raise an illegal instruction exception if
Looks liked that I missed this one.
Thank you Daniel
Max.
On 2024/3/7 1:17 AM, Daniel Henrique Barboza wrote:
On 3/6/24 13:10, Max Chou wrote:
When vlmul is larger than 5, the original fractional LMUL checking may
gets unexpected result.
Signed-off-by: Max Chou
---
There's already
When vlmul is larger than 5, the original fractional LMUL checking may
gets unexpected result.
Signed-off-by: Max Chou
---
target/riscv/vector_helper.c | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index
On 2024/2/16 4:10 AM, Richard Henderson wrote:
On 2/15/24 09:28, Max Chou wrote:
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 68b252cb8e8..c5453810eee 100644
Hi Daniel,
Thank you for the information and suggestion.
Yes, we can do it better if we load/store more bytes at a time.
I'll try to improve the RFC on this way.
Thanks,
Max
On 2024/2/16 5:11 AM, Daniel Henrique Barboza wrote:
On 2/15/24 16:28, Max Chou wrote:
In the vector unit-stride
Hi Richard,
Thank you for the suggestion and the reference.
I'm trying to follow the reference to implement it and I'll send another
version for this.
Thanks a lot,
Max
On 2024/2/16 4:24 AM, Richard Henderson wrote:
On 2/15/24 09:28, Max Chou wrote:
Hi all,
When glibc with RVV support [1
experiment results to check the status of other
plugin callbacks.
Thanks,
Max
On 2024/2/16 4:21 AM, Daniel Henrique Barboza wrote:
On 2/15/24 16:28, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce
Hi Richard,
Thank you for the suggestion. I'll do a v2 with this.
Thanks,
Max
On 2024/2/16 4:03 AM, Richard Henderson wrote:
On 2/15/24 09:28, Max Chou wrote:
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 803c271df11..9ef35a22279 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -1050,8 +1050,9 @@ static
If there are not any QEMU plugin memory callback functions, checking
before calling the qemu_plugin_vcpu_mem_cb function can reduce the
function call overhead.
Signed-off-by: Max Chou
---
accel/tcg/ldst_common.c.inc | 40 +++--
1 file changed, 30 insertions
In the vector unit-stride load/store helper functions. the vext_ldst_us
function corresponding most of the execution time. Inline the functions
can avoid the function call overhead to imperove the helper function
performance.
Signed-off-by: Max Chou
---
target/riscv/vector_helper.c | 30
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 7 +--
1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index 68b252cb8e8..c5453810eee 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -942,8 +942,11 @@ void
Signed-off-by: Max Chou
---
accel/tcg/user-exec.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c
index c5453810eee..803c271df11 100644
--- a/accel/tcg/user-exec.c
+++ b/accel/tcg/user-exec.c
@@ -963,8 +963,9 @@ static inline
This commit seperate the helper function implementations of vector
segment load/store instructions from other vector load/store
instructions.
This can improve performance by avoiding unnecessary segment operation
when NF = 1.
Signed-off-by: Max Chou
---
target/riscv/helper.h
nly focuses on the vle8.v & vse8.v instructions,
the next version or next serious will complete other vector ld/st part.
Regards,
Max.
[1]
https://inbox.sourceware.org/libc-alpha/20230504074851.38763-1-hau@sifive.com
Max Chou (6):
target/riscv: Seperate vector segment ld/st instr
, as is the case with
most other vector instructions.
Reference:
-
https://github.com/riscv/riscv-v-spec/blob/v1.0/v-spec.adoc#whole-vector-register-move
-
https://github.com/riscv/riscv-v-spec/commit/856fe5bd1cb135c39258e6ca941bf234ae63e1b1
Max Chou (2):
target/riscv: Add vill check for whole
The RISC-V v spec 16.6 section says that the whole vector register move
instructions operate as if EEW=SEW. So it should depends on the vsew
field of vtype register.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 3 +--
1 file changed, 1 insertion(+), 2 deletions(-)
diff
.
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 78bd363310d..114ad87397f 100644
--- a/target/riscv/insn_trans
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 20
2 files changed, 23 insertions
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
Expose the properties of ShangMi Algorithm Suite related extensions
(Zvks, Zvksc, Zvksg).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8eae8d3e59c..1709df76a9b 100644
--- a/target/riscv
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou
---
disas/riscv.c | 137 ++
1 file changed, 137
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 7ea6ea050e9..e9458e574b9 100644
--- a/disas
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou
---
disas/riscv.c | 14 +-
disas/riscv.h | 1 +
2 files changed, 14 insertions(+), 1 deletion(-)
diff --git a/disas
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 992f8e0f7b0..8eae8d3e59c 100644
--- a/target/riscv/cpu.c
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou
---
disas/riscv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/disas/riscv.h b/disas/riscv.h
index 8abb578b515..b242d73b25e 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -274,6 +274,7 @@ enum
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 17 +
2 files changed, 20 insertions
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
target/riscv
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5099c786415..992f8e0f7b0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++-
1 file changed, 24
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a2881bfa383..5099c786415 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/ta
to ratified
extensions.
- Replaced TAB indentations with spaces in disas/riscv.c.
Max Chou (14):
target/riscv: Add cfg property for Zvkt extension
target/riscv: Expose Zvkt extension property
target/riscv: Add cfg property for Zvkb extension
target/riscv: Replace Zvbb checking by Zvkb
target
Add rv_fmt_vd_vs2_uimm format for vector crypto instructions.
Signed-off-by: Max Chou
---
disas/riscv.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/disas/riscv.h b/disas/riscv.h
index 8abb578b515..b242d73b25e 100644
--- a/disas/riscv.h
+++ b/disas/riscv.h
@@ -274,6 +274,7 @@ enum
This patch adds following v1.0.0 ratified vector crypto extensions
support to the RISC-V disassembler.
- Zvbb
- Zvbc
- Zvkb
- Zvkg
- Zvkned
- Zvknha
- Zvknhb
- Zvksed
- Zvksh
Signed-off-by: Max Chou
---
disas/riscv.c | 137 ++
1 file changed, 137
Vector crypto spec defines the Zvkt extension that included all of the
instructions of Zvbb & Zvbc extensions and some vector instructions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
target/riscv/tcg/tcg-cpu.c | 5 +
2 files changed, 6 insertions(+)
diff --git a/ta
Vector crypto spec defines the NIST algorithm suite related extensions
(Zvkn, Zvknc, Zvkng) combined by several vector crypto extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 20
2 files changed, 23 insertions
Expose the properties of NIST Algorithm Suite related extensions (Zvkn,
Zvknc, Zvkng).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 992f8e0f7b0..8eae8d3e59c 100644
--- a/target/riscv/cpu.c
extensions.
- Move vector crypto extensions from experimental extensions to ratified
extensions.
- Replace TAB indentations with spaces in disas/riscv.c.
https://github.com/riscv/riscv-crypto/releases/tag/v1.0.0
Max Chou (14):
target/riscv: Add cfg property for Zvkt extension
target/riscv: Expose
Expose the properties of ShangMi Algorithm Suite related extensions
(Zvks, Zvksc, Zvksg).
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8eae8d3e59c..1709df76a9b 100644
--- a/target/riscv
Because the vector crypto specification is ratified, so move theses
extensions from riscv_cpu_experimental_exts to riscv_cpu_extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 36 ++--
1 file changed, 18 insertions(+), 18 deletions(-)
diff --git
Add rv_codec_vror_vi for the vector crypto instruction - vror.vi.
The rotate amount of vror.vi is defined by combining seperated bits.
Signed-off-by: Max Chou
---
disas/riscv.c | 11 +++
disas/riscv.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/disas/riscv.c b/disas/riscv.c
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5099c786415..992f8e0f7b0 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -125,6 +125,7 @@ const RISCVIsaExtData isa_edata_arr
Replaces TABs with spaces, making sure to have a consistent coding style
of 4 space indentations.
Signed-off-by: Max Chou
---
disas/riscv.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index 5bfa9390c45..128478a3a09 100644
--- a/disas
Vector crypto spec defines the ShangMi algorithm suite related
extensions (Zvks, Zvksc, Zvksg) combined by several vector crypto
extensions.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 3 +++
target/riscv/tcg/tcg-cpu.c | 17 +
2 files changed, 20 insertions
The Zvkb extension is a proper subset of the Zvbb extension and includes
following instructions:
* vandn.[vv,vx]
* vbrev8.v
* vrev8.v
* vrol.[vv,vx]
* vror.[vv,vx,vi]
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvvk.c.inc | 37 +++-
1 file changed, 24
Signed-off-by: Max Chou
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index a2881bfa383..5099c786415 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -131,6 +131,7 @@ const RISCVIsaExtData isa_edata_arr
After vector crypto spec v1.0.0-rc3 release, the Zvkb extension is
defined as a proper subset of the Zvbb extension. And both the Zvkn and
Zvks shorthand extensions replace the included Zvbb extension by Zvkb
extnesion.
Signed-off-by: Max Chou
---
target/riscv/cpu_cfg.h | 1 +
target/riscv
The operator (fwmacc16) of vfwmaccbf16.vf helper function should be
replaced by fwmaccbf16.
Signed-off-by: Max Chou
---
target/riscv/vector_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 3fb05cc3d6e
On 2023/8/2 10:54 PM, Alistair Francis wrote:
On Tue, Jul 11, 2023 at 12:59 PM Max Chou wrote:
This patchset provides an implementation for Zvbb, Zvbc, Zvkned, Zvknh,
Zvksh, Zvkg, and Zvksed of the draft RISC-V vector cryptography
extensions as per the v20230620 version of the specification(1
On 2023/7/11 11:57 AM, Max Chou wrote:
On 2023/7/11 11:15 AM, Alistair Francis wrote:
On Mon, Jul 10, 2023 at 6:37 PM Max Chou wrote:
On 2023/7/8 5:25 PM, Daniel Henrique Barboza wrote:
Hi,
This patch breaks some gitlab runners because of this:
On 7/2/23 12:53, Max Chou wrote:
From
-authored-by: Lawrence Hunter
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter
Signed-off-by: Nazar Kazakov
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Exposed x-zvkg property]
[max.c...@sifive.com: Replaced uint
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
---
crypto/sm4.c | 10 ++
include/crypto/sm4.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/crypto/sm4.c b/crypto/sm4
-by: Max Chou
Reviewed-by: Frank Chang
[lawrence.hun...@codethink.co.uk: Moved SM4 functions from
crypto_helper.c to vcrypto_helper.c]
[nazar.kaza...@codethink.co.uk: Added alignment checks, refactored code to
use macros, and minor style changes]
Signed-off-by: Max Chou
---
target/riscv/cpu.c
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
---
include/crypto/sm4.h | 8
target/arm/tcg/crypto_helper.c | 10 ++
2 files changed, 10 insertions
`.
Co-authored-by: Kiran Ostrolenk
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk
Signed-off-by: Lawrence Hunter
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Exposed x-zvksh property]
---
target/riscv/cpu.c
From: Kiran Ostrolenk
Move some macros out of `vector_helper` and into `vector_internals`.
This ensures they can be used by both vector and vector-crypto helpers
(latter implemented in proceeding commits).
Signed-off-by: Kiran Ostrolenk
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov
Co-authored-by: Lawrence Hunter
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov
Signed-off-by: Lawrence Hunter
Signed-off-by: Kiran Ostrolenk
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c
Salmon
Signed-off-by: Kiran Ostrolenk
Signed-off-by: Dickon Hood
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Exposed x-zvbb property]
---
target/riscv/cpu.c | 12 ++
target/riscv/cpu_cfg.h | 1 +
target/riscv
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 28 +++--
1 file changed, 12 insertions(+), 16 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 7e194aae34a..5dfd524c7d2 100644
--- a/target
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.c...@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
[max.c...@sifive.com: Replaced bswap32 calls in aes
/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov
Co-authored-by: Max Chou
Signed-off-by: Nazar Kazakov
Signed-off-by: Lawrence Hunter
Signed-off-by: Max Chou
[max.c...@sifive.com: Exposed x-zvbc property]
---
target/riscv/cpu.c | 9
target/riscv/cpu_cfg.h
-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 52 +++--
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dfd524c7d2..a5562505531 100644
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 31 +---
Li
Signed-off-by: Max Chou
---
target/riscv/meson.build| 1 +
target/riscv/vector_helper.c| 201 +---
target/riscv/vector_internals.c | 81 +
target/riscv/vector_internals.h | 182 +
4 files changed, 265 insertions
Francis
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 62 +
1 file changed, 32 insertions(+), 30 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index c2f7527f53f
e, Nazar, Kiran, and William from
Codethink sponsored by SiFive, as well as Max Chou and Frank Chang
from SiFive.
https://github.com/riscv/riscv-crypto/releases
Thanks to those who have already reviewed:
Daniel Henrique Barboza dbarb...@ventanamicro.com
[PATCH v4 09/17] target/ri
On 2023/7/11 11:15 AM, Alistair Francis wrote:
On Mon, Jul 10, 2023 at 6:37 PM Max Chou wrote:
On 2023/7/8 5:25 PM, Daniel Henrique Barboza wrote:
Hi,
This patch breaks some gitlab runners because of this:
On 7/2/23 12:53, Max Chou wrote:
From: Nazar Kazakov
This commit adds support
On 2023/7/8 5:25 PM, Daniel Henrique Barboza wrote:
Hi,
This patch breaks some gitlab runners because of this:
On 7/2/23 12:53, Max Chou wrote:
From: Nazar Kazakov
This commit adds support for the Zvkg vector-crypto extension, which
consists of the following instructions:
* vgmul.vv
`.
Co-authored-by: Kiran Ostrolenk
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Kiran Ostrolenk
Signed-off-by: Lawrence Hunter
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Exposed x-zvksh property]
---
target/riscv/cpu.c
-authored-by: Lawrence Hunter
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Lawrence Hunter
Signed-off-by: Nazar Kazakov
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Exposed x-zvkg property]
---
target/riscv/cpu.c
Allows sharing of sm4_subword between different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Reviewed-by: Richard Henderson
Signed-off-by: Max Chou
---
include/crypto/sm4.h | 8
target/arm/tcg/crypto_helper.c | 10 ++
2 files changed, 10 insertions
From: Nazar Kazakov
Remove the redundant "vl == 0" check which is already included within the
vstart >= vl check, when vl == 0.
Signed-off-by: Nazar Kazakov
Reviewed-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 31 +---
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c...@sifive.com: Imported aes-round.h and exposed x-zvkned
property]
[max.c...@sifive.com: Fixed endian issues and replaced the vstart & vl
egs checking by helper function]
---
target/riscv/cpu.c |
Adds sm4_ck constant for use in sm4 cryptography across different targets.
Signed-off-by: Max Chou
Reviewed-by: Frank Chang
Signed-off-by: Max Chou
---
crypto/sm4.c | 10 ++
include/crypto/sm4.h | 1 +
2 files changed, 11 insertions(+)
diff --git a/crypto/sm4.c b/crypto/sm4
-by: Weiwei Li
Signed-off-by: Max Chou
---
target/riscv/insn_trans/trans_rvv.c.inc | 52 +++--
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dfd524c7d..a556250553 100644
/vcrypto_helper.c`.
Co-authored-by: Nazar Kazakov
Co-authored-by: Lawrence Hunter
[max.c...@sifive.com: Replaced vstart checking by TCG op]
Signed-off-by: Nazar Kazakov
Signed-off-by: Lawrence Hunter
Signed-off-by: Kiran Ostrolenk
Signed-off-by: Max Chou
Reviewed-by: Daniel Henrique Barboza
[max.c
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