Re: [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register

2021-02-03 Thread michael . nawrocki--- via
On 2/3/21 10:04 AM, Peter Maydell wrote: On Wed, 3 Feb 2021 at 14:50, Michael Nawrocki wrote: On 2/2/21 6:29 AM, Peter Maydell wrote: I see what you mean. Does QEMU support AArch64-only CPU models, and if so, is there a way to determine if the CPU has AArch32? We don't have any curr

[PATCH v2 1/1] target/arm: Fix SCR RES1 handling

2021-02-03 Thread michael . nawrocki--- via
The FW and AW bits of SCR_EL3 are RES1 only in some contexts. Force them to 1 only when there is no support for AArch32 at EL1 or above. The reset value will be 0x30 only if the CPU is AArch64-only; if there is support for AArch32 at EL1 or above, it will be reset to 0. Also adds helper function

[PATCH v2 0/1] target/arm: Fix SCR_EL3 migration issue

2021-02-03 Thread michael . nawrocki--- via
The SCR_EL3 register reset value (0) and the value produced when writing 0 via the scr_write function (set as writefn in the register struct) differ. This causes migration to fail. Ultimately, this is due to incorrect handling of context-dependent behavior of the RES1 bits of SCR_EL3. The FW and

Re: [PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register

2021-02-03 Thread michael . nawrocki--- via
On 2/2/21 6:29 AM, Peter Maydell wrote: On Thu, 28 Jan 2021 at 14:31, Mike Nawrocki wrote: Fixes an issue in migration where the reset value of SCR and the value produced by scr_write via the writefn for SCR_EL3 mismatch. Signed-off-by: Mike Nawrocki --- target/arm/helper.c | 2 +- 1 file

[PATCH 0/1] target/arm: Fix SCR_EL3 migration issue

2021-01-28 Thread michael . nawrocki--- via
The SCR_EL3 register reset value (0) and the value produced when writing 0 via the scr_write function (set as writefn in the register struct) differ. This causes migration to fail. I believe the solution is to specify a raw_writefn for that register. Failing invocation: $ qemu-system-arm -machin

[PATCH 1/1] target/arm: Add raw_writefn to SCR_EL3 register

2021-01-28 Thread michael . nawrocki--- via
Fixes an issue in migration where the reset value of SCR and the value produced by scr_write via the writefn for SCR_EL3 mismatch. Signed-off-by: Mike Nawrocki --- target/arm/helper.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/target/arm/helper.c b/target/arm/helper.c in

Re: [Qemu-devel] [PATCH v3 3/3] Add partial flash interleaving to AMD CFI devices

2017-11-28 Thread Michael Nawrocki
On 11/23/2017 08:46 AM, Peter Maydell wrote: On 13 November 2017 at 17:31, Mike Nawrocki wrote: This mirrors the interleaving support already in place in pflash_cfi01.c, using the max_device_width and device_width properties. Signed-off-by: Mike Nawrocki --- hw/block/pflash_cfi02.c | 244 ++

Re: [Qemu-devel] [PATCH v3 2/3] Enable 8-byte wide access to AMD CFI devices

2017-11-28 Thread Michael Nawrocki
On 11/23/2017 06:49 AM, Peter Maydell wrote: On 13 November 2017 at 16:14, Mike Nawrocki wrote: Signed-off-by: Mike Nawrocki --- hw/block/pflash_cfi02.c | 143 ++-- 1 file changed, 102 insertions(+), 41 deletions(-) diff --git a/hw/block/pflash_c

Re: [Qemu-devel] [PATCH v3 1/3] Switch AMD CFI flash to use new MMIO API

2017-11-28 Thread Michael Nawrocki
On 11/23/2017 06:27 AM, Peter Maydell wrote: On 23 November 2017 at 11:26, Peter Maydell wrote: On 13 November 2017 at 16:14, Mike Nawrocki wrote: Signed-off-by: Mike Nawrocki --- hw/block/pflash_cfi02.c | 97 + 1 file changed, 18 insertions

Re: [Qemu-devel] [PATCH v2 1/2] Fix eepro100 simple transmission mode

2017-11-16 Thread Michael Nawrocki
On 11/16/2017 12:43 PM, Thomas Huth wrote: On 16.11.2017 17:59, Thomas Huth wrote: On 06.11.2017 21:35, Mike Nawrocki wrote: The simple transmission mode was treating the area immediately after the transmit command block (TCB) as if it were a transmit buffer descriptor, when in reality it is si

Re: [Qemu-devel] [PATCH v2 2/2] Add new PCI ID for i82559a

2017-11-15 Thread Michael Nawrocki
On 11/14/2017 04:41 PM, Stefan Weil wrote: Am 06.11.2017 um 21:35 schrieb Mike Nawrocki: Adds a new PCI ID for the i82559a (0x8086 0x1030) interface. Enables this ID with a new property "use-alt-device-id" to preserve compatibility. Signed-off-by: Mike Nawrocki --- hw/net/eepro100.c| 12

Re: [Qemu-devel] [Qemu-block] [PATCH v2 0/1] Add 8-byte wide AMD flash support, partial interleaving

2017-11-13 Thread Michael Nawrocki
On 11/10/2017 06:12 PM, Paolo Bonzini wrote: On 10/11/2017 21:25, Mike Nawrocki wrote: This patch set does a few things. First, it switches the AMD CFI flash MMIO operations from the old MMIO API to the new one. Second, it enables 8-byte wide flash arrays. Finally, it adds flash interleaving usi

Re: [Qemu-devel] [PATCH v2 2/2] Add new PCI ID for i82559a

2017-11-07 Thread Michael Nawrocki
On 11/07/2017 11:12 AM, Michael S. Tsirkin wrote: On Mon, Nov 06, 2017 at 03:35:20PM -0500, Mike Nawrocki wrote: Adds a new PCI ID for the i82559a (0x8086 0x1030) interface. Enables this ID with a new property "use-alt-device-id" to preserve compatibility. Signed-off-by: Mike Nawrocki ---

Re: [Qemu-devel] [PATCH 2/2] Add i82559a eepro100 interface

2017-11-06 Thread Michael Nawrocki
On 11/01/2017 11:32 AM, Michael S. Tsirkin wrote: On Wed, Nov 01, 2017 at 02:48:17PM +, Nawrocki, Michael wrote: On 10/31/17, 13:50, "Dr. David Alan Gilbert" wrote: * Mike Nawrocki (michael.nawro...@gtri.gatech.edu) wrote: > Signed-off-by: Mike Nawrocki > --- > hw/ne

Re: [Qemu-devel] [PATCH] Enable 8-byte wide MMIO for 16550 serial devices

2017-11-06 Thread Michael Nawrocki
On 11/02/2017 04:04 PM, Paolo Bonzini wrote: - Original Message - From: "Philippe Mathieu-Daudé" To: "Paolo Bonzini" , "Mike Nawrocki" , "Avi Kivity" , "Peter Maydell" , "Konrad Frederic" Cc: qemu-devel@nongnu.org, m...@redhat.com Sent: Thursday, November 2, 2017 8:28:09 PM Subject