d-off-by: Nicholas Piggin
---
include/sysemu/runstate.h | 1 +
replay/replay.c | 2 ++
system/runstate.c | 31 ---
3 files changed, 31 insertions(+), 3 deletions(-)
diff --git a/include/sysemu/runstate.h b/include/sysemu/runstate.h
index e210a
The v12 format support for replay-dump has a few issues still. This
fixes async decoding; adds event, shutdown, and end decoding; fixes
audio in / out events, fixes checkpoint checking of following async
events.
Reviewed-by: Alex Bennée
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py
An error path missed setting *errp, which can cause a NULL deref.
Reviewed-by: Alex Bennée
Signed-off-by: Nicholas Piggin
---
migration/savevm.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/migration/savevm.c b/migration/savevm.c
index 85958d7b09..6bb404b9c8 100644
--- a/migration
This runs replay-dump.py after recording a trace, and fails the test if
the script fails.
replay-dump.py is modified to exit with non-zero if an error is
encountered while parsing, to support this.
Reviewed-by: Alex Bennée
Reviewed-by: Pavel Dovgalyuk
Signed-off-by: Nicholas Piggin
v5
tting QEMU_CHAR_FEATURE_REPLAY on the base chardev fixes the problem.
Reviewed-by: Alex Bennée
Signed-off-by: Nicholas Piggin
---
chardev/char.c | 71 +++---
1 file changed, 50 insertions(+), 21 deletions(-)
diff --git a/chardev/char.c b/chardev/char.c
Sort decoder functions to be ascending in order of event number,
same as the decoder tables.
Reviewed-by: Alex Bennée
Signed-off-by: Nicholas Piggin
---
scripts/replay-dump.py | 56 +-
1 file changed, 28 insertions(+), 28 deletions(-)
diff --git a
esn't keep breaking.
Thanks,
Nick
Nicholas Piggin (10):
scripts/replay-dump.py: Update to current rr record format
scripts/replay-dump.py: rejig decoders in event number order
tests/avocado: excercise scripts/replay-dump.py in replay tests
replay: allow runstate shutdown->running wh
This is not a clean patch, but does fix a problem I hit with TB
invalidation due to the target software writing to memory with TBs.
Lockup messages are triggering in Linux due to page clearing taking a
long time when a code page has been freed, because it takes a lot of
notdirty notifiers, which m
On Thu Aug 8, 2024 at 2:46 AM AEST, Philippe Mathieu-Daudé wrote:
> On 7/8/24 06:08, Richard Henderson wrote:
> > Ensure the code structure is the same for matching constraints
> > and emitting code, lest we allow constants that cannot be
> > trivially tested.
> >
> > Cc: qemu-sta...@nongnu.org
>
: 24bd283bccb33 ("ppc/pnv: Implement ADU access to LPC space")
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_adu.c | 12
1 file changed, 12 insertions(+)
diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c
index 81b7d6e526..f636dedf79 100644
--- a/hw/ppc/pnv_adu.c
+++ b/hw/ppc
In Book-S / Power processors, the performance monitor interrupts are
driven by the MMCR0[PMAO] bit, which is level triggered and not cleared
by the interrupt.
Others may have different performance monitor architecture, but none of
those are implemented by QEMU.
Signed-off-by: Nicholas Piggin
The HFSCR defines were being encoded as bit masks, but the users
expect (and analogous FSCR defines are) bit numbers.
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index bd32a1a5f8
Hash virtual real mode addressing is defined by the architecture
to not perform virtual page class key protection checks.
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash64.c | 9 -
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/ppc/mmu-hash64.c b/target/ppc
Doorbell exceptions are not not cleared when they cause a wake from
powersave state, only when they take the corresponding interrupt.
The sreset-on-wake logic must avoid clearing the interrupt in this
case.
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 17 +
1
29 (partially)
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h | 1 +
hw/ppc/pnv_lpc.c | 10 --
2 files changed, 9 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 321ed2da75..bd32a1a5f8 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@
This fixes LPC serirq Coverity issues introduced in the merge
window that Cedric reported. Also fixes for an assorted bunch of
emulation issues recently turned up when running PowerVM firmware
on the model.
Thanks,
Nick
Nicholas Piggin (7):
ppc/pnv: Fix LPC serirq routing calculation
ppc
A typo in the loop over SMT threads to set irq level for doorbells
when storing to DPDES meant everything was aimed at the CPU executing
the instruction.
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/ppc
ere incorrectly specified because of ppc bit numbering
fun. Coverity detected this as an always-zero expression.
Reported-by: Cédric Le Goater
Resolves: Coverity CID 1558829 (partially)
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_lpc.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
d
Now that exec_command doesn't incorrectly consume console output,
and guest time is set correctly, ppc_hv_tests.py is working more
reliably. Try marking it non-flaky.
Signed-off-by: Nicholas Piggin
---
tests/avocado/ppc_hv_tests.py | 1 -
1 file changed, 1 deletion(-)
diff --git a/
This fixes an issue with exec_command eating console output and causing
the ppc_hv_tests.py to fail. A few other tests also use exec_command but
I didn't see any that subsequently checked console output.
Thanks,
Nick
Nicholas Piggin (2):
tests/avocado: exec_command should not consume co
.
This solves occasional hangs in ppc_hv_tests.py, usually when run on KVM
hosts that are fast enough to output important lines quickly enough to be
consumed by exec_command, so they get missed by subsequent wait for
pattern calls.
Signed-off-by: Nicholas Piggin
---
tests/avocado/avocado_qemu
Thanks for doing this.
I have a fix for this problem, it's a bug with the test harness
code but was not merged yet. I'll re-send it.
Thanks,
Nick
On Wed Jul 31, 2024 at 3:03 AM AEST, Daniel P. Berrangé wrote:
> From: Thomas Huth
>
> Note: The original Avocado test seems currently to be broken,
On Sat Aug 3, 2024 at 6:40 PM AEST, Michael Tokarev wrote:
> Hi!
>
> It's been a long time since everyone's fighting with u-boot-sam460ex code
> which is
> very bad, suffers from countless issues.
>
> For one, it does not compile for quite a long time with current compilers.
>
> For example, here
On Thu Jul 25, 2024 at 7:21 AM AEST, Michael Kowal wrote:
> From: Frederic Barrat
>
> The cache watch facility uses the same register interface to handle
> entries in the NVP, NVG and NVC tables. A bit-field in the 'watchX
> specification' register tells the table type. So far, that bit-field
> wa
Hey Aditya,
Thanks for this, I think since we're past the hard freeze it may have
to wait until next release. If it was simply a new PRV maybe it could
be squeezed in, but since it has this PCR tangle then it's a bit
non-trivial. Apologies I didn't get to reviewing it earlier, will get
it in 9.2.
On Mon Jul 29, 2024 at 7:43 PM AEST, Philippe Mathieu-Daudé wrote:
> Hi Nick,
>
> On 26/7/24 01:52, Nicholas Piggin wrote:
> > Apologies this is so late after soft-freeze, apologies. I was waiting
> > on "accel/kvm: Extract common KVM vCPU {creation,parking} code&
On Fri Jul 26, 2024 at 7:11 PM AEST, Thomas Huth wrote:
> On 25/07/2024 17.40, Nicholas Piggin wrote:
> > In Gitlab CI, some ppc64 multi-threaded tcg tests crash when run in the
> > clang-user job with an assertion failure in glibc that seems to
> > indicate corruption
On Fri Jul 26, 2024 at 7:11 PM AEST, Thomas Huth wrote:
> On 25/07/2024 17.40, Nicholas Piggin wrote:
> > In Gitlab CI, some ppc64 multi-threaded tcg tests crash when run in the
> > clang-user job with an assertion failure in glibc that seems to
> > indicate corruption
using the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode| 10 ++
target/ppc/translate/vsx-impl.c.inc | 199
target/ppc/translate/vsx-ops.c.inc |
: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vmx-impl.c.inc | 42 ++---
1 file changed, 20 insertions(+), 22 deletions(-)
diff --git a/target/ppc/translate/vmx-impl.c.inc
b/target/ppc/translate/vmx-impl.c.inc
index
so added a new function do_ea_calc_ra to calculate the effective address :
EA <- (RA == 0) ? 0 : GPR[RA], which is now used by the above-said insns,
and shall be used later by (p){lx, stx}vp insns.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
[np: Fix 32-bit build]
Signed-off
From: BALATON Zoltan
Pass raddr and prot in function parameters instead
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 17 +
1 file changed, 9 insertions(+), 8 deletions(-)
diff --git a/target/ppc
From: BALATON Zoltan
This function is a simple shared function, move it to other similar
static inline functions in the header.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 7 ---
target/ppc/mmu-hash32.h | 6
the header.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_vhyp_mmu.c| 21
target/ppc/mmu-book3s-v3.h | 40 ---
target/ppc/mmu-hash64.c| 49
From: Frederic Barrat
Moving xive2_nvp_pic_print_info() to align with the other "pic_print_info"
functions.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c
Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index b21f52290f..799d2ced9b 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -98,13 +98,12
From: Chalapathi V
In this commit target specific dependency from include/hw/ppc/pnv_xscom.h
has been removed so that pnv_xscom.h can be included outside hw/ppc.
Signed-off-by: Chalapathi V
Reviewed-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Signed-off-by: Nicholas Piggin
From: BALATON Zoltan
Move the parts not needed outside of mmu-radix64.c from the header to
the C file to leave only parts in the header that need to be exported.
Also drop unneded include of this header.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
-by: Cédric Le Goater
Reviewed-by: Glenn Miles
[np: Fix FDT macro compile for qtest]
Signed-off-by: Nicholas Piggin
---
hw/ppc/Kconfig| 3 +
hw/ssi/Kconfig| 4 +
hw/ssi/meson.build| 1 +
hw/ssi/pnv_spi.c | 215
From: Chinmay Rath
No need for a full comparison; xor produces non-zero bits for QC just fine.
Suggested-by: Richard Henderson
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vmx-impl.c.inc | 14 +++---
1 file
From: BALATON Zoltan
This function is only called once and we can make the caller simpler
by inlining it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 71 +
1 file changed, 22
Power CPUs have an execution control facility that can pause, resume,
and cause NMIs, among other things. Add a function that will nmi a CPU
and resume it if it was paused, in preparation for implementing the
control facility.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw
From: BALATON Zoltan
Replace some BAT related constants with defines from mmu-hash32.h
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions
larly with respect
to QME and special wakeup) that it is not trivial to implement POWER9
support by reusing the code.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_core.c | 89 ---
include/hw/ppc/pnv_core.h | 3 ++
2 files changed, 87 insertions(+), 5
From: BALATON Zoltan
Drop includes from header that is not needed by the header itself and
only include them from C files that really need it.
Signed-off-by: BALATON Zoltan
Acked-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-book3s-v3.h | 3 ---
target/ppc/mmu-hash64
From: BALATON Zoltan
The ppc6xx_tlb_check() relies on the caller to initialise raddr field
in ctx. Move this init from the only caller into the function.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 4 ++--
1 file
From: BALATON Zoltan
Invert conditions to avoid deep nested ifs and return early instead.
Remove some obvious comments that don't add more clarity.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c
From: BALATON Zoltan
This is used only once and can be inlined.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 19 ---
1 file changed, 4 insertions(+), 15 deletions(-)
diff --git a/target/ppc/mmu
Power9 CPUs have a core thread state register accessible via SPRC/SPRD
indirect registers. This register includes a bit for big-core mode,
which skiboot requires.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/misc_helper.c | 17 +
1 file changed
From: BALATON Zoltan
Reorganise ppc_hash32_pp_prot() swapping the if legs so it does not
test for negative first and clean up to make it shorter. Also rename
it to ppc_hash32_prot().
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu
ble.
This patch allows to read/write entries in the NVG and NVC table as
well.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 49 +++--
1 file c
From: Chinmay Rath
Those functions are used to ld/st data to and from Altivec registers,
in 64 bits chunks, and are only used in vmx-impl.c.inc file,
hence the clean-up movement.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc
d-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/xive2.c | 7 +--
include/hw/ppc/xive2_regs.h | 7 +++
2 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/hw/intc/xive2.c b/hw/intc/xiv
From: BALATON Zoltan
Pass raddr and prot in function parameters instead.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 +-
1 file changed, 13 insertions(+), 13 deletions(-)
diff --git a
From: BALATON Zoltan
Add a function to get key bit from SR and use it instead of open coded
version.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 9 ++---
target/ppc/mmu-hash32.h | 5 +
target/ppc
27;-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/insn32.decode| 11
target/ppc/translate/vsx-impl.c.inc | 39 +
target/ppc/translate/vsx-ops.c.inc | 11
3 fil
psi#0:lpc_serirq_mux1
Whereas they previously turn up on lpchc.
Reviewed-by: Glenn Miles
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 36 +--
hw/ppc/pnv_lpc.c | 128 ---
include/hw/ppc/pnv_lpc.h | 14 -
3 files changed, 148 inser
w works sufficiently to run Linux,
with a single socket. Multi-threaded KVM guests still have problems,
as does multi-socket Linux boot.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 38 ++
hw/ppc/pnv
bit shift
1001- - No compression
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 20
hw/intc/pnv_xive2_regs.h | 2 ++
2 files changed, 22 insertions(+)
diff
at
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 5 +
1 file changed, 5 insertions(+)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index 08b9166a09..9fbd44f974 100644
--- a/hw/intc/pnv_xive2.c
+++ b/hw/intc/p
definitions are still shared, since the VST tables can be set
through both the VC and/or PC, they are dynamically re-mapped in
memory by first deleting the memory subregion.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
the same, which were captured with the '-d in_asm,op' flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/fpu_helper.c | 44 ++--
target/ppc/helper.h | 44 ++--
From: BALATON Zoltan
Instead of passing around ptem in context use it once in the same
function so it can be removed from mmu_ctx_t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 23 ++-
1 file
From: BALATON Zoltan
The ptev variable in ppc6xx_tlb_pte_check() is used only once and just
obfuscates an otherwise clear value. Get rid of it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 5 ++---
1 file changed, 2
From: BALATON Zoltan
The eaddr field of mmu_ctx_t is set once but never used so can be
removed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/target/ppc/mmu_common.c
Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 18 +-
target/ppc/mmu-hash32.h | 14 +++
target/ppc/mmu_common.c | 52 ++---
3 files changed, 27 insertions(+), 57 deletions(-)
diff --git a/target/ppc/mmu-hash32.c b/target
From: BALATON Zoltan
In ppc6xx_tlb_pte_check() the pteh variable is used only once to
compare to the h parameter of the function. Inline its value and use
pteh name for the function parameter which is more descriptive.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by
From: BALATON Zoltan
In mmu6xx_get_physical_address() the switch handles all cases so the
default is never reached and can be dropped. Also group together cases
which just return -4.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc
From: BALATON Zoltan
This function is used only once and does not add more clarity than
doing it inline.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu-hash32.c | 18 +-
1 file changed, 5 insertions(+), 13
From: BALATON Zoltan
Instead of using a local ret variable return directly and remove the
local.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 10 +++---
1 file changed, 3 insertions(+), 7 deletions(-)
diff --git
-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/translate/vsx-impl.c.inc | 74 +
1 file changed, 33 insertions(+), 41 deletions(-)
diff --git a/target/ppc/translate/vsx-impl.c.inc
b/target/ppc/translate/vsx-impl.c.inc
index 26ebf3fedf..40a87d
by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 85 +--
hw/ppc/pnv_core.c | 10 +++--
include/hw/ppc/pnv_chip.h | 4 +-
3 files changed, 64 insertions(+), 35 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/p
#x27; flag.
Signed-off-by: Chinmay Rath
Reviewed-by: Richard Henderson
Signed-off-by: Nicholas Piggin
---
target/ppc/fpu_helper.c | 16 +-
target/ppc/helper.h | 16 +-
target/ppc/insn32.decode| 12
target/ppc/translate/vsx-impl.
ok like an SMT8 core in TCG. Then the xscom and pervasive
models mostly do not need to differentiate big and small core modes.
This change adds initial mode bits and QEMU topology handling to
split SMT8 cores into 2xSMT4 cores.
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c
From: BALATON Zoltan
Pass it as a parameter instead. Also use named constants instead of
hex values when extracting bits from SR.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 24
1 file
From: BALATON Zoltan
The ptem variable in ppc6xx_tlb_pte_check() is used only once,
simplify by removing it as the value is already clear itself without
adding a local name for it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc
From: BALATON Zoltan
Completely get rid of mmu_ctx_t after converting the remaining
functions to pass raddr and prot without the context struct.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 25
From: BALATON Zoltan
Rename parameter of get_bat_6xx_tlb() from virtual to eaddr to match
other functions.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 18 +-
1 file changed, 9 insertions(+), 9
From: BALATON Zoltan
Return hash value via a parameter and remove it from mmu_ctx.t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 19 ---
1 file changed, 8 insertions(+), 11 deletions(-)
diff --git a
Add helpers for TCG code to determine if there are SMT siblings
sharing per-core and per-lpar registers. This simplifies the
callers and makes SMT register topology simpler to modify with
later changes.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu.h
From: Chalapathi V
In this commit Write a qtest pnv-spi-seeprom-test to check the
SPI transactions between spi controller and seeprom device.
Signed-off-by: Chalapathi V
Acked-by: Cédric Le Goater
Reviewed-by: Caleb Schlossin
Signed-off-by: Nicholas Piggin
---
tests/qtest/meson.build
-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 251 +--
hw/intc/pnv_xive2_regs.h | 90 ++
2 files changed, 305 insertions(+), 36 deletions(-)
diff --git a/hw/intc/pnv_xive2.c b/h
implements the v3.0 semantics, which can make
multi-threaded POWER8 hang when booting Linux (due to IPIs
failing). This change adds v2.07 semantics.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
target/ppc/excp_helper.c | 74
1 file
operation is requested.
Co-authored-by: Glenn Miles
Signed-off-by: Glenn Miles
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 154 +-
hw/intc/pnv_xive2_regs.h | 16
include/hw/ppc
From: Akihiko Odaki
This fixes LeakSanitizer warnings.
Signed-off-by: Akihiko Odaki
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Michael S. Tsirkin
Signed-off-by: Nicholas Piggin
---
hw/ppc/spapr_vof.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ppc
From: BALATON Zoltan
In mmu6xx_get_physical_address() tagtet_page_bits local is declared
only to use TARGET_PAGE_BITS once. Drop the unneeded variable.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 4 +---
1 file
From: BALATON Zoltan
Pass it as a function parameter and remove it from mmu_ctx_t.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 26 ++
1 file changed, 14 insertions(+), 12 deletions(-)
diff
From: BALATON Zoltan
The mmask local variable is a less descriptive local name for a
constant. Drop it and use the constant directly in the two places it
is needed.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
---
target/ppc/mmu_common.c | 5
From: Frederic Barrat
In XIVE Gen 2 there were some minor changes to the TIMA header that were
updated when printed.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/xive.c | 12 +---
1 file changed
hread 0 of a core.
Move the state out into PnvCore and share it among all threads.
Reviewed-by: Harsh Prateek Bora
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_chiptod.c | 7 ++---
include/hw/ppc/pnv_core.h| 17 ++
target/ppc/cpu.h | 21 -
targe
#x27; flag.
Reviewed-by: Richard Henderson
Signed-off-by: Chinmay Rath
Signed-off-by: Nicholas Piggin
---
target/ppc/helper.h | 24 +--
target/ppc/insn32.decode| 16 ++
target/ppc/int_helper.c | 22 +--
target/ppc/translate/vmx-impl.c
: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv_core.c | 2 ++
hw/ppc/spapr_cpu_core.c | 4
target/ppc/cpu.h| 9 +
3 files changed, 11 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index 28ca61926d..7bda29b9c7 100644
From: BALATON Zoltan
This function is used only once, its return value is ignored and one
of its parameter is a return value from a previous call. It is better
to inline it in the caller and remove it.
Signed-off-by: BALATON Zoltan
Reviewed-by: Nicholas Piggin
Signed-off-by: Nicholas Piggin
XSCOM bridge
implementation, and pnv_adu.c implements the ADU registers and other
functions.
So far, just the ADU no-op registers in the pnv_xscom.c default handler
are moved over to the adu model.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/meson.build
From: Shivaprasad G Bhat
The patch enables DEXCR migration by hooking with the
"KVM one reg" ID KVM_REG_PPC_DEXCR.
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Nicholas Piggin
---
target/ppc/cpu_init.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/
other VST tables.
Signed-off-by: Frederic Barrat
Signed-off-by: Michael Kowal
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/intc/pnv_xive2.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c
index c3b5bfe61f..08b9166a09 10064
POWER10 has a quirk in its ChipTOD addressing that requires the even
small-core to be selected even when programming the odd small-core.
This allows skiboot chiptod init to run in big-core mode.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 7
lenn Miles
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 21 -
hw/ssi/pnv_spi.c | 8
include/hw/ppc/pnv_chip.h | 3 +++
3 files changed, 31 insertions(+), 1 deletion(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pn
Big-core implementation is complete, so expose it as a machine
property that may be set with big-core=on option on powernv9 and
powernv10 machines.
Reviewed-by: Cédric Le Goater
Signed-off-by: Nicholas Piggin
---
hw/ppc/pnv.c | 61 ++--
1 file
From: Shivaprasad G Bhat
This is a placeholder change for these SPRs until the full linux
header update.
Signed-off-by: Shivaprasad G Bhat
Signed-off-by: Nicholas Piggin
---
linux-headers/asm-powerpc/kvm.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/linux-headers/asm-powerpc/kvm.h
101 - 200 of 1276 matches
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