On Thu, 01 Feb 2024 10:57:00 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40
On Thu, 01 Feb 2024 09:39:22 PST (-0800), alex.ben...@linaro.org wrote:
Palmer Dabbelt writes:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> D
handles open source implementations).
Link: https://github.com/riscv/riscv-isa-manual/pull/1213
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 16
target/riscv/cpu_vendorid.h | 3 +++
2 files changed, 19 insertions(+)
diff --git a/target/riscv/cpu.c b/target/riscv
On Wed, 31 Jan 2024 06:39:25 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
I'm not 100% sure this is a sane GSoC idea, as it's a bit open ended and
might have some tricky parts
On Tue, 30 Jan 2024 17:26:11 PST (-0800), alistai...@gmail.com wrote:
On Wed, Jan 31, 2024 at 10:30 AM Palmer Dabbelt wrote:
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
> On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
>>
>> On Mon, 15 Jan 2024 08:3
On Tue, 30 Jan 2024 12:28:27 PST (-0800), stefa...@gmail.com wrote:
On Tue, 30 Jan 2024 at 14:40, Palmer Dabbelt wrote:
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
> Dear QEMU and KVM communities,
> QEMU will apply for the Google Summer of Code and Outreachy inte
On Mon, 15 Jan 2024 08:32:59 PST (-0800), stefa...@gmail.com wrote:
Dear QEMU and KVM communities,
QEMU will apply for the Google Summer of Code and Outreachy internship
programs again this year. Regular contributors can submit project
ideas that they'd like to mentor by replying to this email
>> Â Â Â .text
>> ENTRY(__vdso_rt_sigreturn)
>> Â Â Â .cfi_startproc
>> Â Â Â .cfi_signal_frame
>> Â Â Â li a7, __NR_rt_sigreturn
>> Â Â Â ecall
>> Â Â Â .cfi_endproc
>> ENDPROC(__vdso_rt_sigreturn)
>
> Perhaps it's not require
+pc = host_sigbus_handler(cpu, info, uc);
sync_sig = true;
break;
case SIGILL:
--
2.40.1
Either way,
Reviewed-by: Palmer Dabbelt
Thanks!
Support for probing the Zicboz block size landed in Linux 6.6, which was
released a few weeks ago. This provides the user-configured block size
when Zicboz is enabled.
Signed-off-by: Palmer Dabbelt
---
linux-user/syscall.c | 6 ++
1 file changed, 6 insertions(+)
diff --git a/linux-user
On Thu, 26 Oct 2023 16:03:28 PDT (-0700), turt...@utexas.edu wrote:
From 4af1fca6e5c99578a5b80b834c22b70f6419639f Mon Sep 17 00:00:00 2001
From: Brendan Sweeney
Date: Thu, 26 Oct 2023 17:01:29 -0500
Subject: [PATCH] Support for the RISCV Zalasr extension
This doesn't have a commit body. At
On Sat, 09 Sep 2023 00:18:02 PDT (-0700), pbonz...@redhat.com wrote:
Il sab 9 set 2023, 03:35 Atish Patra ha scritto:
On Fri, Sep 8, 2023 at 3:29 AM Paolo Bonzini wrote:
>
> Queued, thanks.
>
I didn't realize it was already queued. Gmail threads failed me this time.
@Paolo Bonzini : Can you
On Thu, 10 Aug 2023 08:31:46 PDT (-0700), ajo...@ventanamicro.com wrote:
On Mon, Jul 31, 2023 at 11:33:20AM -0700, Richard Bagley wrote:
The recent commit 36df75a0a9 corrected one aspect of LUI disassembly
by recovering the immediate argument from the result of LUI with a
shift right by 12.
On Tue, 08 Aug 2023 14:10:54 PDT (-0700), dbarb...@ventanamicro.com wrote:
On 8/8/23 17:52, Palmer Dabbelt wrote:
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported
On Tue, 08 Aug 2023 11:45:49 PDT (-0700), Vineet Gupta wrote:
On 8/8/23 11:29, Richard Henderson wrote:
On 8/8/23 11:17, Vineet Gupta wrote:
zicond is now codegen supported in both llvm and gcc.
It is still not in
https://wiki.riscv.org/display/HOME/Recently+Ratified+Extensions
Right,
On Tue, 11 Jul 2023 09:43:48 PDT (-0700), Richard Henderson wrote:
Hiya,
This breakage crept in while cross-riscv64-system was otherwise broken in
configure:
https://gitlab.com/qemu-project/qemu/-/jobs/4633277557#L4165
../target/riscv/kvm.c:209:38: error: ‘KVM_RISCV_ISA_EXT_ZICBOZ’
On Fri, 30 Jun 2023 04:14:09 PDT (-0700), rory.opensou...@gmail.com wrote:
RISCV architecture supports an optional big endian mode of operation.
In this mode, data accesses are treated as big endian, while code is
always in little endian format. This is similar to how the ARM
architecture treats
pairs, arg2);
> +unlock_user(host_pairs, arg1, sizeof(*host_pairs) * (size_t)arg2);
> +return 0;
> +}
> +#endif /* TARGET_NR_riscv_hwprobe */
> +
> #if defined(TARGET_NR_pivot_root) && defined(__NR_pivot_root)
> _syscall2(int, pivot_root, const char *, new_root, const char *, put_old)
> #endif
> @@ -13571,6 +13712,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env,
> int num, abi_long arg1,
> return ret;
> #endif
>
> +#if defined(TARGET_NR_riscv_hwprobe)
> +case TARGET_NR_riscv_hwprobe:
> +return do_riscv_hwprobe(cpu_env, arg1, arg2, arg3, arg4, arg5);
> +#endif
> +
> default:
> qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num);
> return -TARGET_ENOSYS;
> --
> 2.39.2
Reviewed-by: Palmer Dabbelt
riscv_hwprobe() hasn't been released yet, but it's in Linus' tree so
unless something unforseen happens it should show up in 6.4 in a few
weeks.
f HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN
{ "/proc/net/route", open_net_route, is_proc },
#endif
-#if defined(TARGET_SPARC) || defined(TARGET_HPPA)
+#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
Reviewed-by: Palmer Dabbelt
Thanks!
TARGET_SPARC) || defined(TARGET_HPPA) || defined(TARGET_RISCV)
{ "/proc/cpuinfo", open_cpuinfo, is_proc },
#endif
#if defined(TARGET_M68K)
Aside from that,
Reviewed-by: Palmer Dabbelt
Thanks!
On Wed, 03 May 2023 04:13:55 PDT (-0700), sch...@suse.de wrote:
On Mai 02 2023, Andreas Schwab wrote:
None of the currently defined cpus are non-GC cpus (except sifive_e, but
that is not suitable for user-space anyway), and there doesn't appear to
be any properties defined for changing the
On Tue, 02 May 2023 06:44:00 PDT (-0700), sch...@suse.de wrote:
Signed-off-by: Andreas Schwab
---
linux-user/syscall.c | 30 --
1 file changed, 28 insertions(+), 2 deletions(-)
diff --git a/linux-user/syscall.c b/linux-user/syscall.c
index 69f740ff98..c72456a34b
---
1 file changed, 8 insertions(+), 3 deletions(-)
Reviewed-by: Palmer Dabbelt
Though this made me think: it'd be nice to have some sort of
"aggressively do odd things for VTA/VMA" mode in QEMU, as that could
help shake out bugs in software.
On Fri, 10 Mar 2023 10:03:23 PST (-0800), alex.ben...@linaro.org wrote:
Whatever they are up to a number of people for the company are
contributing to QEMU so lets group them together.
Signed-off-by: Alex Bennée
Cc: Atish Patra
Cc: Dao Lu
Cc: Andrew Bresticker
Cc: Palmer Dabbelt
Cc: Vineet
Reviewed-by: Alistair Francis
Reviewed-by: Bin Meng
Reviewed-by: Frank Chang
Message-ID: <20230303131252.892893-3-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 21 +++--
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/target
49-1-ivan.klo...@syntacore.com>
Signed-off-by: Palmer Dabbelt
---
disas/riscv.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/disas/riscv.c b/disas/riscv.c
index ddda687c13..544558 100644
--- a/disas/riscv.c
+++ b/disas/riscv.c
@@ -1645,7 +1645,7 @@ const rv_opcode_
-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 4 ++
target
ory configurations:
-cpu rv64,sv48=on,sv48=off # Linux will boot using sv39 scheme
Co-Developed-by: Ludovic Henry
Signed-off-by: Ludovic Henry
Signed-off-by: Alexandre Ghiti
Reviewed-by: Andrew Jones
Reviewed-by: Bin Meng
Acked-by: Alistair Francis
Reviewed-by: Frank Chang
Message-ID: <2023
7-2-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 5 +
include/hw/riscv/virt.h | 2 ++
2 files changed, 7 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 26eb81d036..5a059489b5 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Bin Meng
Message-ID: <20230302091406.407824-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 11 +++
1 file changed, 11 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 4f81
-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Reviewed-by: Weiwei Li
Message-ID: <20230224132536.552293-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn32.decode | 1 +
: <20230303131252.892893-6-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 19 +++
1 file changed, 11 insertions(+), 8 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 7f70fa11a1..26eb81d036 100644
--- a/hw/riscv/virt.c
+++ b/hw
-build.c and enable
building this infrastructure.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-5-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/Kconfig | 1 +
hw/riscv/meson.build | 1 +
hw/riscv/virt-acpi-b
to be replaced by
cpu_by_arch_id which performs lookup based on the sparse physical hart IDs.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-3-mchit...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
h
The following changes since commit 2946e1af2704bf6584f57d4e3aec49d1d5f3ecc0:
configure: Disable thread-safety warnings on macOS (2023-03-04 14:03:46 +)
are available in the Git repository at:
https://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230306
for you to fetch
From: Sunil V L
Add Multiple APIC Description Table (MADT) with the
RINTC structure for each cpu.
Signed-off-by: Sunil V L
Acked-by: Alistair Francis
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-6-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/risc
From: Sunil V L
RISC-V ACPI platforms need to provide RISC-V Hart Capabilities
Table (RHCT). Add this to the ACPI tables.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-7-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/vir
From: Mayuresh Chitale
Implement the callback for getting the architecture-dependent CPU ID ie
mhartid.
Signed-off-by: Mayuresh Chitale
Signed-off-by: Anup Patel
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230303065055.915652-2-mchit...@ventanamicro.com>
Signed-off-by: Palmer D
-by: Weiwei Li
Co-developed-by: Philipp Tomsich
Signed-off-by: Christoph Muellner
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20230224132536.552293-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 3 +
target/riscv
xgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 93 ++
target/riscv/cpu.h | 8 +++-
2 files changed, 75 insertions(+), 26 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e1e8057836..1e97473af2 100644
--- a/
From: Sunil V L
Initialize the ACPI tables if the acpi option is not
disabled.
Signed-off-by: Sunil V L
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-8-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 4
1 file c
From: Sunil V L
ACPI will be enabled by default. Add a switch to turn off
for testing and debug purposes.
Signed-off-by: Sunil V L
Reviewed-by: Andrew Jones
Message-ID: <20230302091212.999767-3-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c
Message-ID: <20230302091212.999767-4-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 2 ++
include/hw/riscv/virt.h | 1 +
2 files changed, 3 insertions(+)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 90579a4c0e..aed303e1e6 100644
--- a/hw
-ID: <20230302091212.999767-9-suni...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 18 --
1 file changed, 12 insertions(+), 6 deletions(-)
diff --git a/MAINTAINERS b/MAINTAINERS
index 011fd85a09..26bf14b57b 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -
, as was suggested by the template. It also
adds the python3 package via apt, as OpenSBI requires that to build.
Reviewed-by: Bin Meng
Message-ID: <20230303202448.11911-2-pal...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
.gitlab-ci.d/opensbi.yml| 4 ++--
.gitlab-ci.d/opensbi/Dockerfile |
-by: Andrew Jones
Reviewed-by: Bin Meng
Message-ID: <20230303131252.892893-2-alexgh...@rivosinc.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 29 +++--
1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
On Sun, 05 Mar 2023 15:45:05 PST (-0800), Palmer Dabbelt wrote:
On Thu, 02 Mar 2023 01:12:04 PST (-0800), suni...@ventanamicro.com wrote:
This series adds the basic ACPI support for the RISC-V virt machine.
Currently only RINTC interrupt controller specification is approved by the
UEFI forum
On Mon, 06 Mar 2023 09:50:49 PST (-0800), dbarb...@ventanamicro.com wrote:
On 3/5/23 20:34, Palmer Dabbelt wrote:
On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexgh...@rivosinc.com wrote:
This introduces new properties to allow the user to set the satp mode,
see patch 3 for full syntax
str(buffer, "mmu") != NULL) {
+assert(strcmp(buffer, "mmu\t\t: sv48\n") == 0);
+ } else if (strstr(buffer, "uarch") != NULL) {
+assert(strcmp(buffer, "uarch\t\t: qemu\n") == 0);
+}
+}
+
+fclose(fp);
+retu
On Mon, 06 Mar 2023 00:33:20 PST (-0800), alexgh...@rivosinc.com wrote:
Hi Palmer,
On Mon, Mar 6, 2023 at 12:34 AM Palmer Dabbelt wrote:
On Fri, 03 Mar 2023 05:12:47 PST (-0800), alexgh...@rivosinc.com wrote:
> This introduces new properties to allow the user to set the satp mode,
&g
On Thu, 02 Mar 2023 01:12:04 PST (-0800), suni...@ventanamicro.com wrote:
This series adds the basic ACPI support for the RISC-V virt machine.
Currently only RINTC interrupt controller specification is approved by the
UEFI forum. External interrupt controller support in ACPI is in progress.
On Fri, 03 Mar 2023 15:28:14 PST (-0800), Bin Meng wrote:
On Sat, Mar 4, 2023 at 4:25 AM Palmer Dabbelt wrote:
The OpenSBI build has been using docker:19.03.1, which appears to be old
enough that v2 of the manifest is no longer supported. Something has
started serving us those manifests
On Thu, 02 Mar 2023 22:50:53 PST (-0800), mchit...@ventanamicro.com wrote:
Currently a Risc-V platform cannot realizes multiple CPUs with non contiguous
hart IDs because the APLIC, IMSIC and ACLINT emulation code uses the
contiguous logical CPU ID to fetch per CPU state.
This patchset
("Merge tag 'for-upstream' of
https://gitlab.com/bonzini/qemu into staging")
I have that, but I still got some merge conflicts. I've put that here
<https://github.com/palmer-dabbelt/qemu/tree/set-satp> for now, pending
Daniel's response below.
v11:
- rebase on top of master
-
4df1f9f4e704ce8325f958858c5cbff7
gpg: Signature made Sun 05 Mar 2023 12:43:52 PM PST
gpg:using RSA key 2B3C3747446843B24A943A7A2E1319F35FBB1889
gpg:issuer "pal...@dabbelt.com"
gpg: Good signature from "Palmer Dabbelt " [ultimate]
gpg:
On Fri, 24 Feb 2023 05:25:32 PST (-0800), dbarb...@ventanamicro.com wrote:
Hi,
This version has a change in patch 2, proposed by Weiwei Li, where we're
now triggering virt_instruction_fault before triggering illegal_insn
fault from S mode.
Richard already queued patch 1 is queued in tcg-next
On Thu, 02 Mar 2023 00:37:10 PST (-0800), ben.do...@codethink.co.uk wrote:
On 01/03/2023 21:59, Daniel Henrique Barboza wrote:
From: Anup Patel
The cbom-block-size fdt property property is used to inform the OS about
the blocksize in bytes for the Zicbom cache operations.
Linux documents it
On Thu, 02 Mar 2023 01:14:05 PST (-0800), dbarb...@ventanamicro.com wrote:
Based-on: 20230224132536.552293-1-dbarb...@ventanamicro.com
("[PATCH v8 0/4] riscv: Add support for Zicbo[m,z,p] instructions")
Hi,
This second version, which is still dependent on:
[PATCH v8 0/4] riscv: Add support
, as was suggested by the template. It also
adds the python3 package via apt, as OpenSBI requires that to build.
Signed-off-by: Palmer Dabbelt
---
.gitlab-ci.d/opensbi.yml| 4 ++--
.gitlab-ci.d/opensbi/Dockerfile | 1 +
2 files changed, 3 insertions(+), 2 deletions(-)
diff --git a/.gitlab-ci.d
and
poke around a bit but figured I'd send it out in case someone else has seen
something similar.
Changes since v1 <20230224212543.20462-1-pal...@rivosinc.com>:
* Installs python3, which OpenSBI depends on (via kconfiglib).
Link: https://gitlab.com/palmer-dabbelt/qemu/-/pipelines/79569609
-ID: <20230224174520.92490-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 32 +---
1 file changed, 9 insertions(+), 23 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 86e183feb3..78c3b6d5f6 100644
--- a/target/riscv/cs
From: Weiwei Li
Fix indent problems in vector related check.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-8-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.
: <20230228104035.1879882-18-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 020c3f524f..785f6f4d45 100644
--- a/target/riscv/csr.c
+++ b/target/riscv
-by: LIU Zhiwei
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230222185205.355361-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 5 +
1 file changed, 5 insertions(+)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
05.355361-10-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 7 ---
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 4 ++--
target/riscv/monitor.c| 2 +-
target/riscv/pmp.c| 2 +-
6 f
From: Weiwei Li
menvcfg.PBMTE/STCE are read-only zero if Svpbmt/Sstc are not implemented.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-2-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target
since
'features' is no longer being migrated.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-11-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target
-by: Weiwei Li
Message-ID: <20230228104035.1879882-16-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 22 --
1 file changed, 20 insertions(+), 2 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 15b23b9b5a..a0e70f5ba0
From: Bin Meng
There is no need to generate the CSR XML if the Zicsr extension
is not enabled.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-6-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub
default true for backward compatibility.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-6-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 6 --
target/riscv/cpu_helper
From: Bin Meng
Use the register index that has already been calculated in the
pmpcfg_csr_{read,write} call.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-9-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv
-off-by: Shaobo Song
Reviewed-by: Richard Henderson
Message-ID: <20230220072732.568-1-songsha...@eswincomputing.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/translate.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/translate.c b/target/riscv/trans
riscv: write bootargs 'chosen' FDT after
riscv_load_kernel()")
Signed-off-by: Bin Meng
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230228074522.1845007-1-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 1 +
hw/riscv/virt.c | 1 +
2 files chang
these
2 pointers.
Suggested-by: LIU Zhiwei
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.
: <20230224040852.37109-4-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 1 +
target/riscv/cpu_bits.h | 4
target/riscv/csr.c | 17 +++--
3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/target/riscv/cpu.h b/target/riscv
From: Daniel Henrique Barboza
Use riscv_cpu_cfg() to retrieve pmu_num.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr
Barboza
Message-ID: <20230215020539.4788-12-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv.c.inc | 31 +++--
1 file changed, 29 insertions(+), 2 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target
From: Weiwei Li
Check for Zve32f/Zve64d can overlap check for F/D.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-10-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv
-ID: <20230226170514.588071-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 20 ++--
1 file changed, 10 insertions(+), 10 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 7e476ea8c3..2
://gitlab.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230303
for you to fetch changes up to 37151032989ecf6e7ce8b65bc7bcb400d0318b2c:
Merge patch series "target/riscv: some vector_helper.c cleanups" (2023-03-01
18:0
From: Bin Meng
Fix various places that violate QEMU coding style:
- correct multi-line comment format
- indent to opening parenthesis
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-7-bm...@tinylab.org>
Signed-off-by: Palmer D
From: Weiwei Li
Add dependence chain:
* V => Zve64d => Zve64f => Zve32f => F
* V => Zve64d => D
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-6-liwei...@iscas.ac.cn>
Signed-off-by: Pal
-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-17-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 19 ++-
1 file changed, 14 insertions(+), 5 deletions(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a0e7
From: Bin Meng
The read_only variable is currently declared as an 'int', but it
should really be a 'bool'.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-8-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv
-ID: <20230222185205.355361-7-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 10 +++---
target/riscv/cpu.h | 1 -
target/riscv/csr.c | 2 +-
target/riscv/pmp.c | 4 ++--
4 files changed, 6 insertions(+), 11 deletions(-)
diff --git a/target/riscv/cpu.c b/target/ri
From: Bin Meng
Use env_archcpu() to get RISCVCPU pointer from env directly.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-10-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.
From: Weiwei Li
Zfhmin is part of Zfh, so Zfhmin will be enabled when Zfh is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-2-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu
From: Weiwei Li
We needn't check Zfh and Zhinx in these instructions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-4-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn
Message-ID: <20230228104035.1879882-3-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 11 ++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 75a540bfcb..4cc2c6370f 100644
--- a/target/riscv/csr.c
+++ b/ta
2-5-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index e57372db38..704f3d6922 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
From: Weiwei Li
Add check for Zvfh and Zvfhmin.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-7-liwei...@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.
by: Weiwei Li
Reviewed-by: Frank Chang
Signed-off-by: Daniel Henrique Barboza
Message-ID: <20230226170514.588071-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 86 +---
1 file changed, 30 insertions(+), 56 delet
mp;
rv32")
inserted these vector CSRs in an ad-hoc, non-standard way in the
riscv-vector.xml. Now we can treat these CSRs no different from
other CSRs.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-13-bm...@tinylab.org>
S
e of being
accessed by a debugger. All we need to do is to turn on debugger
mode before calling predicate().
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-12-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/gdbstub.c
From: Weiwei Li
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-3-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv
From: Weiwei Li
Add properties for Zve64d,Zvfh,Zvfhmin extensions.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-5-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.h | 3 +++
This will force users to pick saner options in the QEMU command line.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-6-dbarb...@ventanamicro.com>
Signed-off-by:
Reviewed-by: LIU Zhiwei
Message-ID: <20230220095612.1529031-1-christoph.muell...@vrull.eu>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_xthead.c.inc | 4
1 file changed, 4 deletions(-)
diff --git a/target/riscv/insn_trans/trans_xthead.c.inc
b/target/riscv/insn
From: Daniel Henrique Barboza
We don't need to use env_cpu() and CPUState().
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Richard Henderson
Message-ID: <20230224174520.92490-2-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3 +--
1 file chan
From: Bin Meng
Move sstc()/sstc32() to where all predicate() routines live, and
smstateen_acc_ok() to near {read,write}_xenvcfg().
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-19-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv
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