to
the PMP CSR predicate() routine, so that non-existent pmpcfgX won't
be reported in the CSR XML for RV64.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-11-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.
compatibility.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-5-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 3 +++
target/riscv/cpu_helper.c | 10 --
2 files chang
-by: Daniel Henrique Barboza
Message-ID: <20230228074522.1845007-2-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/sifive_u.c | 31 +++
hw/riscv/virt.c | 29 ++---
include/hw/riscv/sifive_u.h | 1 +
3 files chang
From: Weiwei Li
Require_zve32/64f have been overlapped by require_rvf/require_scale_rvf.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-11-liwei...@iscas.ac.cn>
[Palmer: commit text]
Signed-off-by: Palmer D
exception when software forgets to install the hook.
Change to use g_assert() instead.
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Message-ID: <20230228104035.1879882-4-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 6 +-
1 file changed, 1 insertion
-ID: <20230222185205.355361-5-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 6 +-
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/machine.c| 3 +--
5 files changed, 4 insertions(+), 10
wei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv.c.inc | 12
1 file changed, 4 insertions(+), 8 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 5dbdce073b..fc0d0d60e8 100644
--- a/
n the CSR XML generation logic to
fix this issue.
Fixes: 7100fe6c2441 ("target/riscv: Enable privileged spec version 1.12")
Signed-off-by: Bin Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230228104035.1879882-2-bm...@tinylab.org>
Signed-off-by: Palmer Dabbel
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 10ae5df5e6..15b23b9b5a 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -459,6 +459,10 @@ static RISCVException seed(CPURISCVStat
-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
hw/riscv/virt.c | 7 ---
1 file changed, 4 insertions(+), 3 deletions(-)
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index 86c4adc0c9..49f2c157f7 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -232,20 +232,21 @@ st
From: Weiwei Li
Set it default true for backward compatibility
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230224040852.37109-7-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 3 +++
1 file c
From: Weiwei Li
Expose Zve64d,Zvfh,Zvfhmin properties.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-15-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 7 +++
1 file chan
-14-bm...@tinylab.org>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 4
1 file changed, 4 insertions(+)
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index 7284fd8a0d..10ae5df5e6 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -131,6 +131,10 @@ static RISCVExc
is
nonzero, otherwise moves rs1 to rd.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Frank Chang
Message-ID: <20230221091009.36545-1-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +
target/riscv
-ID: <20230222185205.355361-8-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c| 4
target/riscv/cpu.h| 1 -
target/riscv/cpu_helper.c | 2 +-
target/riscv/csr.c| 2 +-
target/riscv/machine.c| 3 +--
target/riscv/op_helper.c | 2 +
: <20230215020539.4788-13-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target/riscv/insn_trans/trans_rvv.c.inc | 9 -
1 file changed, 4 insertions(+), 5 deletions(-)
diff --git a/target/riscv/insn_trans/trans_rvv.c.inc
b/target/riscv/insn_trans/trans_rvv.c.inc
index 9b2c5c9ac0..5dbd
From: Weiwei Li
V/Zve64f depend on Zve32f, so we can only check Zve32f in these cases.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-9-liwei...@iscas.ac.cn>
Signed-off-by: Palmer Dabbelt
---
target
Meng
Reviewed-by: Weiwei Li
Reviewed-by: LIU Zhiwei
Message-ID: <20230222185205.355361-4-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 6 ++
target/riscv/cpu.h | 2 +-
target/riscv/csr.c | 2 +-
3 files changed, 8 insertions(+), 2 deletions(-)
diff
From: Weiwei Li
Just like zfh and zfhmin, Zhinxmin is part of Zhinx so Zhinxmin
will be enabled when Zhinx is enabled.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang Wang
Reviewed-by: Daniel Henrique Barboza
Message-ID: <20230215020539.4788-3-liwei...@iscas.ac.cn>
Signed-off-by:
s pass by, misa_ext_mask itself needs to be fixed instead.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Weiwei Li
Reviewed-by: Bin Meng
Reviewed-by: Andrew Jones
Message-ID: <20230222185205.355361-3-dbarb...@ventanamicro.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/csr.c | 3
On Sun, 26 Feb 2023 09:05:12 PST (-0800), dbarb...@ventanamicro.com wrote:
Based-on: 20230222185205.355361-2-dbarb...@ventanamicro.com
("[PATCH v7 01/10] target/riscv: introduce riscv_cpu_cfg()")
Hi,
This is a re-send of patch 1, which is already reviewed, with a
follow-up that uses
On Fri, 24 Feb 2023 13:25:41 PST (-0800), Palmer Dabbelt wrote:
The OpenSBI version bump found a CI failure, which appears to actually
have been related to the Docker version as opposed to the Ubuntu
version -- at least assuming my local CI run
<https://gitlab.com/palmer-dabbelt/qemu/-/j
On Sun, 26 Feb 2023 10:23:01 PST (-0800), phi...@linaro.org wrote:
On 26/2/23 18:05, Daniel Henrique Barboza wrote:
Commit 752614cab8e6 ("target/riscv: rvv: Add tail agnostic for vector
load / store instructions") added code to set the tail elements to 1 in
the end of vext_ldst_stride(),
On Fri, 24 Feb 2023 09:45:16 PST (-0800), dbarb...@ventanamicro.com wrote:
Hi,
These cleanups were suggested by LIU Zhiwei during the review of the
RISCV_FEATURE_* cleanups, currently on version 7 [1].
These are dependent on the patch "[PATCH v7 01/10] target/riscv: introduce
riscv_cpu_cfg()"
On Fri, 24 Feb 2023 04:36:43 PST (-0800), liwei...@iscas.ac.cn wrote:
On 2023/2/24 20:19, Andrew Jones wrote:
On Fri, Feb 24, 2023 at 12:08:48PM +0800, Weiwei Li wrote:
henvcfg.PBMTE/STCE are read-only zero if menvcfg.PBMTE/STCE are zero.
Signed-off-by: Weiwei Li
Signed-off-by: Junqiang
On Thu, 23 Feb 2023 20:08:46 PST (-0800), liwei...@iscas.ac.cn wrote:
This patchset adds support svadu extension. It also fixes some relationship
between *envcfg fields and Svpbmt/Sstc extensions.
Specification for Svadu extension can be found in:
https://github.com/riscv/riscv-svadu
The
On Mon, 27 Feb 2023 23:45:21 PST (-0800), bm...@tinylab.org wrote:
Launch qemu-system-riscv64 with a given dtb for 'sifive_u' and 'virt'
machines, QEMU complains:
qemu_fdt_add_subnode: Failed to create subnode /soc: FDT_ERR_EXISTS
The whole DT generation logic should be skipped when a given
On Tue, 21 Feb 2023 01:10:09 PST (-0800), liwei...@iscas.ac.cn wrote:
The spec can be found in https://github.com/riscv/riscv-zicond.
Two instructions are added:
- czero.eqz: Moves zero to a register rd, if the condition rs2 is
equal to zero, otherwise moves rs1 to rd.
- czero.nez: Moves
On Sun, 19 Feb 2023 23:27:32 PST (-0800), songsha...@eswincomputing.com wrote:
This bug has a noticeable behavior of falling back to the main loop and
respawning a redundant translation block including a single instruction
when the end address of the compressive instruction is exactly on a page
On Mon, 20 Feb 2023 01:56:12 PST (-0800), christoph.muell...@vrull.eu wrote:
From: Christoph Müllner
The XTheadMemPair does not define any restrictions for store-pair
instructions (th.sdd or th.swd). However, the current code enforces
the restrictions that are required for load-pair
On Wed, 01 Mar 2023 16:30:52 PST (-0800), Bin Meng wrote:
On Thu, Mar 2, 2023 at 7:43 AM Palmer Dabbelt wrote:
On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
> On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei
wrote:
>>
>>
>> On 2023/2/28 18:40, Bin Meng wrote:
On Fri, 17 Feb 2023 07:45:14 PST (-0800), dbarb...@ventanamicro.com wrote:
On 2/17/23 12:14, Ivan Klokov wrote:
Due to typo in opcode list, ctzw is disassembled as clzw instruction.
The code was added by 02c1b569a15b4b06a so I believe a "Fixes:" tag is in
order:
Fixes: 02c1b569a15b
Wang, Zhenyu Z ; Mi,
> Dapeng1 ; Ding, Zhuocheng
> ; Robert Hoo ;
> Christopherson,, Sean ; Like Xu
> ; Liu, Zhao1 ; Meng, Bin
> ; Palmer Dabbelt ; Alistair
> Francis ; Vijai Kumar K
> Subject: [RFC 22/52] riscv: Replace MachineState.smp access with topology
> helpers
On Wed, 22 Feb 2023 10:51:55 PST (-0800), dbarb...@ventanamicro.com wrote:
Hi,
In this version we gave up removing all the write_misa() body and,
instead, we went back to something closer to what we were doing in v2.
write_misa() is now gated behind an experimental x-misa-w cfg option,
On Tue, 14 Feb 2023 18:05:25 PST (-0800), liwei...@iscas.ac.cn wrote:
Specification for Zv* extensions can be found in:
https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc
The port is available here:
https://github.com/plctlab/plct-qemu/tree/plct-zvfh-upstream-v2
v2:
* improve the
On Wed, 01 Mar 2023 01:55:34 PST (-0800), Bin Meng wrote:
On Wed, Mar 1, 2023 at 5:52 PM LIU Zhiwei wrote:
On 2023/2/28 18:40, Bin Meng wrote:
> There is no need to generate the CSR XML if the Zicsr extension
> is not enabled.
Should we generate the FPU XML or Vector XML when Zicsr is not
(-)
create mode 100644 target/riscv/insn_trans/trans_rvzicbo.c.inc
Acked-by: Palmer Dabbelt
in case Richard wants to take these along with the TCG patch, otherwise
I'm happy to take these through the RISC-V tree when that lands (or do
some sort of shared tag, as we're getting kind of close).
On Thu, 23 Feb 2023 16:10:59 PST (-0800), Richard Henderson wrote:
On 2/23/23 13:44, Daniel Henrique Barboza wrote:
probe_access_flags() as it is today uses probe_access_full(), which in
turn uses probe_access_internal() with size = 0. probe_access_internal()
then uses the size to call the
t;pc;
} else {
-env->pc = tb_pc(tb);
+env->pc = tb->pc;
}
}
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Thanks! I'm going to assume you want these to stay together, but LMK if
you were looking to aim this at the RISC-V tree.
, as was suggested by the template.
Signed-off-by: Palmer Dabbelt
---
.gitlab-ci.d/opensbi.yml | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/.gitlab-ci.d/opensbi.yml b/.gitlab-ci.d/opensbi.yml
index 04ed5a3ea1..9a651465d8 100644
--- a/.gitlab-ci.d/opensbi.yml
+++ b/.gitlab-ci.d
The OpenSBI version bump found a CI failure, which appears to actually
have been related to the Docker version as opposed to the Ubuntu
version -- at least assuming my local CI run
<https://gitlab.com/palmer-dabbelt/qemu/-/jobs/3832389705> is accurate
(thanks to Thomas for pointing out how
Reviewed-by: Alistair Francis
Message-Id: <20230206140022.2748401-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c| 20 +---
hw/riscv/microchip_pfsoc.c | 3 ++-
hw/riscv/opentitan.c | 3 ++-
hw
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:
tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09
11:23:53 +)
are available in the Git repository at:
g...@github.com:palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230224
for
From: Daniel Henrique Barboza
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Weiwei Li
Message-ID: <20230210123836.506286-1-dbarb...@ventanamicro.com>
Signed-off-by:
1-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 80 -
include/hw/riscv/boot.h | 1 -
2 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
Reviewed-by: Weiwei Li
Reviewed-by: Frank Chang
Message-ID: <20230213094550.29621-1-zhiwei_...@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target
the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.
Cc: Palmer Dabbelt
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
Reviewed
hau...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d1126a6066..4bc4113531 100644
--- a/target/riscv/pmp.c
+++ b/target
Chang
Reviewed-by: Bin Meng
Reviewed-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-Id: <20230208063209.27279-1-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 21 +++--
2 files c
-by: Frank Chang
Message-Id: <20230209003308.738237-1-alistair.fran...@opensource.wdc.com>
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,6
On Fri, 24 Feb 2023 10:52:34 PST (-0800), Peter Maydell wrote:
On Fri, 24 Feb 2023 at 06:56, Thomas Huth wrote:
Hi!
On 23/02/2023 23.49, Palmer Dabbelt wrote:
> Nobody's replied, so I'm inclined to just drop the OpenSBI bump and re-send
> the PR. At least that way we can avoid g
On Wed, 22 Feb 2023 07:56:10 PST (-0800), Palmer Dabbelt wrote:
On Tue, 21 Feb 2023 08:43:47 PST (-0800), Peter Maydell wrote:
On Fri, 17 Feb 2023 at 17:53, Palmer Dabbelt wrote:
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:
tests/qtest/netdev-socket: Raise
The OpenSBI docker images have started tripping up on Ubuntu 18.04,
which is about to hit EOL. So let's just move to 22.04 for EDK2 as
well.
Signed-off-by: Palmer Dabbelt
---
Just like the other one I don't know how to test this and I'm not at all
familiar with the CI so it might just be broken
On Tue, 21 Feb 2023 08:43:47 PST (-0800), Peter Maydell wrote:
On Fri, 17 Feb 2023 at 17:53, Palmer Dabbelt wrote:
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:
tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09
11:23:53 +
should be
'application/vnd.docker.distribution.manifest.v2+json' not
'application/vnd.oci.image.manifest.v1+json'
Since 18.04 hits EOL at the end of April (a few months), let's just move
to 22.04 now.
Signed-off-by: Palmer Dabbelt
---
I don't even know how to test this, as I've not touched the CI
Reviewed-by: Alistair Francis
Message-Id: <20230206140022.2748401-2-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c| 20 +---
hw/riscv/microchip_pfsoc.c | 3 ++-
hw/riscv/opentitan.c | 3 ++-
hw
Reviewed-by: Weiwei Li
Reviewed-by: Frank Chang
Message-ID: <20230213094550.29621-1-zhiwei_...@linux.alibaba.com>
Signed-off-by: Palmer Dabbelt
---
target/riscv/vector_helper.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/riscv/vector_helper.c b/target
The following changes since commit 417296c8d8588f782018d01a317f88957e9786d6:
tests/qtest/netdev-socket: Raise connection timeout to 60 seconds (2023-02-09
11:23:53 +)
are available in the Git repository at:
https://github.com/palmer-dabbelt/qemu.git tags/pull-riscv-to-apply-20230217
Chang
Reviewed-by: Bin Meng
Reviewed-by: LIU Zhiwei
Acked-by: Alistair Francis
Message-Id: <20230208063209.27279-1-frank.ch...@sifive.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 2 +-
target/riscv/csr.c | 21 +++--
2 files c
From: Daniel Henrique Barboza
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza
Reviewed-by: Philippe Mathieu-Daudé
Reviewed-by: Weiwei Li
Message-ID: <20230210123836.506286-1-dbarb...@ventanamicro.com>
Signed-off-by:
the behavior of boards that aren't calling
riscv_load_init(), add an 'load_initrd' flag to riscv_load_kernel() and
allow these boards to opt out from initrd loading.
Cc: Palmer Dabbelt
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
Signed-off-by: Daniel Henrique Barboza
Reviewed
-by: Frank Chang
Message-Id: <20230209003308.738237-1-alistair.fran...@opensource.wdc.com>
Signed-off-by: Palmer Dabbelt
---
MAINTAINERS | 3 +++
1 file changed, 3 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 96e25f62ac..847bc7f131 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -287,6
1-4-dbarb...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
hw/riscv/boot.c | 80 -
include/hw/riscv/boot.h | 1 -
2 files changed, 40 insertions(+), 41 deletions(-)
diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
hau...@ventanamicro.com>
Signed-off-by: Alistair Francis
Signed-off-by: Palmer Dabbelt
---
target/riscv/pmp.c | 9 ++---
1 file changed, 6 insertions(+), 3 deletions(-)
diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c
index d1126a6066..4bc4113531 100644
--- a/target/riscv/pmp.c
+++ b/target
On Thu, 16 Feb 2023 17:59:42 PST (-0800), Bin Meng wrote:
Hi Palmer,
On Fri, Feb 17, 2023 at 12:40 AM Palmer Dabbelt wrote:
On Tue, 14 Feb 2023 18:22:21 PST (-0800), Bin Meng wrote:
> On Tue, Feb 14, 2023 at 10:59 PM weiwei wrote:
>>
>>
>> On 2023/2/14 22:27, Bin Meng w
On Tue, 14 Feb 2023 18:22:21 PST (-0800), Bin Meng wrote:
On Tue, Feb 14, 2023 at 10:59 PM weiwei wrote:
On 2023/2/14 22:27, Bin Meng wrote:
> At present the envcfg CSRs predicate() routines are generic one like
> smode(), hmode. The configuration check is done in the read / write
> routine.
On Wed, 15 Feb 2023 06:08:10 PST (-0800), suni...@ventanamicro.com wrote:
On Tue, Feb 14, 2023 at 05:44:44AM -0300, Daniel Henrique Barboza wrote:
On 2/14/23 00:43, Sunil V L wrote:
> On Mon, Feb 13, 2023 at 03:48:04PM -0300, Daniel Henrique Barboza wrote:
Nah. Doing that now will make this
On Mon, 13 Feb 2023 01:45:50 PST (-0800), zhiwei_...@linux.alibaba.com wrote:
vslide1up_##BITWIDTH is used by the vslide1up.vx and vslide1up.vf. So its
scalar input should be uint64_t to hold the 64 bits float register.And the
same for vslide1down_##BITWIDTH.
This bug is caught when run these
On Fri, 10 Feb 2023 04:38:36 PST (-0800), dbarb...@ventanamicro.com wrote:
We have a RISCVCPU *cpu pointer available at the start of the function.
Signed-off-by: Daniel Henrique Barboza
---
target/riscv/cpu_helper.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git
't failing, though. Either way
Reviewed-by: Palmer Dabbelt
Acked-by: Palmer Dabbelt
Thanks!
Signed-off-by: Michael Tokarev
---
hw/ssi/sifive_spi.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c
index 03540cf5ca..1b4a401ca1 100644
--
On Thu, 29 Sep 2022 12:16:48 PDT (-0700), dgilb...@redhat.com wrote:
* Palmer Dabbelt (pal...@rivosinc.com) wrote:
Ztso, the RISC-V extension that provides the TSO memory model, was
recently frozen. This provides support for Ztso on targets that are
themselves TSO.
Signed-off-by: Palmer
On Thu, 22 Sep 2022 21:35:26 PDT (-0700), alistai...@gmail.com wrote:
On Sat, Sep 17, 2022 at 6:12 PM Palmer Dabbelt wrote:
The Ztso extension was recently frozen, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker
On Sat, 17 Sep 2022 01:02:46 PDT (-0700), Richard Henderson wrote:
On 9/16/22 14:52, Palmer Dabbelt wrote:
Though, honestly, I've had patches to add the required barriers sitting around
for the
last few releases, to better support things like x86 on aarch64. I should just
finish
that up.
I
The Ztso extension was recently frozen, this adds it as a CPU property
and adds various fences throughout the port in order to allow TSO
targets to function on weaker hosts. We need no fences for AMOs as
they're already SC, the placess we need barriers are described.
Signed-off-by: Palmer
On Sat, 03 Sep 2022 17:47:54 PDT (-0700), richard.hender...@linaro.org wrote:
On 9/2/22 04:44, Palmer Dabbelt wrote:
-#define TCG_GUEST_DEFAULT_MO 0
+/*
+ * RISC-V has two memory models: TSO is a bit weaker than Intel (MMIO and
+ * fetch), and WMO is approximately equivilant to Arm MCA. Rather
--- a/gdb-xml/riscv-64bit-fpu.xml
+++ b/gdb-xml/riscv-64bit-fpu.xml
@@ -5,10 +5,6 @@
are permitted in any medium without royalty provided the copyright
notice and this notice are preserved. -->
-
-
@@ -17,7 +13,7 @@
-
+
Reviewed-by: Palmer Dabbelt
Thanks.
Ztso, the RISC-V extension that provides the TSO memory model, was
recently frozen. This provides support for Ztso on targets that are
themselves TSO.
Signed-off-by: Palmer Dabbelt
---
My first thought was to just add the TCG barries to load/store and AMOs
that as defined by Ztso, but after
>cfg.ebreakvu;
> +} else {
> +return cpu->cfg.ebreaku;
> +}
> +}
> +
> +return false;
> +}
> #endif /* !CONFIG_USER_ONLY */
>
> /*
> @@ -1342,7 +1366,7 @@ void riscv_cpu_do_interrupt(CPUState *cs)
> target_ulong mtval2 = 0;
>
>
is disabled at runtime via misa.
This just stops overriding M from Zmmul, with that the other checks for
the multiplication instructions work as per the ISA.
Signed-off-by: Palmer Dabbelt
---
target/riscv/cpu.c | 5 -
1 file changed, 5 deletions(-)
diff --git a/target/riscv/cpu.c b/target
On Wed, 04 May 2022 08:10:03 PDT (-0700), alistai...@gmail.com wrote:
On Wed, May 4, 2022 at 2:32 PM nihui wrote:
This patch brings the optional risc-v vector and hypervisor bits
in hwcap so that application could detect these isa support from
/proc/self/auxv correctly in qemu userspace mode.
On Wed, 30 Mar 2022 22:13:39 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 31, 2022 at 2:36 PM Palmer Dabbelt wrote:
On Wed, 30 Mar 2022 20:23:21 PDT (-0700), alistai...@gmail.com wrote:
> On Thu, Mar 31, 2022 at 3:11 AM Idan Horowitz wrote:
>>
>> On Wed, 30 Mar 2022 a
On Wed, 30 Mar 2022 20:23:21 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 31, 2022 at 3:11 AM Idan Horowitz wrote:
On Wed, 30 Mar 2022 at 19:11, Palmer Dabbelt wrote:
>
>
> Presumably you mean "revert" here? That might be the right way to go,
> just to avoi
: 1e0d985fa9 ("target/riscv: Only flush TLB if SATP.ASID changes")
Signed-off-by: Palmer Dabbelt
---
Another way to fix this would be to utilize a MMU index that cooresponds
to no ASID to hold these direct mappings, but given that we're not
currently taking advantage of ASIDs for translation p
On Wed, 30 Mar 2022 09:11:18 PDT (-0700), Palmer Dabbelt wrote:
[re-ordering the top post]
+linux-riscv, as this may very well be a kernel bug
On Wed, 30 Mar 2022 05:38:30 PDT (-0700), phan...@zju.edu.cn wrote:
-Original Messages-
From: "Idan Horowitz"
Sent Time: 2022-03-3
[re-ordering the top post]
+linux-riscv, as this may very well be a kernel bug
On Wed, 30 Mar 2022 05:38:30 PDT (-0700), phan...@zju.edu.cn wrote:
-Original Messages-
From: "Idan Horowitz"
Sent Time: 2022-03-30 15:35:19 (Wednesday)
To: "Atish Patra"
Cc: phan...@zju.edu.cn, "open
On Sun, 20 Mar 2022 22:43:07 PDT (-0700), alistai...@gmail.com wrote:
On Thu, Mar 17, 2022 at 7:46 PM Peter Maydell wrote:
On Wed, 16 Mar 2022 at 22:23, Alistair Francis wrote:
> Hmm... This seems like a bug. We shouldn't allow the user to specify a
> `-bios` option if using KVM. Would you
On Tue, 08 Feb 2022 05:07:23 PST (-0800), liyu.yukit...@bytedance.com wrote:
Since the hypervisor extension been non experimental and enabled for
default CPU, the previous command is no longer available and the
option `x-h=true` or `h=true` is also no longer required.
Signed-off-by: Yu Li
---
On Fri, 04 Jun 2021 08:30:30 PDT (-0700), richard.hender...@linaro.org wrote:
On 6/3/21 11:33 PM, Kito Cheng wrote:
RISC-V define the hwcap as same as content of misa, but it only take lower
26-bits.
As far as I can see linux only passes IMAFDC, not all 26 bits.
We decided to play it safe
On Tue, 25 May 2021 22:43:27 PDT (-0700), zhiwei_...@c-sky.com wrote:
On 5/24/21 9:00 AM, Palmer Dabbelt wrote:
On Mon, 15 Mar 2021 14:22:58 PDT (-0700), alistai...@gmail.com wrote:
On Fri, Feb 12, 2021 at 10:14 AM LIU Zhiwei
wrote:
Signed-off-by: LIU Zhiwei
Acked-by: Alistair Francis
On Tue, 25 May 2021 22:30:14 PDT (-0700), Palmer Dabbelt wrote:
On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_...@c-sky.com wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 6
target/riscv/insn32.decode | 6
target/riscv/insn_trans
On Fri, 12 Feb 2021 07:02:26 PST (-0800), zhiwei_...@c-sky.com wrote:
Signed-off-by: LIU Zhiwei
---
target/riscv/helper.h | 6
target/riscv/insn32.decode | 6
target/riscv/insn_trans/trans_rvp.c.inc | 7
target/riscv/packed_helper.c|
shift = sextract32((*(uint32_t *)vb), 0, 4);
+
+if (shift >= 0) {
+do_ksll8(env, vd, va, vb, i);
+} else {
+shift = -shift;
+shift = (shift == 8) ? 7 : shift;
+d[i] = vssra8(env, 0, a[i], shift);
+}
+}
+
+RVPR(kslra8_u, 1, 1);
Reviewed-by: Palmer Dabbelt
vb;
+d[i] = ssubu8(env, 0, a[i], b[i]);
+}
+
+RVPR(uksub8, 1, 1);
--
2.17.1
The naming on some of these helpers is a bit odd, but given that they're
a mix of the V and P extensions it's probably fine to just leave them
as-is.
Reviewed-by: Palmer Dabbelt
ec_illegal, rv_fmt_none, NULL, 0, 0, 0 },
{ "lui", rv_codec_u, rv_fmt_rd_imm, NULL, 0, 0, 0 },
{ "auipc", rv_codec_u, rv_fmt_rd_offset, NULL, 0, 0, 0 },
Reviewed-by: Palmer Dabbelt (RISC-V)
Thanks!
8b0bf966..c347d49bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+SiFive Machines
+M: Alistair Francis
+M: Bin Meng
+M: Palmer Dabbelt
+L: qemu-ri...@nongnu.org
SC-V machines:
diff --git a/MAINTAINERS b/MAINTAINERS
index 8d8b0bf966..c347d49bd2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1359,6 +1359,15 @@ F: include/hw/misc/mchp_pfsoc_dmc.h
F: include/hw/misc/mchp_pfsoc_ioscb.h
F: include/hw/misc/mchp_pfsoc_sysreg.h
+SiFive Machines
+M: Alistair Francis
+M:
list by running
``qemu-system-riscv64 --machine help``, or
``qemu-system-riscv32 --machine help``.
+..
+ This table of contents should be kept sorted alphabetically
+ by the title text of each file, which isn't the same ordering
+ as an alphabetical sort by filename.
+
+.. toctree::
+ :maxdepth:
*machine)
fdt_load_addr = riscv_load_fdt(memmap[VIRT_DRAM].base,
machine->ram_size, s->fdt);
/* load the reset vector */
-riscv_setup_rom_reset_vec(machine, s->soc[0], start_addr,
+riscv_setup_rom_reset_vec(machine, >soc[0], start
t/riscv/meson.build b/target/riscv/meson.build
index 14a5c62dac..88ab850682 100644
--- a/target/riscv/meson.build
+++ b/target/riscv/meson.build
@@ -26,6 +26,7 @@ riscv_ss.add(files(
riscv_softmmu_ss = ss.source_set()
riscv_softmmu_ss.add(files(
+ 'arch_dump.c',
'pmp.c',
'monitor.c',
'machine.c'
Reviewed-by: Palmer Dabbelt
Has anyone tested this with GDB?
Thanks!
On Thu, 14 Jan 2021 01:49:40 PST (-0800), bmeng...@gmail.com wrote:
On Thu, Jan 14, 2021 at 8:09 AM Alistair Francis wrote:
On Fri, Nov 6, 2020 at 2:36 AM Alex Bennée wrote:
>
>
> Palmer Dabbelt writes:
>
> > On Thu, 22 Oct 2020 17:56:38 PDT (-0700), alistai...@gmail.com
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