Re: [PATCH] target/i386: Fix exception classes for SSE/AVX instructions.

On Fri, Apr 14, 2023 at 8:19 AM Philippe Mathieu-Daudé wrote: > Having this patch split in 2 (documentation first, logical change then) > would ease code review. > > > There is one functional change: > > > > Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class > > 4 (only requi

[PATCH v2 3/3] target/i386: Fix exception classes for MOVNTPS/MOVNTPD.

Before this change, MOVNTPS and MOVNTPD were labeled as Exception Class 4 (only requiring alignment for legacy SSE instructions). This changes them to Exception Class 1 (always requiring memory alignment), as documented in the Intel manual. --- target/i386/tcg/decode-new.c.inc | 5 +++-- 1 file ch

[PATCH v2 1/3] target/i386: Fix and add some comments next to SSE/AVX instructions.

Adds some comments describing what instructions correspond to decoding table entries and fixes some existing comments which named the wrong instruction. --- target/i386/tcg/decode-new.c.inc | 24 1 file changed, 12 insertions(+), 12 deletions(-) diff --git a/target/i386/t

[PATCH v2 2/3] target/i386: Fix exception classes for SSE/AVX instructions.

Fix the exception classes for some SSE/AVX instructions to match what is documented in the Intel manual. These changes are expected to have no functional effect on the behavior that qemu implements (primarily >= 16-byte memory alignment checks). For instance, since qemu does not implement the AC f

Re: [PATCH] target/i386: Fix exception classes for SSE/AVX instructions.

Another ping for this patch: Patchew link: https://patchew.org/QEMU/20230212082812.55101-1-ri...@rzhou.org/ Thanks, Ricky On Mon, Mar 20, 2023 at 6:21 AM Ricky Zhou wrote: > > On Sun, Feb 12, 2023 at 12:28 AM Ricky Zhou wrote: > > Fix the exception classes for some SSE/AVX ins

Re: [PATCH] target/i386: Fix exception classes for SSE/AVX instructions.

On Sun, Feb 12, 2023 at 12:28 AM Ricky Zhou wrote: > Fix the exception classes for some SSE/AVX instructions to match what is > documented in the Intel manual. Friendly ping :-) Does this change seem reasonable to folks? Patchew link: https://patchew.org/QEMU/20230212082812.5510

[PATCH] target/i386: Fix exception classes for SSE/AVX instructions.

cy SSE instructions). This changes them to Exception Class 1 (always requiring memory alignment), as documented in the Intel manual. Signed-off-by: Ricky Zhou --- target/i386/tcg/decode-new.c.inc | 79 1 file changed, 40 insertions(+), 39 deletions(-) diff --git a/targe

Re: [PATCH v3 2/2] target/i386: Raise #GP on unaligned m128 accesses when required.

rt is from being merged, but do let me know if there's any preference re applying this change vs. waiting to rebase on top the AVX support changes, etc. Thanks! Ricky On Mon, Aug 29, 2022 at 8:48 PM Ricky Zhou wrote: > > Many instructions which load/store 128-bit values are supposed to

[PATCH v3 2/2] target/i386: Raise #GP on unaligned m128 accesses when required.

and qemu-system, respectively. Resolves: https://gitlab.com/qemu-project/qemu/-/issues/217 Reviewed-by: Richard Henderson Signed-off-by: Ricky Zhou --- target/i386/tcg/excp_helper.c| 13 target/i386/tcg/helper-tcg.h | 28 ++--- target/i386/tcg/sysemu/exc

[PATCH v3 1/2] target/i386: Read 8 bytes from cvttps2pi/cvtps2pi memory operands

written as xmm/m64. I double-checked on real hardware that both of these instructions only read 8 bytes. Reviewed-by: Richard Henderson Signed-off-by: Ricky Zhou --- target/i386/tcg/translate.c | 6 +- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/target/i386/tcg/translate.c b

[PATCH v2 0/1] target/i386: Raise #GP on unaligned m128 accesses when required.

these hooks for now rather than plumbing through an extra bit in MemOp. Let me know if that seems reasonable, thanks! Ricky Zhou (1): target/i386: Raise #GP on unaligned m128 accesses when required. target/i386/tcg/excp_helper.c| 13 target/i386/tcg/helper-tcg.h

[PATCH v2 1/1] target/i386: Raise #GP on unaligned m128 accesses when required.

do not have any address alignment requirements). Resolves: https://gitlab.com/qemu-project/qemu/-/issues/217 Signed-off-by: Ricky Zhou --- target/i386/tcg/excp_helper.c| 13 target/i386/tcg/helper-tcg.h | 28 +--- target/i386/tcg/sysemu/excp_helper.c | 8 +

Re: [PATCH 1/1] target/i386: Raise #GP on unaligned m128 accesses when required.

On Mon, Aug 29, 2022 at 9:45 AM Richard Henderson wrote: > > On 8/29/22 07:23, Ricky Zhou wrote: > This trap should be raised via the memory operation: > ... > Only the first of the two loads/stores must be aligned, as the other is known > to be +8. > You

[PATCH 1/1] target/i386: Raise #GP on unaligned m128 accesses when required.

gitlab.com/qemu-project/qemu/-/issues/217 Signed-off-by: Ricky Zhou --- target/i386/helper.h | 1 + target/i386/tcg/mem_helper.c | 8 target/i386/tcg/translate.c | 38 +--- 3 files changed, 44 insertions(+), 3 deletions(-) diff --git a/target/i386/he

[PATCH 0/1] target/i386: Raise #GP on unaligned m128 accesses when required.

VEX). Not sure this is very future-proof though - for example, it may need to be updated if support for EVEX prefixes is added. LMK if there's a nicer way to do this. 3. I tested this by running a Linux VM in qemu-system-x86_64 and verifying that movaps on an misaligned address trigg

[Qemu-devel] [PATCH] target-i386: Allow execute from user mode when SMEP is enabled.

Previously, execute would be disabled for all pages with SMEP enabled, regardless of what mode the access took place in. Signed-off-by: Ricky Zhou --- target-i386/helper.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/target-i386/helper.c b/target-i386/helper.c index