Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
approach to modify the ACPI pre-built binary
files required by the Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR table to support SPCR table
.
+0050: 00 00 00 00 02 00 58 00 2E 00 // ..X...
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
---
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
di
/931
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Reviewed-by: Michael S. Tsirkin
Acked-by: Alistair Francis
---
hw/acpi/aml-build.c | 20
hw/arm/virt-acpi-build.c| 8 ++--
hw/loongarch/acpi-build.c | 6 +-
hw/riscv/virt-acpi-build.c | 12
/931
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
---
hw/acpi/aml-build.c | 20
hw/arm/virt-acpi-build.c| 8 ++--
hw/riscv/virt-acpi-build.c | 12 +---
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml
.
+0050: 00 00 00 00 02 00 58 00 2E 00 // ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a/tests/data/acpi/r
Signed-off-by: Sia Jee Heng
Reviewed-by: Sunil V L
Acked-by: Alistair Francis
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b
ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR table to support SPCR table revision 4
format
tests/qtest/bios-tables-test: Update virt SPCR golden reference for
RISC-V
hw/acpi/aml-build.c
00 00 //
+0050: 00 00 00 00 02 00 58 00 2E 00 // ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a
v2:
- Utilizes a three-patch approach to modify the ACPI pre-built binary
files required by the Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR
/931
Signed-off-by: Sia Jee Heng
Acked-by: Alistair Francis
---
hw/acpi/aml-build.c | 20
hw/arm/virt-acpi-build.c| 10 +++---
hw/riscv/virt-acpi-build.c | 12 +---
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml-build.h | 2 +-
5 files
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test
v2:
- Utilizes a three-patch approach to modify the ACPI pre-built binary
files required by the Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..aae973048a 100644
--- a/tests/qtest/bios-tables-test
00 00 //
+0050: 00 00 00 00 02 00 58 00 2E 00 // ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-allowed-diff.h | 1 -
2 files changed, 1 deletion(-)
diff --git a
/931
Signed-off-by: Sia Jee Heng
Acked-by: Alistair Francis
---
hw/acpi/aml-build.c | 20
hw/arm/virt-acpi-build.c| 10 +++---
hw/riscv/virt-acpi-build.c | 12 +---
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml-build.h | 2 +-
5 files
Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
hw/acpi: Upgrade ACPI SPCR table to support SPCR table version 4
format
tests/qtest/bios-tables-test: Update virt SPCR
00 00 00 // ............
+ 0050: 00 00 00 00 02 00 58 00 2E 00// ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/aarch64/virt/SPCR | Bin 80 -> 90 bytes
tests/data/acpi/riscv64/virt/SPCR | Bin 80 -> 90 bytes
tests/qtest/bios-tables-test-a
Signed-off-by: Sia Jee Heng
Acked-by: Alistair Francis
---
hw/acpi/aml-build.c | 14 +++---
hw/arm/virt-acpi-build.c| 10 --
hw/riscv/virt-acpi-build.c | 12 +---
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml-build.h | 2 +-
5 files changed
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..b2dfcd60dd 100644
--- a/tests/qtest/bios-tables-test
-suni...@ventanamicro.com/
Changes in v2:
- Utilizes a three-patch approach to modify the ACPI pre-built binary
files required by the Bios-Table-Test.
- Rebases and incorporates changes to support both ARM and RISC-V ACPI
pre-built binary files.
Sia Jee Heng (3):
qtest: allow SPCR acpi table changes
1 00 00 03 //
0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 //
+ 0050: 00 00 00 00 02 00 58 00 2E 00// ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/virt/aarch64/SPCR | Bin 80 -> 90 bytes
tests/data/acpi/virt/r
Signed-off-by: Sia Jee Heng
---
tests/qtest/bios-tables-test-allowed-diff.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/tests/qtest/bios-tables-test-allowed-diff.h
b/tests/qtest/bios-tables-test-allowed-diff.h
index dfb8523c8b..3f12ca546b 100644
--- a/tests/qtest/bios-tables-test
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 14 +++---
hw/arm/virt-acpi-build.c| 10 --
hw/riscv/virt-acpi-build.c | 12 +---
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml-build.h | 2 +-
5 files changed, 34 insertions(+), 11
0: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ..!.
+0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 //
+0050: 00 00 00 00 02 00 58 00 2E 00 // ..X...
Signed-off-by: Sia Jee Heng
---
tests/data/acpi/virt/SPCR | Bin 80 -> 90 bytes
1 file changed
-hardware/drivers/serports/serial-port-console-redirection-table
[2]: https://github.com/acpica/acpica/pull/931
Sia Jee Heng (2):
tests/qtest/bios-tables-test: Update virt SPCR golden references
hw/acpi: Upgrade ACPI SPCR table to support SPCR table version 4
format
hw/acpi/aml-build.c
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 14 +++---
hw/arm/virt-acpi-build.c| 10 --
hw/riscv/virt-acpi-build.c | 10 --
include/hw/acpi/acpi-defs.h | 7 +--
include/hw/acpi/aml-build.h | 2 +-
5 files changed, 33 insertions(+), 10
Introduced a 3-layer cache for the ARM virtual machine.
Signed-off-by: Sia Jee Heng
---
hw/arm/virt-acpi-build.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 17aeec7a6f
,threads=1
2-layer: -smp 4,sockets=1,cores=2,threads=2
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 65 ++---
include/hw/acpi/aml-build.h | 26 ++-
2 files changed, 85 insertions(+), 6 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi
Generate the Processor Properties Topology Table (PPTT) with a
cache type 1 structure for RISC-V virtual machine. A 3-layer
cache topology is used.
Signed-off-by: Sia Jee Heng
---
hw/riscv/virt-acpi-build.c | 49 +-
hw/riscv/virt.c| 1 +
2 files
from the
architecture code.
Examples:
3-layer: -smp 4,sockets=1,clusters=2,cores=2,threads=1
2-layer: -smp 4,sockets=1,cores=2,threads=2
Sia Jee Heng (3):
hw/acpi/aml-build: Add cache structure table creation for PPTT table
hw/riscv/virt-acpi-build.c: Generate PPTT table
hw/arm/virt-acpi
Introduced a 3-layer cache for the ARM virtual machine.
Signed-off-by: Sia Jee Heng
---
hw/arm/virt-acpi-build.c | 44 +++-
1 file changed, 43 insertions(+), 1 deletion(-)
diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 17aeec7a6f
,threads=1
2-layer: -smp 4,sockets=1,cores=2,threads=2
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 65 ++---
include/hw/acpi/aml-build.h | 26 ++-
2 files changed, 85 insertions(+), 6 deletions(-)
diff --git a/hw/acpi/aml-build.c b/hw/acpi
Generate the Processor Properties Topology Table (PPTT) with a
cache type 1 structure for RISC-V virtual machine. A 3-layer
cache topology is used.
Signed-off-by: Sia Jee Heng
---
hw/riscv/virt-acpi-build.c | 49 +-
hw/riscv/virt.c| 1 +
2 files
from the
architecture code.
Examples:
3-layer: -smp 4,sockets=1,clusters=2,cores=2,threads=1
2-layer: -smp 4,sockets=1,cores=2,threads=2
Sia Jee Heng (3):
hw/acpi/aml-build: Add cache structure table creation for PPTT table
hw/riscv/virt-acpi-build.c: Generate PPTT table
hw/arm/virt-acpi
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/virt-acpi-build.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi
RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 51
hw/arm/virt-acpi-build.c| 68
.@ventanamicro.com/
[2]
https://lore.kernel.org/qemu-devel/20240105090608.5745-1-jeeheng....@starfivetech.com/
Sia Jee Heng (2):
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
hw/riscv/virt-acpi-build.c: Generate SPCR table
hw/acpi/aml-build.c | 51
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng
Reviewed-by: Daniel Henrique Barboza
---
hw/riscv/virt-acpi-build.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi
RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 51
hw/arm/virt-acpi-build.c| 68
.@ventanamicro.com/
[2]
https://lore.kernel.org/qemu-devel/20240105090608.5745-1-jeeheng....@starfivetech.com/
Sia Jee Heng (2):
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common location
hw/riscv/virt-acpi-build.c: Generate SPCR table
hw/acpi/aml-build.c | 51
RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 51
hw/arm/virt-acpi-build.c| 68
function.
The patch set is built upon Alistair's riscv-to-apply.next branch and
relies on Sunil's patches at [1].
[1]
https://lore.kernel.org/qemu-devel/20231218150247.466427-1-suni...@ventanamicro.com/
Sia Jee Heng (2):
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common loc
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng
---
hw/riscv/virt-acpi-build.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index
RISC-V should also generate the SPCR in a manner similar to ARM.
Therefore, instead of replicating the code, relocate this function
to the common AML build.
Signed-off-by: Sia Jee Heng
---
hw/acpi/aml-build.c | 51
hw/arm/virt-acpi-build.c| 68
Generate Serial Port Console Redirection Table (SPCR) for RISC-V
virtual machine.
Signed-off-by: Sia Jee Heng
---
hw/riscv/virt-acpi-build.c | 39 ++
1 file changed, 39 insertions(+)
diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c
index
function.
The patch set is built upon Alistair's riscv-to-apply.next branch and
relies on Sunil's patches at [1].
[1]
https://lore.kernel.org/qemu-devel/20231218150247.466427-1-suni...@ventanamicro.com/
Sia Jee Heng (2):
hw/arm/virt-acpi-build.c: Migrate SPCR creation to common loc
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