On Fri, Oct 4, 2024 at 6:00 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/4/24 5:33 AM, Andrew Jones wrote:
> > On Thu, Oct 03, 2024 at 11:36:00AM GMT, Tomasz Jeznach wrote:
> >> On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
> >> wrote:
> &
On Thu, Oct 3, 2024 at 6:06 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/3/24 6:26 AM, Andrew Jones wrote:
> > On Tue, Oct 01, 2024 at 10:02:58PM GMT, Daniel Henrique Barboza wrote:
> > ...
> >> +/*
> >> + * RISCV IOMMU Address Translation Lookup - Page Table Walk
> >> + *
> >> + * Note: Code i
On Tue, Sep 3, 2024 at 4:46 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/26/24 11:18 PM, Tomasz Jeznach wrote:
> > On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
> > wrote:
> >>
> >>
> >>
> >> On 8/20/24 12:16 PM, Jason Ch
On Tue, Oct 1, 2024 at 4:00 PM Daniel Henrique Barboza
wrote:
>
>
>
> On 10/1/24 7:14 PM, Tomasz Jeznach wrote:
> > On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell
> > wrote:
> >>
> >> On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
> >>
On Tue, Sep 24, 2024 at 3:18 PM Alistair Francis wrote:
> +
> +/* IOMMU index for transactions without process_id specified. */
> +#define RISCV_IOMMU_NOPROCID 0
> +
> +static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t
> vec_type)
> +{
> +switch (vec_type) {
> +case RI
On Sun, Sep 29, 2024 at 8:46 AM Peter Maydell wrote:
>
> On Sat, 28 Sept 2024 at 22:01, Daniel Henrique Barboza
> wrote:
> >
> >
> >
> > On 9/28/24 5:22 PM, Peter Maydell wrote:
> > > On Tue, 24 Sept 2024 at 23:19, Alistair Francis
> > > wrote:
>
> > >> +/* Register helper functions */
> > >> +
converted to atomic operations.
Signed-off-by: Tomasz Jeznach
---
hw/intc/riscv_imsic.c | 50 +++
1 file changed, 32 insertions(+), 18 deletions(-)
diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c
index b90f0d731d..9ef65d4012 100644
--- a/hw/intc
On Thu, Jul 4, 2024 at 7:20 AM Jason Chien wrote:
>
> Hi Danial,
>
> On 2024/6/25 上午 04:18, Daniel Henrique Barboza wrote:
> > From: Tomasz Jeznach
> >
> > The RISC-V IOMMU specification is now ratified as-per the RISC-V
> > international process. The latest
On Fri, Aug 23, 2024 at 10:18 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/20/24 12:27 PM, Jason Chien wrote:
> > Hi Daniel,
> >
> > On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
> >> From: Tomasz Jeznach
> >>
> >> The RISC-V IOMM
On Fri, Aug 23, 2024 at 5:42 AM Daniel Henrique Barboza
wrote:
>
>
>
> On 8/20/24 12:16 PM, Jason Chien wrote:
> > Hi Daniel,
> >
> > On 2024/8/1 下午 11:43, Daniel Henrique Barboza wrote:
> >> From: Tomasz Jeznach
> >>
> >> The RIS
github [1] branch
riscv_iommu_v4-rc1.
[1] link: https://github.com/tjeznach/qemu/tree/riscv_iommu_v4-rc1
Thanks!
- Tomasz Jeznach
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index a27f56419a..75c5d645fc 100644
--- a/hw/riscv/riscv-iommu.c
+++ b/hw/riscv/riscv-iommu.c
@@ -99
On Sun, Jul 23, 2023 at 7:35 PM Alistair Francis wrote:
>
> On Thu, Jul 20, 2023 at 12:35 PM Tomasz Jeznach wrote:
> >
> > Adding virt machine property 'iommu' to enable/disable IOMMU
> > support, with platform RISC-V IOMMU device implementation.
> >
Signed-off-by: Tomasz Jeznach
---
MAINTAINERS | 6 ++
1 file changed, 6 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index 43bd9afc19..ed8f65d879 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -1971,6 +1971,12 @@ F: include/hw/i2c/ppc4xx_i2c.h
F: hw/intc/ppc-uic.c
F: include/hw
Extend memory transaction attributes with process identifier to allow
per-request address translation logic to use requester_id / process_id
to identify memory mapping (e.g. enabling IOMMU w/ PASID translations).
Signed-off-by: Tomasz Jeznach
---
include/exec/memattrs.h | 6 ++
1 file
Adding virt machine property 'iommu' to enable/disable IOMMU
support, with platform RISC-V IOMMU device implementation.
Generate device tree entry for riscv-iommu device, along with
mapping all PCI device identifiers to the single IOMMU device
instance.
Signed-off-by: Tomasz Jeznac
Use iommu index as process identifier, linking transaction
memory attributes with translation request.
Signed-off-by: Tomasz Jeznach
---
hw/riscv/riscv-iommu.c | 11 +--
1 file changed, 9 insertions(+), 2 deletions(-)
diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c
index
.
Co-developed-by: Sebastien Boeuf
Signed-off-by: Sebastien Boeuf
Signed-off-by: Tomasz Jeznach
---
hw/riscv/Kconfig|3 +
hw/riscv/meson.build|1 +
hw/riscv/riscv-iommu-bits.h | 749 +++
hw/riscv/riscv-iommu-pci.c | 181 +++
hw/riscv/riscv-iommu-sys.c | 123 +
30719
Tomasz Jeznach (5):
hw/riscv: Introduction of RISC-V IOMMU device
MAINTAINERS: Add RISC-V IOMMU maintainers
exec/memtxattr: add process identifier to the transaction attributes
hw/riscv: IOMMU: use process identifier from transaction attributes.
hw/riscv: virt: support for RISC-V IOMMU pla
://lists.riscv.org/g/tech-iommu/message/3
[3]
https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/view
Signed-off-by: Tomasz Jeznach
---
hw/riscv/Kconfig |3 +
hw/riscv/meson.build |1 +
hw/riscv/rivos_iommu.c | 1350
Enable rivos-iommu device support in riscv:virt machine emulation.
Signed-off-by: Tomasz Jeznach
---
hw/riscv/Kconfig| 1 +
hw/riscv/virt.c | 115 +++-
include/hw/riscv/virt.h | 2 +
3 files changed, 94 insertions(+), 24 deletions(-)
diff
7; machine
emulation.
[1]
https://docs.google.com/document/d/1ytBZ6eDk1pAeBlZjDvm6_qqJbKQ0fMYKedyx0uoAGB0/view
[2] https://lists.riscv.org/g/tech-iommu/message/3
[3]
https://lore.kernel.org/qemu-devel/20220220085526.808674-1-a...@brainfault.org
Tomasz Jeznach (2):
hw/riscv: rivos-iommu: Baseli
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