[PATCH v3 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 89 1 file changed, 89 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 338b772732..6d28a29070 100644 --- a/tcg/loongarch64/tcg-target.c.inc

[PATCH v3 13/30] tcg/loongarch64: Implement deposit/extract ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 21 + tcg/loongarch64/tcg-target.h | 8 3 files changed, 26 insertions(+), 4 deletions(-) diff --git a/tcg

[PATCH v3 06/30] tcg/loongarch64: Define the operand constraints

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-str.h | 28 +++ tcg/loongarch64/tcg-target.c.inc | 52 2 files changed, 80 insertions(+) create mode 100644 tcg/loongarch64/tcg-target-con-str.h diff --git

[PATCH v3 07/30] tcg/loongarch64: Implement necessary relocation operations

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 66 1 file changed, 66 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index f0930f77ef..69e882ba5d 100644 --- a/tcg

[PATCH v3 14/30] tcg/loongarch64: Implement bswap{16,32,64} ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 32 tcg/loongarch64/tcg-target.h | 10 +- 2 files changed, 37 insertions(+), 5 deletions(-) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index

[PATCH v3 08/30] tcg/loongarch64: Implement the memory barrier op

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 32 1 file changed, 32 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 69e882ba5d..338b772732 100644 --- a/tcg

[PATCH v3 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Signed-off-by: WANG Xuerui Acked-by: Richard Henderson --- tcg/loongarch64/tcg-insn-defs.c.inc | 881 1 file changed, 881 insertions(+) create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg

[PATCH v3 01/30] elf: Add machine type value for LoongArch

-gdb.git;a=commit;h=01a8c731aacbdbed0eb5682d13cc074dc7e25fb3 Signed-off-by: WANG Xuerui --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 811bf4a1cb..3a4bcb646a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -182,6 +182,8 @@ typedef struct

[PATCH v3 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer

I ported the initial code, so I should maintain it of course. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index d7915ec128..859e5b5ba2 100644 --- a/MAINTAINERS +++ b/MAINTAINERS

[PATCH v3 03/30] tcg/loongarch64: Add the tcg-target.h file

Support for all optional TCG ops are initially marked disabled; the bits are to be set in individual commits later. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.h | 180 +++ 1 file changed, 180 insertions(+) create

Re: [PATCH v2 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts

Hi Richard, On 9/23/21 00:51, Richard Henderson wrote: On 9/21/21 1:19 PM, WANG Xuerui wrote: +    case 0b0001110: /* stle.w */ +    case 0b000: /* stle.d */ +    is_write = 1; +    break; +    default: +    /* test for am* instruction range

Re: [PATCH v2 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops

Hi Richard, On 9/23/21 00:29, Richard Henderson wrote: On 9/21/21 1:19 PM, WANG Xuerui wrote: +    /* Compare masked address with the TLB entry.  */ +    label_ptr[0] = s->code_ptr; +    tcg_out_opc_bne(s, TCG_REG_TMP0, TCG_REG_TMP1, 0); + +    /* TLB Hit - translate address using add

Re: [PATCH v2 20/30] tcg/loongarch64: Implement setcond ops

Hi Richard, On 9/22/21 23:13, Richard Henderson wrote: On 9/21/21 1:19 PM, WANG Xuerui wrote: +static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, +    TCGReg arg1, TCGReg arg2, bool c1, bool c2) +{ +    TCGReg tmp; + +    if (c1

Re: [PATCH v2 14/30] tcg/loongarch64: Implement bswap32_i32/bswap32_i64/bswap64_i64

Hi Richard, On 9/22/21 22:54, Richard Henderson wrote: On 9/21/21 1:18 PM, WANG Xuerui wrote: +    case INDEX_op_bswap32_i32: +    /* All 32-bit values are computed sign-extended in the register.  */ +    a2 = TCG_BSWAP_OS; +    /* fallthrough */ +    case INDEX_op_bswap32_i64

Re: [PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops

Hi Richard, On 9/22/21 12:35, Richard Henderson wrote: On 9/21/21 1:18 PM, WANG Xuerui wrote: +    case INDEX_op_eqv_i32: +    case INDEX_op_eqv_i64: +    if (c2) { +    /* guaranteed to fit due to constraint */ +    tcg_out_opc_xori(s, a0, a1, ~a2); +    } else

Re: [PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Hi Richard, On 9/22/21 23:17, Richard Henderson wrote: On 9/22/21 8:16 AM, WANG Xuerui wrote: Hi Richard, On 9/22/21 12:25, Richard Henderson wrote: On 9/21/21 1:18 PM, WANG Xuerui wrote: +    /* Test for PC-relative values that can be loaded faster.  */ +    intptr_t pc_offset = val

Re: [PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Hi Richard, On 9/22/21 12:25, Richard Henderson wrote: On 9/21/21 1:18 PM, WANG Xuerui wrote: +    /* Test for PC-relative values that can be loaded faster.  */ +    intptr_t pc_offset = val - (uintptr_t)s->code_ptr; This isn't quite right for split r^x code buffer. You should have s

Re: [PATCH v6 00/21] Add LoongArch linux-user emulation support

Hi Song, On 9/22/21 14:22, Song Gao wrote: Hi, Richard. On 09/21/2021 05:17 AM, Richard Henderson wrote: On 9/17/21 1:12 AM, Song Gao wrote: The 'o32' code has been deleted at the latest kernel [1]. This series only support linux-user emulation. I have now reviewed all but the linux-user/

Re: [PATCH v2 03/30] tcg/loongarch64: Add the tcg-target.h file

Hi Richard, On 9/22/21 11:55, Richard Henderson wrote: On 9/21/21 1:18 PM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   tcg/loongarch64/tcg-target.h | 180 +++   1 file changed, 180 insertions(+)   create mode 100644 tcg/loongarch64/tcg-target.h Reviewed

[PATCH v2 27/30] tcg/loongarch64: Register the JIT

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 44 1 file changed, 44 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 240e40374a..d599de3b17 100644 --- a/tcg

[PATCH v2 30/30] configure, meson.build: Mark support for loongarch64 hosts

Signed-off-by: WANG Xuerui --- configure | 7 ++- meson.build | 4 +++- 2 files changed, 9 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1043ccce4f..3a9035385d 100755 --- a/configure +++ b/configure @@ -659,6 +659,8 @@ elif check_define __arm__ ; then cpu=&quo

[PATCH v2 17/30] tcg/loongarch64: Implement add/sub ops

The neg_i{32,64} ops is fully expressible with sub, so omitted for simplicity. Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-set.h | 2 ++ tcg/loongarch64/tcg-target.c.inc | 38 2 files changed, 40 insertions(+) diff --git a/tcg/loongarch64/tcg

[PATCH v2 15/30] tcg/loongarch64: Implement clz/ctz ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 42 2 files changed, 43 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index d958183020

[PATCH v2 28/30] linux-user: Add safe syscall handling for loongarch64 hosts

Signed-off-by: WANG Xuerui --- linux-user/host/loongarch64/hostdep.h | 34 .../host/loongarch64/safe-syscall.inc.S | 80 +++ 2 files changed, 114 insertions(+) create mode 100644 linux-user/host/loongarch64/hostdep.h create mode 100644 linux-user/host

[PATCH v2 29/30] accel/tcg/user-exec: Implement CPU-specific signal handler for loongarch64 hosts

Signed-off-by: WANG Xuerui --- accel/tcg/user-exec.c | 78 +++ 1 file changed, 78 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..87660903b2 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c

[PATCH v2 13/30] tcg/loongarch64: Implement deposit/extract ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 21 + 2 files changed, 22 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con

[PATCH v2 26/30] tcg/loongarch64: Implement tcg_target_init

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 27 +++ 1 file changed, 27 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 9cdb283942..240e40374a 100644 --- a/tcg

[PATCH v2 24/30] tcg/loongarch64: Implement tcg_target_qemu_prologue

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 68 1 file changed, 68 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index bbb6b7f47d..0c413c4c95 100644 --- a/tcg

[PATCH v2 11/30] tcg/loongarch64: Implement sign-/zero-extension ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 82 2 files changed, 83 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target

[PATCH v2 25/30] tcg/loongarch64: Implement exit_tb/goto_tb

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 0c413c4c95..9cdb283942 100644 --- a/tcg/loongarch64

[PATCH v2 20/30] tcg/loongarch64: Implement setcond ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 74 1 file changed, 74 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index b0600a3dbd..08e6541dcf 100644 --- a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 23/30] tcg/loongarch64: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 332 +++ 2 files changed, 334 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 3ab0416d9f

[PATCH v2 19/30] tcg/loongarch64: Implement br/brcond ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 53 2 files changed, 54 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target

[PATCH v2 10/30] tcg/loongarch64: Implement goto_ptr

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 17 + tcg/loongarch64/tcg-target.c.inc | 15 +++ 2 files changed, 32 insertions(+) create mode 100644 tcg/loongarch64/tcg-target-con-set.h diff --git a/tcg

[PATCH v2 22/30] tcg/loongarch64: Implement simple load/store ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 131 +++ 2 files changed, 132 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target

[PATCH v2 21/30] tcg/loongarch64: Implement tcg_out_call

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 34 1 file changed, 34 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 08e6541dcf..44532ee1e4 100644 --- a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 08/30] tcg/loongarch64: Implement the memory barrier op

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 32 1 file changed, 32 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 69e882ba5d..338b772732 100644 --- a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 18/30] tcg/loongarch64: Implement mul/mulsh/muluh/div/divu/rem/remu ops

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 65 2 files changed, 66 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target

[PATCH v2 12/30] tcg/loongarch64: Implement not/and/or/xor/nor/andc/orc/eqv ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-set.h | 2 + tcg/loongarch64/tcg-target.c.inc | 101 +++ 2 files changed, 103 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 7e459490ea

[PATCH v2 06/30] tcg/loongarch64: Define the operand constraints

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-str.h | 28 +++ tcg/loongarch64/tcg-target.c.inc | 52 2 files changed, 80 insertions(+) create mode 100644 tcg/loongarch64/tcg-target-con-str.h diff --git a/tcg/loongarch64/tcg-target

[PATCH v2 16/30] tcg/loongarch64: Implement shl/shr/sar/rotl/rotr ops

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target-con-set.h | 1 + tcg/loongarch64/tcg-target.c.inc | 91 2 files changed, 92 insertions(+) diff --git a/tcg/loongarch64/tcg-target-con-set.h b/tcg/loongarch64/tcg-target-con-set.h index 2975e03127

[PATCH v2 14/30] tcg/loongarch64: Implement bswap32_i32/bswap32_i64/bswap64_i64

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 20 1 file changed, 20 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 27066960cf..e7b5f2c5ab 100644 --- a/tcg/loongarch64/tcg-target.c.inc +++ b/tcg

[PATCH v2 02/30] MAINTAINERS: Add tcg/loongarch64 entry with myself as maintainer

I ported the initial code, so I should maintain it of course. Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6c20634d63..66d1a17ca3 100644 --- a/MAINTAINERS +++ b/MAINTAINERS

[PATCH v2 05/30] tcg/loongarch64: Add register names, allocation order and input/output sets

Signed-off-by: WANG Xuerui Reviewed-by: Richard Henderson --- tcg/loongarch64/tcg-target.c.inc | 118 +++ 1 file changed, 118 insertions(+) create mode 100644 tcg/loongarch64/tcg-target.c.inc diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg

[PATCH v2 09/30] tcg/loongarch64: Implement tcg_out_mov and tcg_out_movi

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 89 1 file changed, 89 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index 338b772732..e4e7e5e903 100644 --- a/tcg/loongarch64/tcg-target.c.inc

[PATCH v2 04/30] tcg/loongarch64: Add generated instruction opcodes and encoding helpers

Signed-off-by: WANG Xuerui Acked-by: Richard Henderson --- tcg/loongarch64/tcg-insn-defs.c.inc | 873 1 file changed, 873 insertions(+) create mode 100644 tcg/loongarch64/tcg-insn-defs.c.inc diff --git a/tcg/loongarch64/tcg-insn-defs.c.inc b/tcg/loongarch64/tcg

[PATCH v2 00/30] LoongArch64 port of QEMU TCG

ything else I could see - Updated generated instruction definitions to latest - Reordered the configure/meson.build changes to come last v1: https://patchew.org/QEMU/20210920080451.408655-1-...@xen0n.name/ WANG Xuerui (30): elf: Add machine type value for LoongArch MAINTAINERS: Add tcg/loonga

[PATCH v2 03/30] tcg/loongarch64: Add the tcg-target.h file

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.h | 180 +++ 1 file changed, 180 insertions(+) create mode 100644 tcg/loongarch64/tcg-target.h diff --git a/tcg/loongarch64/tcg-target.h b/tcg/loongarch64/tcg-target.h new file mode 100644 index

[PATCH v2 01/30] elf: Add machine type value for LoongArch

Signed-off-by: WANG Xuerui --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 811bf4a1cb..3a4bcb646a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -182,6 +182,8 @@ typedef struct mips_elf_abiflags_v0 { #define EM_NANOMIPS 249

[PATCH v2 07/30] tcg/loongarch64: Implement necessary relocation operations

Signed-off-by: WANG Xuerui --- tcg/loongarch64/tcg-target.c.inc | 66 1 file changed, 66 insertions(+) diff --git a/tcg/loongarch64/tcg-target.c.inc b/tcg/loongarch64/tcg-target.c.inc index f0930f77ef..69e882ba5d 100644 --- a/tcg/loongarch64/tcg-target.c.inc

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Hi Peter, On 9/21/21 22:42, Peter Maydell wrote: On Mon, 20 Sept 2021 at 18:25, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui Be consistent with loongarch or loongarch64 everywhere. If there's no loongarch32, and never will be, then there's

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

On 9/21/21 22:07, WANG Xuerui wrote: Hi Richard, On 9/21/21 21:30, Richard Henderson wrote: On 9/20/21 11:02 PM, WANG Xuerui wrote: So should I drop the explicit probing for __loongarch64, instead just probe for __loongarch__ and later #error out the non-__loongarch64 cases individually

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Hi Richard, On 9/21/21 21:30, Richard Henderson wrote: On 9/20/21 11:02 PM, WANG Xuerui wrote: So should I drop the explicit probing for __loongarch64, instead just probe for __loongarch__ and later #error out the non-__loongarch64 cases individually? I'm ok with checking the __loongarch64

Re: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers

Hi Philippe, On 9/21/21 17:58, Philippe Mathieu-Daudé wrote: On 9/20/21 10:04, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   tcg/loongarch/tcg-insn-defs.c.inc | 1080 +   1 file changed, 1080 insertions(+)   create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Hi Philippe, On 9/21/21 14:59, Philippe Mathieu-Daudé wrote: On 9/21/21 08:02, WANG Xuerui wrote: On 9/21/21 01:23, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   configure   | 4 +++-   meson.build | 4 +++-   2 files changed, 6 insertions

Re: [PATCH 21/30] tcg/loongarch: Implement tcg_out_call

Hi Richard, On 9/21/21 00:35, Richard Henderson wrote: On 9/20/21 9:31 AM, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +    } else if (TCG_TARGET_REG_BITS == 32 || offset == (int32_t)offset) { +    /* long jump: +/- 2GiB */ +    tcg_out_opc_pcaddu12i(s

Re: [PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64

Hi Richard, On 9/20/21 23:11, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +    case INDEX_op_bswap32_i32: +    tcg_out_opc_revb_2h(s, a0, a1); +    tcg_out_opc_rotri_w(s, a0, a0, 16); +    break; +    case INDEX_op_bswap64_i64: +    tcg_out_opc_revb_d(s, a0

Re: [PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Hi Richard, On 9/21/21 01:23, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   configure   | 4 +++-   meson.build | 4 +++-   2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1043ccce4f..f1bc85e71b 100755

Re: [PATCH 07/30] tcg/loongarch: Implement necessary relocation operations

Hi Richard, On 9/20/21 22:36, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +static bool reloc_call(tcg_insn_unit *src_rw, const tcg_insn_unit *target) +{ +    const tcg_insn_unit *src_rx = tcg_splitwx_to_rx(src_rw); +    intptr_t offset = (intptr_t)target - (intptr_t)src_rx

Re: [PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers

Hi Richard, On 9/20/21 23:55, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   tcg/loongarch/tcg-insn-defs.c.inc | 1080 +   1 file changed, 1080 insertions(+)   create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc

Re: [PATCH 05/30] tcg/loongarch: Add register names, allocation order and input/output sets

Hi Richard, On 9/20/21 23:57, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: +    /* Argument registers */ +    TCG_REG_A0, +    TCG_REG_A1, +    TCG_REG_A2, +    TCG_REG_A3, +    TCG_REG_A4, +    TCG_REG_A5, +    TCG_REG_A6, +    TCG_REG_A7, +}; Generally I'd place

Re: [PATCH 03/30] tcg/loongarch: Add the tcg-target.h file

Hi Richard, On 9/20/21 22:23, Richard Henderson wrote: On 9/20/21 1:04 AM, WANG Xuerui wrote: Signed-off-by: WANG Xuerui ---   tcg/loongarch/tcg-target.h | 183 +   1 file changed, 183 insertions(+)   create mode 100644 tcg/loongarch/tcg-target.h diff --git

[PATCH 29/30] linux-user: Add host dependency for 64-bit LoongArch

Currently nothing special is needed for LoongArch hosts to work, so only leave a placeholder there. Signed-off-by: WANG Xuerui --- linux-user/host/loongarch64/hostdep.h | 11 +++ 1 file changed, 11 insertions(+) create mode 100644 linux-user/host/loongarch64/hostdep.h diff --git

[PATCH 22/30] tcg/loongarch: Implement simple load/store ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 131 + 2 files changed, 132 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index bcbf0780ff

[PATCH 25/30] tcg/loongarch: Implement exit_tb/goto_tb

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 19 +++ 1 file changed, 19 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 10df007087..585bf8dba0 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg

[PATCH 05/30] tcg/loongarch: Add register names, allocation order and input/output sets

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 118 + 1 file changed, 118 insertions(+) create mode 100644 tcg/loongarch/tcg-target.c.inc diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc new file mode 100644 index

[PATCH 04/30] tcg/loongarch: Add generated instruction opcodes and encoding helpers

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-insn-defs.c.inc | 1080 + 1 file changed, 1080 insertions(+) create mode 100644 tcg/loongarch/tcg-insn-defs.c.inc diff --git a/tcg/loongarch/tcg-insn-defs.c.inc b/tcg/loongarch/tcg-insn-defs.c.inc new file mode

[PATCH 28/30] configure, meson.build: Mark support for 64-bit LoongArch hosts

Signed-off-by: WANG Xuerui --- configure | 4 +++- meson.build | 4 +++- 2 files changed, 6 insertions(+), 2 deletions(-) diff --git a/configure b/configure index 1043ccce4f..f1bc85e71b 100755 --- a/configure +++ b/configure @@ -659,6 +659,8 @@ elif check_define __arm__ ; then cpu=&quo

[PATCH 01/30] elf: Add machine type value for LoongArch

Signed-off-by: WANG Xuerui --- include/elf.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/elf.h b/include/elf.h index 811bf4a1cb..3a4bcb646a 100644 --- a/include/elf.h +++ b/include/elf.h @@ -182,6 +182,8 @@ typedef struct mips_elf_abiflags_v0 { #define EM_NANOMIPS 249

[PATCH 09/30] tcg/loongarch: Implement tcg_out_mov and tcg_out_movi

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 73 ++ 1 file changed, 73 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 71564e3246..60783d7ddc 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 07/30] tcg/loongarch: Implement necessary relocation operations

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 84 ++ 1 file changed, 84 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 594b434b47..8be34f8275 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 12/30] tcg/loongarch: Implement not/and/or/xor/nor/andc/orc ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 2 + tcg/loongarch/tcg-target.c.inc | 69 ++ 2 files changed, 71 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 7e459490ea..385f503552

[PATCH 10/30] tcg/loongarch: Implement goto_ptr

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 17 + tcg/loongarch/tcg-target.c.inc | 15 +++ 2 files changed, 32 insertions(+) create mode 100644 tcg/loongarch/tcg-target-con-set.h diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg

[PATCH 03/30] tcg/loongarch: Add the tcg-target.h file

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.h | 183 + 1 file changed, 183 insertions(+) create mode 100644 tcg/loongarch/tcg-target.h diff --git a/tcg/loongarch/tcg-target.h b/tcg/loongarch/tcg-target.h new file mode 100644 index 00

[PATCH 30/30] accel/tcg/user-exec: Implement CPU-specific signal handler for LoongArch hosts

Signed-off-by: WANG Xuerui --- accel/tcg/user-exec.c | 83 +++ 1 file changed, 83 insertions(+) diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 8fed542622..0f85062e61 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c

[PATCH 18/30] tcg/loongarch: Implement mul/mulsh/muluh/div/divu/rem/remu ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 65 ++ 2 files changed, 66 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 58b5c487e2..57b2846d82

[PATCH 08/30] tcg/loongarch: Implement the memory barrier op

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 32 1 file changed, 32 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 8be34f8275..71564e3246 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 15/30] tcg/loongarch: Implement clz/ctz ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 31 ++ 2 files changed, 32 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index b0751c4bb0..417c97549a

[PATCH 14/30] tcg/loongarch: Implement bswap32_i32/bswap64_i64

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 10 ++ 1 file changed, 10 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index e5356bdaf8..d617b833e5 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg/loongarch/tcg

[PATCH 26/30] tcg/loongarch: Implement tcg_target_init

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 29 + 1 file changed, 29 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 585bf8dba0..107682e1fa 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 20/30] tcg/loongarch: Implement setcond ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 53 ++ 1 file changed, 53 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index a533a5619d..fb0143474a 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 00/30] 64-bit LoongArch port of QEMU TCG

is certainly appreciated! WANG Xuerui (30): elf: Add machine type value for LoongArch MAINTAINERS: Add tcg/loongarch entry with myself as maintainer tcg/loongarch: Add the tcg-target.h file tcg/loongarch: Add generated instruction opcodes and encoding helpers tcg/loongarch: Add register names

[PATCH 21/30] tcg/loongarch: Implement tcg_out_call

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 37 ++ 1 file changed, 37 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index fb0143474a..01c6002fdb 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 27/30] tcg/loongarch: Register the JIT

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 44 ++ 1 file changed, 44 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 107682e1fa..59adc92d26 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 16/30] tcg/loongarch: Implement shl/shr/sar/rotl/rotr ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 91 ++ 2 files changed, 92 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 417c97549a..8630d1ee6e

[PATCH 23/30] tcg/loongarch: Add softmmu load/store helpers, implement qemu_ld/qemu_st ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 2 + tcg/loongarch/tcg-target.c.inc | 344 + 2 files changed, 346 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index cdbfe9cd8d

[PATCH 06/30] tcg/loongarch: Define the operand constraints

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-str.h | 26 tcg/loongarch/tcg-target.c.inc | 48 ++ 2 files changed, 74 insertions(+) create mode 100644 tcg/loongarch/tcg-target-con-str.h diff --git a/tcg/loongarch/tcg-target-con

[PATCH 19/30] tcg/loongarch: Implement br/brcond ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 52 ++ 2 files changed, 53 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 57b2846d82..bcbf0780ff

[PATCH 24/30] tcg/loongarch: Implement tcg_target_qemu_prologue

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target.c.inc | 66 ++ 1 file changed, 66 insertions(+) diff --git a/tcg/loongarch/tcg-target.c.inc b/tcg/loongarch/tcg-target.c.inc index 0b6f16bde0..10df007087 100644 --- a/tcg/loongarch/tcg-target.c.inc +++ b/tcg

[PATCH 02/30] MAINTAINERS: Add tcg/loongarch entry with myself as maintainer

I wrote the initial code, so I should maintain it of course. Signed-off-by: WANG Xuerui --- MAINTAINERS | 5 + 1 file changed, 5 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 6c20634d63..0e9942cc00 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -3109,6 +3109,11 @@ S: Maintained

[PATCH 13/30] tcg/loongarch: Implement deposit/extract ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 21 + 2 files changed, 22 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 385f503552..b0751c4bb0 100644

[PATCH 11/30] tcg/loongarch: Implement sign-/zero-extension ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 1 + tcg/loongarch/tcg-target.c.inc | 82 ++ 2 files changed, 83 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 5cc4407367..7e459490ea

[PATCH 17/30] tcg/loongarch: Implement neg/add/sub ops

Signed-off-by: WANG Xuerui --- tcg/loongarch/tcg-target-con-set.h | 2 ++ tcg/loongarch/tcg-target.c.inc | 47 ++ 2 files changed, 49 insertions(+) diff --git a/tcg/loongarch/tcg-target-con-set.h b/tcg/loongarch/tcg-target-con-set.h index 8630d1ee6e..58b5c487e2

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