On Fri, 2024-06-14 at 11:28 +1000, Alistair Francis wrote:
> From: Wilfred Mallawa
>
> Setup Data Object Exchance (DOE) as an extended capability for the
> NVME
small typo here 邏️ [s/Setup Data Object Exchance/Setup Data Object
Exchange]
Wilfred
> controller and connect
Reviewed-by: Wilfred Mallawa
On Fri, 2024-06-14 at 11:28 +1000, Alistair Francis wrote:
> Add all of the defined protocols/features from the PCIe-SIG r6.0
> "Table 6-32 PCI-SIG defined Data Object Types (Vendor ID = 0001h)"
> table.
>
> Signed-off-by: Alistair Francis
On Tue, 2023-03-14 at 17:08 -0700, Max Filippov wrote:
> On Tue, Mar 14, 2023 at 4:41 PM Wilfred Mallawa
> wrote:
> >
> > On Tue, 2023-03-14 at 15:08 -0700, Max Filippov wrote:
> > > Linker script for xtensa tests must be preprocessed for a
> > > specif
changed, 1 insertion(+)
Wilfred Mallawa
>
> diff --git a/tests/tcg/xtensa/Makefile.softmmu-target
> b/tests/tcg/xtensa/Makefile.softmmu-target
> index 973e55298ee4..948c0e6506bd 100644
> --- a/tests/tcg/xtensa/Makefile.softmmu-target
> +++ b/tests/tcg/xtensa/Makefile.softmmu-t
ves: https://gitlab.com/qemu-project/qemu/-/issues/1493
> Signed-off-by: Peter Maydell
> ---
> hw/char/cadence_uart.c | 6 --
> 1 file changed, 4 insertions(+), 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
&g
On Mon, 2023-03-13 at 10:01 +, Peter Maydell wrote:
> On Mon, 13 Mar 2023 at 00:26, Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > Fixup a few minor typos
>
> Typo in patch subject line: should be 'block' :-)
Ha! already sent a V2 for t
From: Wilfred Mallawa
Fixup a few minor typos
Signed-off-by: Wilfred Mallawa
---
v2:
- Fixup typo in commit msg.
include/block/aio-wait.h | 2 +-
include/block/block_int-common.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/block/aio-wait.h b
From: Wilfred Mallawa
Fixup a few minor typos
Signed-off-by: Wilfred Mallawa
---
include/block/aio-wait.h | 2 +-
include/block/block_int-common.h | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/block/aio-wait.h b/include/block/aio-wait.h
index
nitor/monitor.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/monitor/monitor.c b/monitor/monitor.c
> index 8dc96f6af9..602535696c 100644
> --- a/monitor/monitor.c
> +++ b/monitor/monitor.c
> @@ -666,7 +666,7 @@ void mon
c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/monitor/hmp.c b/monitor/hmp.c
> index fee410362f..5cab56d355 100644
> --- a/monitor/hmp.c
> +++ b/monitor/hmp.c
> @@ -1167,7 +1167,7 @@ void handle_hmp_comman
e Mathieu-Daudé
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Kevin Wolf
> Signed-off-by: Stefan Hajnoczi
> ---
> block/io.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/block/io.c b/block/io.c
> index 8
e substituted.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Kevin Wolf
> Signed-off-by: Stefan Hajnoczi
> ---
> block/graph-lock.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Wilfred Mallawa
>
context_release() is never called anyway.
>
> Reviewed-by: Philippe Mathieu-Daudé
> Tested-by: Philippe Mathieu-Daudé
> Reviewed-by: Kevin Wolf
> Signed-off-by: Stefan Hajnoczi
> ---
> block/export/export.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Review
> entirely.
>
> Reviewed-by: Kevin Wolf
> Signed-off-by: Stefan Hajnoczi
> ---
> block/block-backend.c | 8 +---
> 1 file changed, 1 insertion(+), 7 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/block/block-backend.c b/block/block-backend.c
>
> ---
> target/riscv/vector_helper.c | 36 ---
> --
> target/riscv/vector_internals.c | 24 ++
> target/riscv/vector_internals.h | 16 +++
> 3 files changed, 40 insertions(+), 36 deletions(-)
>
Reviewed-by: Wi
> 1 file changed, 14 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-
> ci.d/crossbuilds.yml
> index 3ce51adf77..419b0c2fe1 100644
> --- a/.gitlab-ci.d/crossbuilds.yml
> +++ b/.gitlab-ci.d/crossbuilds.yml
> @@ -1,13 +1,6 @
ly that anybody is still seriously using QEMU on a 32-bit arm
> CPU, so we deprecate the 32-bit arm hosts here to finally save use
> some time and precious CI minutes.
>
> Signed-off-by: Thomas Huth
> ---
> docs/about/deprecated.rst | 9 +
> 1 file changed, 9 insert
ready, so we don't really need
> qemu-system-arm anymore, thus deprecated it now.
>
> Signed-off-by: Thomas Huth
> ---
> docs/about/deprecated.rst | 10 ++
> 1 file changed, 10 insertions(+)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/docs/about/deprecated.rst
> 1 file changed, 16 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-
> ci.d/crossbuilds.yml
> index 101416080c..3ce51adf77 100644
> --- a/.gitlab-ci.d/crossbuilds.yml
> +++ b/.gitlab-ci.d/crossbuilds.yml
> @@ -43,22
> old
> 32-bit stuff.
>
> Signed-off-by: Thomas Huth
> ---
> docs/about/deprecated.rst | 12 ++++
> 1 file changed, 12 insertions(+)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst
> index 11700adac9..a30
t
> > qemu-system-i386 binary here:
> >
> > https://lore.kernel.org/kvm/y%2ffkts5ajfy0h...@google.com/
> >
> > Signed-off-by: Thomas Huth
> > ---
> > docs/about/deprecated.rst | 12 ++++
> > 1 file changed, 12 insertions(+)
>
> Reviewed-by: Daniel P. Berrangé
Reviewed-by: Wilfred Mallawa
>
>
> With regards,
> Daniel
From: Wilfred Mallawa
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Memory layout as per [1]
[1]
https://github.com/lowRISC/opentitan/blob/565e4af39760a123c59a184aa2f5812a961fde47
From: Wilfred Mallawa
Updates the opentitan IRQs to match the latest supported commit of
Opentitan from TockOS.
OPENTITAN_SUPPORTED_SHA := 565e4af39760a123c59a184aa2f5812a961fde47
Signed-off-by: Wilfred Mallawa
---
include/hw/riscv/opentitan.h | 10 +-
1 file changed, 5 insertions
On Wed, 2023-01-04 at 22:30 +1000, Alistair Francis wrote:
> On Thu, Dec 22, 2022 at 8:40 AM Alistair Francis
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > use the `FIELD32_1CLEAR` macro to implement register
> > `rw1c` functionality to `ibex_spi`.
> &
ld CPU reset handlers with system emulation
>
Reviewed-by: Wilfred Mallawa
> hw/core/meson.build | 2 +-
> target/i386/cpu.c | 2 +-
> target/i386/helper.c | 2 +-
> target/loongarch/cpu.c | 2 ++
> target/s390x/cpu.c | 4 +++-
> 5 files changed, 8 insertions(+), 4 deletions(-)
>
t from interrupt source
> 0 and add a comment to make it crystal clear.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Reviewed-by: Wilfred Mallawa
Wilfred
> ---
>
> (no changes since v1)
>
> include/hw/riscv/microchip_pfsoc.h | 2 +-
> include/hw/riscv/
BROKEN and drop the selection from
> RISC-V machines.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Reviewed-by: Wilfred Mallawa
Wilfred
> ---
>
> (no changes since v1)
>
> hw/intc/Kconfig | 1 +
> hw/riscv/Kconfig | 5 -
> 2 files changed, 1 insert
On Wed, 2022-12-07 at 18:03 +0800, Bin Meng wrote:
> SHAKTI_C machine Kconfig option was inserted in disorder. Fix it.
>
> Signed-off-by: Bin Meng
> Reviewed-by: Alistair Francis
Reviewed-by: Wilfred Mallawa
Wilfred
> ---
>
> (no changes since v1)
>
On Wed, 2022-12-07 at 17:00 +0800, Bin Meng wrote:
> There are 2 paths in helper_sret() and the same mstatus update codes
> are replicated. Extract the common parts to simplify it a little bit.
>
> Signed-off-by: Bin Meng
Reviewed-by: Wilfred Mallawa
Wilfred
> ---
>
ry is configured")
> Signed-off-by: Bin Meng
> ---
>
> target/riscv/op_helper.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c
> index 09f1f5185d..d7af7f056b
On Mon, 2022-12-05 at 16:21 +0800, Bin Meng wrote:
> On Fri, Dec 2, 2022 at 8:28 AM Wilfred Mallawa
> wrote:
> >
> > On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> > > The pending register upper limit is currently set to
> > > plic->num_sources
> iotests/check: Fix typing for sys.exit() value
> python: add 3.11 to supported list
>
> python/setup.cfg | 6 --
> tests/qemu-iotests/check | 2 +-
> 2 files changed, 5 insertions(+), 3 deletions(-)
>
> --
> 2.38.1
>
I see you've left Westeros! xD
Reviewed-by: Wilfred Mallawa
>
>
; ---
> docs/devel/acpi-bits.rst | 3 +++
> 1 file changed, 3 insertions(+)
Reviewed-by: Wilfred Mallawa
>
> diff --git a/docs/devel/acpi-bits.rst b/docs/devel/acpi-bits.rst
> index 4a94c7d83d..9eb4b9e666 100644
> --- a/docs/devel/acpi-bits.rst
> +++ b/docs/devel/acpi-bits.
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> The pending register upper limit is currently set to
> plic->num_sources >> 3, which is wrong, e.g.: considering
> plic->num_sources is 7, the upper limit becomes 0 which fails
> the range check if reading the pending register at pending_base.
>
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> "hartid-base" and "priority-base" are zero by default. There is no
> need to initialize them to zero again.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/opentitan.c | 2 --
> 1 file changed,
gt;
> hw/riscv/sifive_u.c | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index b139824aab..b40a4767e2 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@
e.cdn.prismic.io/sifive/3af39c59-6498-471e-9dab-5355a0d539eb_fe310-g003-manual.pdf
>
> Fixes: eb637edb1241 ("SiFive Freedom E Series RISC-V Machine")
> Signed-off-by: Bin Meng
> ---
>
> include/hw/riscv/sifive_e.h | 7 ++-
> 1 file changed, 6 insertions(+), 1 del
hanged, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/include/hw/riscv/microchip_pfsoc.h
> b/include/hw/riscv/microchip_pfsoc.h
> index a757b240e0..9720bac2d5 100644
> --- a/include/hw/riscv/microchip_pfsoc.h
> +++ b/include
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> H-mode has been removed since priv spec 1.10. Drop it.
>
> Signed-off-by: Bin Meng
> ---
>
> include/hw/intc/sifive_plic.h | 1 -
> hw/intc/sifive_plic.c | 1 -
> 2 files changed, 2 deletions(-)
Revi
On Thu, 2022-12-01 at 22:08 +0800, Bin Meng wrote:
> PLIC is not included in the 'spike' machine.
>
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/spike.c | 1 -
> 1 file changed, 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/riscv/spike.c b/hw/riscv
> Signed-off-by: Bin Meng
> ---
>
> hw/riscv/Kconfig | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig
> index 167dc4cca6..1e4b58024f 100644
> --- a/hw/riscv/Kconfig
> +++ b/hw/riscv/Kconf
ull << i*16);
> ^
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> tcg/s390x/tcg-target.c.inc | 20 ++--
> 1 file changed, 10 insertions(+), 10 deletions(-)
Reviewed-by: Wilfred Mallawa
>
> diff --git
é
> ---
> hw/core/machine.c | 1 +
> include/hw/boards.h | 1 -
> 2 files changed, 1 insertion(+), 1 deletion(-)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/hw/core/machine.c b/hw/core/machine.c
> index 8d34caa31d..42fc6f1e84 100644
> --- a/hw/core/machine.c
> +++ b/hw/co
139 | void replay_read_next_clock(unsigned int kind);
> | ^~
>
> Fixes: 8eda206e090 ("replay: recording and replaying clock ticks")
> Signed-off-by: Richard Henderson
> ---
> replay/replay-internal.h | 2 +-
> 1 file changed, 1 insertion
ime. Let's officially assign it to 9p
> maintainers.
>
> Signed-off-by: Christian Schoenebeck
> ---
> MAINTAINERS | 1 +
> 1 file changed, 1 insertion(+)
>
Reviewed-by: Wilfred Mallawa
> diff --git a/MAINTAINERS b/MAINTAINERS
> index cf24910249..4f156a99f1 100644
>
On Tue, 2022-11-29 at 09:38 +0800, weiwei wrote:
>
> On 2022/11/29 07:06, Wilfred Mallawa wrote:
>
> > On Mon, 2022-11-28 at 20:29 +0800, Weiwei Li wrote:
> >
> > > Modify the check for C extension to Zca (C implies Zca)
> > >
> > > Signed-
/*
> + * Zca support all of the existing C extension, excluding
> all
> + * compressed floating point loads and stores
> + */
Look like a typo: *`supports` and *`C extensions`
> + if (!ctx->cfg_ptr->ext_zca) {
> gen_exception_illegal(ctx);
> } else {
> ctx->opcode = opcode;
otherwise,
Reviewed-by: Wilfred Mallawa
Wilfred
From: Wilfred Mallawa
This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.
Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note
From: Wilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Bin Meng
Reviewed-by: Alistair Francis
---
hw/riscv/opentitan.c | 3 +++
include
From: Wilfred Mallawa
This patch provides updates to the OpenTitan model to bump to RTL
version .
A unique change here is the merger of hwip `padctrl` into `pinmux`, to
reflect this change, any references to `padctrl` are removed.
Additionally, an unimplemented device for `aon_timer` is added
From: Wilfred Mallawa
Adds the updated `aon_timer` base as an unimplemented device. This is
used by TockOS, patch ensures the guest doesn't hit load faults.
Signed-off-by: Wilfred Mallawa
---
hw/riscv/opentitan.c | 3 +++
include/hw/riscv/opentitan.h | 1 +
2 files changed, 4
From: Wilfred Mallawa
This patch updates the OpenTitan model to match
the specified register layout as per [1]. Which is also the latest
commit of OpenTitan supported by TockOS.
Note: Pinmux and Padctrl has been merged into Pinmux [2][3], this patch removes
any references to Padctrl. Note
From: Wilfred Mallawa
This patch provides updates to the OpenTitan model to bump to RTL
version .
A unique change here is the merger of hwip `padctrl` into `pinmux`, to
reflect this change, any references to `padctrl` are removed.
Additionally, an unimplemented device for `aon_timer` is added
From: Wilfred Mallawa
Adds a helper macro that implements the register `w1c`
functionality.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
If ANY bits of the specified `FIELD` is set
then the respective field is cleared and returned to `data`.
If the field is cleared (0
From: Wilfred Mallawa
use the `FIELD32_1CLEAR` macro to implement register
`rw1c` functionality to `ibex_spi`.
This change was tested by running the `SPI_HOST` from TockOS.
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host.c | 21 +
1 file changed, 9 insertions
From: Wilfred Mallawa
This patch series implements a `FIELDx_1CLEAR()` macro and implements it
in the `hw/ssi/ibex_spi.c` model.
*** Changelog ***
Since v2:
- change the macro arguments name to match
the existing macros.
(reg_val, reg, field
On Mon, 2022-10-10 at 11:29 +1000, Alistair Francis wrote:
> On Tue, Sep 27, 2022 at 10:58 AM Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > Changes from V1:
> > * Instead of needing all field bits to be set
> > we cl
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 36
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html
Fixes: Coverity CID 1488107
Signed-off
From: Wilfred Mallawa
The remaining patches in this series address:
- Coverity issues for `ibex_spi`
- Adds rw1c functionality
Changes since V4:
- Fixup compiler warning for unused variable `data` in [1/2]
Wilfred Mallawa (2):
hw/ssi: ibex_spi: fixup coverity issue
From: Wilfred Mallawa
Connects the ibex lifecycle controller with opentitan,
with this change, we can now get past the lifecycle checks
in the boot rom.
Signed-off-by: Wilfred Mallawa
---
hw/riscv/opentitan.c | 10 --
include/hw/riscv/opentitan.h | 2 ++
2 files changed, 10
From: Wilfred Mallawa
Device model for the OpenTitan lifecycle controller as per [1].
Addition of this model is the first of many steps to adding `boot_rom`
support for OpenTitan. The OpenTitan `boot_rom` needs to access the
lifecycle controller during the init/test sequence before it jumps
From: Wilfred Mallawa
This series of patches:
- Add OpenTitan lifecycle controller with basic functionality
- Connects it to OpenTitan
Currently in OpenTitan, we skip the `boot_rom` since is has become more
complex and we do not have all the support in QEMU to use it. One
From: Wilfred Mallawa
Changes from V1:
* Instead of needing all field bits to be set
we clear the field if any are set. If the field is
0/clear then no change.
Adds a helper macro that implements the register `w1c`
functionality.
Ex:
uint32_t data
on_id = 5,
> + .minimum_version_id = 5,
> .post_load = riscv_cpu_post_load,
> .fields = (VMStateField[]) {
> VMSTATE_UINTTL_ARRAY(env.gpr, RISCVCPU, 32),
> @@ -331,7 +331,7 @@ const VMStateDescription vmstate_riscv_cpu = {
> VMSTATE_UINT32(env.features, RISCVCPU),
> VMSTATE_UINTTL(env.priv, RISCVCPU),
> VMSTATE_UINTTL(env.virt, RISCVCPU),
> - VMSTATE_UINTTL(env.resetvec, RISCVCPU),
> + VMSTATE_UINT64(env.resetvec, RISCVCPU),
> VMSTATE_UINTTL(env.mhartid, RISCVCPU),
> VMSTATE_UINT64(env.mstatus, RISCVCPU),
> VMSTATE_UINT64(env.mip, RISCVCPU),
Reviewed by: Wilfred Mallawa
Ping!
https://lore.kernel.org/qemu-devel/20220901010220.495112-1-wilfred.mall...@opensource.wdc.com/
Wilfred
On Fri, 2022-09-02 at 01:18 +0200, Philippe Mathieu-Daudé wrote:
> On 1/9/22 07:32, Richard Henderson wrote:
> > On 9/1/22 02:02, Wilfred Mallawa wrote:
> > > Fro
es serial_hds in realize function, thus can't be
> used twice */
> dc->user_creatable = false;
Nice! I tested this on https://github.com/tock/tock/pull/3056 , with
the addition of `global
driver=riscv.lowrisc.ibex.soc,property=resetvec,value=0x2450 `
Alot more convienient with this patch for when the entry point changes,
will look into parsing the manifest to dynamically set it!
Reviewed by: Wilfred Mallawa
_abort);
> - object_property_set_int(OBJECT(>cpus), "resetvec",
> 0x2490,
> + object_property_set_int(OBJECT(>cpus), "resetvec",
> 0x2400,
> _abort);
> sysbus_realize(SYS_BUS_DEVICE(>cpus), _fatal);
>
Reviewed by: Wilfred Mallawa
From: Wilfred Mallawa
Adds a helper macro that implements the `rw1c`
behaviour.
Ex:
uint32_t data = FIELD32_1CLEAR(val, REG, FIELD);
if the specified `FIELD` is set (single/multi bit all fields)
then the respective field is cleared and returned to `data`.
If ALL bits of the bitfield
From: Wilfred Mallawa
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 34
From: Wilfred Mallawa
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html
Fixes: Coverity CID 1488107
Signed-off
From: Wilfred Mallawa
Patch V4 fixes up:
- Fixup missing register field clearing on tx/rx_fifo_reset() in [2/4]
Testing:
- Tested with Opentitan unit tests for TockOS...[OK]
Wilfred Mallawa (4):
hw/ssi: ibex_spi: fixup typos in ibex_spi_host
hw/ssi: ibex_spi: fixup coverity issue
On Mon, 2022-08-22 at 13:42 +1000, Alistair Francis wrote:
> On Mon, Aug 22, 2022 at 9:53 AM Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > This patch addresses the coverity issues specified in [1],
> > as suggested, `FIELD_DP3
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
[1] https://www.mail-archive.com/qemu-devel@nongnu.org/msg887713.html
Fixes: Coverity CID 1488107
Signed-off
From: Wilfred Mallawa
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1
From: Wilfred Mallawa
This patch series cleans up the ibex_spi driver,
fixes the specified coverity issue,
implements register rw1c functionality and
updates an incorrect register offset.
Patch V3 fixes up:
- Style errors (excess indentation on multi-line)
- Remove patch note from
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 34
From: Wilfred Mallawa
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi
From: Wilfred Mallawa
Updates the `EVENT_ENABLE` register to offset `0x34` as per
OpenTitan spec [1].
[1] https://docs.opentitan.org/hw/ip/spi_host/doc/#Reg_event_enable
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
---
hw/ssi/ibex_spi_host.c | 34
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
Patch V2: Style changes have been made as suggested by
Andrew Jones, to promote code readability.
[1] https://www.mail
From: Wilfred Mallawa
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa
Reviewed-by: Alistair Francis
Reviewed-by: Andrew Jones
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi
From: Wilfred Mallawa
This patch series (note V2) cleans up the ibex_spi driver,
fixes the specified coverity issue,
implements register rw1c functionality and
updates an incorrect register offset.
In V2, the following changes are made.
- New patch [4/4] to isolate the register address offset
On Thu, 2022-08-11 at 10:55 +0800, Bin Meng wrote:
> On Thu, Aug 11, 2022 at 8:58 AM Wilfred Mallawa
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > This patch addresses the coverity issues specified in [1],
> > as suggested, `FIELD_DP32()`/`FIELD_EX32
From: Wilfred Mallawa
The following patch updates opentitan to match the new configuration,
as per, lowRISC/opentitan@217a0168ba118503c166a9587819e3811eeb0c0c
Note: with this patch we now skip the usage of the opentitan
`boot_rom`. The Opentitan boot rom contains hw verification
for devies
From: Wilfred Mallawa
This patch adds the `rw1c` functionality to the respective
registers. The status fields are cleared when the respective
field is set.
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host.c | 36 +++---
include/hw/ssi/ibex_spi_host.h
From: Wilfred Mallawa
This patch fixes up minor typos in ibex_spi_host
Signed-off-by: Wilfred Mallawa
---
hw/ssi/ibex_spi_host.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c
index d14580b409..601041d719 100644
From: Wilfred Mallawa
This patch addresses the coverity issues specified in [1],
as suggested, `FIELD_DP32()`/`FIELD_EX32()` macros have been
implemented to clean up the code.
Additionally, the `EVENT_ENABLE` register is correctly updated
to addr of `0x34`.
[1] https://www.mail-archive.com
r Francis
> wrote:
> >
> > From: Wilfred Mallawa
> >
> > The following change was made to rectify incorrectly set stride
> > length
> > on the PLIC. Where it should be 32bit and not 24bit (0x18). This
> > was
>
> PLIC [1]
Thanks, wil
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