Michael S. Tsirkin wrote on 2015-09-13:
> On Fri, Sep 11, 2015 at 05:39:07PM +0200, Claudio Fontana wrote:
>> On 09.09.2015 09:06, Michael S. Tsirkin wrote:
>>
>> There are many consequences to this, offset within BAR alone is not
>> enough, there are multiple things at the virtio level that need
Claudio Fontana wrote on 2015-09-07:
> Coming late to the party,
>
> On 31.08.2015 16:11, Michael S. Tsirkin wrote:
>> Hello!
>> During the KVM forum, we discussed supporting virtio on top
>> of ivshmem. I have considered it, and came up with an alternative
>> that has several advantages over
Eric Blake wrote on 2014-11-06:
Hi Eric
Thanks for your review and comment.
On 11/06/2014 12:08 PM, Li Liang wrote:
Instead of sending the guest memory directly, this solution compress
the ram page before sending, after receiving, the data will be
decompressed.
This feature can help to
Stefano Stabellini wrote on 2014-11-10:
On Mon, 10 Nov 2014, Zhang, Yang Z wrote:
Igor Mammedov wrote on 2014-05-23:
if user starts QEMU with -machine pc,accel=xen, then compat
property in xenfv won't work and it would cause error:
Unsupported bus. Bus doesn't have property 'acpi-pcihp-bsel
Igor Mammedov wrote on 2014-05-23:
if user starts QEMU with -machine pc,accel=xen, then compat property
in xenfv won't work and it would cause error:
Unsupported bus. Bus doesn't have property 'acpi-pcihp-bsel' set
when PCI device is added with -device on QEMU CLI.
In case of Xen instead of
Zhang Haoyu wrote on 2014-08-29:
Hi, Yang, Gleb, Michael,
Could you help review below patch please?
I don't quite understand the background. Why ioacpi-irr is setting before EOI?
It should be driver's responsibility to clear the interrupt before issuing EOI.
Thanks,
Zhang Haoyu
Hi
Paolo Bonzini wrote on 2014-06-03:
Il 30/05/2014 10:59, Tiejun Chen ha scritto:
+static int create_pch_isa_bridge(PCIBus *bus, XenHostPCIDevice *hdev)
+{
+struct PCIDevice *dev;
+
+char rid;
+
+dev = pci_create(bus, PCI_DEVFN(0x1f, 0), intel-pch-isa-bridge);
This is really a
Fabio Fantoni wrote on 2014-05-19:
Il 19/05/2014 08:44, Gerd Hoffmann ha scritto:
Hi,
+/* + * Some video bioses and gfx drivers will assume the bdf
of IGD is 00:02.0. + * So user need to set it to 00:02.0 in Xen
configure file explicitly, + * otherwise IGD will fail to
Konrad Rzeszutek Wilk wrote on 2014-05-16:
On Fri, May 16, 2014 at 06:53:42PM +0800, Tiejun Chen wrote:
Some registers of Intel IGD are mapped in host bridge, so it needs to
passthrough these registers of physical host bridge to guest because
emulated host bridge in guest doesn't have these
Anthony PERARD wrote on 2014-03-22:
On Fri, Feb 21, 2014 at 02:44:09PM +0800, Yang Zhang wrote:
From: Yang Zhang yang.z.zh...@intel.com
basic gfx passthrough support:
- add a vga type for gfx passthrough
- retrieve VGA bios from host 0xC, then load it to guest 0xC
-
Zhang, Yang Z wrote on 2014-02-21:
From: Yang Zhang yang.z.zh...@intel.com
The following patches are ported from Xen Qemu-traditional branch
which are adding Intel IGD passthrough supporting to Qemu upstream.
To pass through IGD to guest, user need to add following lines in Xen
config
Sanjay Lal wrote on 2013-03-02:
The following patchset implements KVM support for MIPS32 processors,
using Trap Emulate, with basic runtime binary translation to improve
performance.
In KVM mode, CPU virtualization is handled via the kvm kernel module,
while system and I/O virtualization
update_in_progress(RTCState *s)
Best regards,
Yang
-Original Message-
From: Stefan Weil [mailto:s...@weilnetz.de]
Sent: Tuesday, September 11, 2012 1:14 PM
To: Zhang, Yang Z
Cc: Paolo Bonzini; qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] buildbot failure in qemu on default_mingw32
MinGW
Paolo Bonzini wrote on 2012-09-11:
Il 11/09/2012 09:05, Zhang, Yang Z ha scritto:
how about the following patch:
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c index d63554f..30bbbe6
100644 --- a/hw/mc146818rtc.c +++ b/hw/mc146818rtc.c @@ -556,14 +556,14
@@ static void rtc_set_cmos
Paolo Bonzini wrote on 2012-08-02:
The current RTC emulation has two timers firing every second, one
on each edge of the UIP bit. This will prevent CPUs from staying at
deep C-states. Intel's measurements from previous submissions show the
C6 residency reduced by 6% when running 64 idle
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Cc: 'qemu-devel@nongnu.org'; 'aligu...@us.ibm.com'
Subject: Re: [PATCH v6 0/7] RTC: New logic to emulate RTC
Il 17/05/2012 04:28, Zhang, Yang Z ha scritto:
Changes in v6:
Rebase
Changes in v6:
Rebase to latest QEMU
Fix a bug that fail to pass tests/rtc-test:
In previous version, it uses host time as the base point to calculate
guest RTC. It works when guest uses host based clock. But for vm and rt based
clock, it's wrong. Because guest's clock may not
Use offset instead of timer to calculate guest rtc. Guest rtc is calculated by
(base_rtc + guest_time_now - guest_time_last_update_rtc + offset).
Base_rtc means the rtc value of last update.
Guest_time_now means the guest time that access happens.
Guest_time_last_update means the guest time of
Change DM(date mode) and 24/12 control bit doesn't affect the internal
registers. It only indicates what format is using for those registers.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 10 +-
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git
The UIP will be set when updating cycle begins and cleared after updated cycle
ended.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 18 ++
1 files changed, 18 insertions(+), 0 deletions(-)
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index
There are no need to run a periodic timer to emulate updated-end
logic. Only run the timer when the UF is cleared.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 95 +
1 files changed, 87 insertions(+), 8 deletions(-)
Use a timer to emulate alarm. The timer runs only when the AF is cleared.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 276 ++
1 files changed, 257 insertions(+), 19 deletions(-)
diff --git a/hw/mc146818rtc.c
The new logic is compatible with old. So should not block to migrate
from old QEMU. But new version cannot migrate to old.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 43 ---
1 files changed, 40 insertions(+), 3 deletions(-)
The first update cycle begins one - half seconds later when divider reset is
removing.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 46 --
1 files changed, 40 insertions(+), 6 deletions(-)
diff --git a/hw/mc146818rtc.c
Changes in v5:
Rebase to latest head.
Add Checking of divider, because it also can stop the update.
Fixing some bugs.
Changes in v4:
Rebase to latest head.
Changing in patch 6:
Set the timer to one second earlier before target alarm when AF bit is
clear. In version 3, in order to solve
There are no need to run a periodic timer to emulate updated-end
logic. Only run the timer when the UF or AF was clear.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 94 +
1 files changed, 86 insertions(+), 8
The first update cycle begins one - half seconds later when divider
reset is removing.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 61 +
1 files changed, 51 insertions(+), 10 deletions(-)
diff --git
The UIP(update in progress) is set when RTC is updating. And the update cycle
begins 244us later after UIP is set. And it is cleared when update end.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 18 ++
1 files changed, 18 insertions(+), 0
Add alarm support.
Set the timer to one second earlier before target alarm when AF bit is clear.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 273 ++
1 files changed, 254 insertions(+), 19 deletions(-)
diff --git
There has no need to use two periodic timer to update RTC time. In this patch,
we only update it when guest reading it.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 207 +-
1 files changed, 66 insertions(+), 141
Change DM(date mode) and 24/12 control bit don't affect the internal registers.
It only indicates what format is using for those registers. So we don't need to
update time format when it is modified.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 10 +-
1
The new logic is compatible with old. So should not block to migrate
from old version. But new version cannot migrate to old.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 35 +++
1 files changed, 31 insertions(+), 4 deletions(-)
diff
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Wednesday, May 09, 2012 9:07 PM
Subject: Re: PATCH v5 0/7] RTC: New logic to emulate RTC
At last this passes my tests, great! There's still a few problems, but more
or less it's ok:
1) it needs rebase
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Tuesday, March 20, 2012 10:16 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Paolo Bonzini; aligu...@us.ibm.com;
k...@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v4 2/7] RTC: Update
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Wednesday, March 21, 2012 1:39 AM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Paolo Bonzini; aligu...@us.ibm.com;
k...@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v4 4/7] RTC: Set
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Wednesday, March 21, 2012 2:04 AM
On Mon, 19 Mar 2012, Zhang, Yang Z wrote:
Use a timer to emulate update cycle. When update cycle ended and UIE is
setting, then raise an interrupt
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
I attach a patch that fixes some problems with divider reset and in
general simplifies the logic. Even with the patch, however, I still see
failures in my test case unfortunately. Probably there are rounding
errors
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Il 22/03/2012 01:23, Zhang, Yang Z ha scritto:
Actually, I also see some failures during testing. And most of them
are fail to pass the 244us update cycle checking. Since we are in
emulation environment, we
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Thursday, March 22, 2012 11:05 AM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; aligu...@us.ibm.com; k...@vger.kernel.org
Subject: Re: [PATCH v4 0/7] RTC: New logic to emulate RTC
Il 22/03/2012 04:03, Zhang
-Original Message-
From: Stefano Stabellini [mailto:stefano.stabell...@eu.citrix.com]
Sent: Tuesday, March 20, 2012 10:05 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Paolo Bonzini; aligu...@us.ibm.com;
k...@vger.kernel.org
Subject: Re: [Qemu-devel] [PATCH v4 1/7] RTC: Remove
Changes in v4:
Rebase to latest head.
Changing in patch 6:
Set the timer to one second earlier before target alarm when AF bit is
clear. In version 3, in order to solve the async between UF, AF and UIP, the
timer will keep running when UF or AF are clear. This is a little ugly,
The UIP(update in progress) is set when RTC is updating. And the update cycle
begins 244us later after UIP is set. And it is cleared when update end.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 18 ++
1 files changed, 18 insertions(+), 0
The first update cycle begins one - half seconds later when divider reset is
removing.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 38 +-
1 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/hw/mc146818rtc.c
Changing in this patch:
Set the timer to one second earlier before target alarm when AF bit is
clear. In version 3, in order to solve the async between UF, AF and UIP, the
timer will keep running when UF or AF are clear. This is a little ugly,
especially when a userspace program is
Use a timer to emulate update cycle. When update cycle ended and UIE is
setting, then raise an interrupt. The timer runs only when UF or AF is cleared.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 86 ++
1 files
There has no need to use two periodic timer to update RTC time. In this patch,
we only update it when guest reading it.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 207 +-
1 files changed, 66 insertions(+), 141
The new logic is compatible with old. So it should not block migrate from old
version. But new version cannot migrate to old.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 48
1 files changed, 44 insertions(+), 4
Change DM(date mode) and 24/12 control bit don't affect the internal registers.
It only indicates what format is using for those registers. So we don't need to
update time format when it is modified.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 10 +-
1
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Wednesday, March 14, 2012 4:35 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Jan Kiszka; k...@vger.kernel.org;
aligu...@us.ibm.com; Marcelo Tosatti
Subject: Re: [PATCH v3 0/7] RTC: New logic to emulate RTC
Is there any comments with the version 3?
best regards
yang
-Original Message-
From: Zhang, Yang Z
Sent: Friday, March 02, 2012 2:59 PM
To: qemu-devel@nongnu.org
Cc: Jan Kiszka; k...@vger.kernel.org; k...@vger.kernel.org;
aligu...@us.ibm.com;
Paolo Bonzini; Marcelo Tosatti
Hi all
Currently, if not using nonblocking mode, the default timeout of
select() in main_loop_wait is 1000ms. There has no problem if you run few VMs.
But when running more VMs like 32 or 64, then the problem is coming. Our
experience shows that when running 64 idle VMs, the pkg C6
-Original Message-
From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
Sent: Friday, March 09, 2012 9:36 AM
---
hw/mc146818rtc.c | 10 +-
1 files changed, 1 insertions(+), 9 deletions(-)
diff --git a/hw/mc146818rtc.c b/hw/mc146818rtc.c
index a46fdfc..9b49cbc 100644
I think the better fixing is to update the cmos before reading the RTC. And in
my patch, it will do it.
best regards
yang
-Original Message-
From: Zhang, Yang Z
Sent: Friday, March 09, 2012 9:54 AM
To: Marcelo Tosatti
Cc: qemu-devel@nongnu.org; Jan Kiszka; k...@vger.kernel.org
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Sent: Friday, March 02, 2012 8:14 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Jan Kiszka; k...@vger.kernel.org;
aligu...@us.ibm.com; Marcelo Tosatti
Subject: Re: [PATCH v3 5/7
Changes in v3:
Rebase to latest head.
Remove the logic to update time format when DM bit changed.
Allow to migrate from old version.
Solve the async when reading UF and UIP
Changes in v2:
Add UIP check logic.
Add logic that next second tick will occur in exactly 500ms later after reset
divider
Change DM(date mode) and 24/12 control bit don't affect the internal
registers. It only indicates what format is using for those registers. So
we don't need to update time format when it is modified.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 10 +-
1 files
There has no need to use two periodic timer to update RTC time.
In this patch, we only update it when guest reading it.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 207 +-
1 files changed, 66 insertions(+), 141
The new logic is compatible with old. So it should not block to migrate
from old version. But new version cannot migrate to old.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 48
1 files changed, 44 insertions(+), 4
The UIP(update in progress) is set when RTC is updating. And the update
cycle begins 244us later after UIP is set. And it is cleared when update end.
.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 18 ++
1 files changed, 18 insertions(+), 0
Add the alarm check when update cycle ended. If alarm is fired,
also AIE bit is setting, then raise a interrupt
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 48 ++--
1 files changed, 46 insertions(+), 2 deletions(-)
diff
Use a timer to emulate update cycle. When update cycle ended and UIE is
setting,
then raise an interrupt. The timer runs only when UF or AF is cleared.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 86 ++
1 files
The first update cycle begins one - half seconds later when divider
reset is removing.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 38 +-
1 files changed, 33 insertions(+), 5 deletions(-)
diff --git a/hw/mc146818rtc.c
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Wednesday, February 22, 2012 7:19 PM
0) My alarm tests failed quite badly. :( I attach a patch for kvm-unit-tests
(repository at git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git).
The tests can be
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Wednesday, February 22, 2012 7:19 PM
0) My alarm tests failed quite badly. :( I attach a patch for kvm-unit-tests
(repository at git://git.kernel.org/pub/scm/virt/kvm/kvm-unit-tests.git).
The tests can be
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Sent: Monday, February 20, 2012 3:38 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; Jan Kiszka; k...@vger.kernel.org;
aligu...@us.ibm.com; Marcelo Tosatti
Subject: Re: [PATCH v2 2/4
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Sent: Monday, February 20, 2012 3:41 PM
On 02/20/2012 01:24 AM, Zhang, Yang Z wrote:
Changes in v2:
Add UIP check logic.
Add logic that next second tick will occur in exactly
Changes in v2:
Add UIP check logic.
Add logic that next second tick will occur in exactly 500ms later after setting
the clock
Current RTC emulation uses periodic timer(2 timers per second) to update RTC
clock. And it will stop CPU staying at deep C-state for long period. Our
experience shows
There has no need to use two periodic timer to update RTC time.
In this patch, we only update it when guest reading it.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 199 +++---
1 files changed, 56 insertions(+), 143
Use timer to emulate alarm. The timer is enabled when AIE is setting
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 187 ++
1 files changed, 187 insertions(+), 0 deletions(-)
diff --git a/hw/mc146818rtc.c
The UIP(update in progress) is set when RTC is updating. We only
consider the normal oscillator(32Khz) mode.
When time base is 32kHz, the update cycle takes 1984us at the end
of every second. And the update cycle begins 244us later after UIP
is set. So the UIP is set in 2228us at end of every
Use timer to emulate RTC update-ended interrupt. The timer is enabled
only when UIE is setting.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
---
hw/mc146818rtc.c | 53 -
1 files changed, 48 insertions(+), 5 deletions(-)
diff --git
-Original Message-
From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
Sent: Thursday, January 12, 2012 6:03 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; a...@redhat.com; aligu...@us.ibm.com; Zhang,
Xiantao; Shan, Haitao; k...@vger.kernel.org
Subject: Re: [PATCH 3/3] stop
-Original Message-
From: Marcelo Tosatti [mailto:mtosa...@redhat.com]
Regarding the UIP bit, a guest could read it in a loop and wait for the value
to
change. But you can emulate it in cmos_ioport_read by reading the host time,
that is, return 1 during 244us, 0 for remaining of
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Because it's not in the spec because some engineer thought it was cool.
It not cool. We need to do some optimizations to get Better Performance.
It's in the spec because it gives you a
-Original Message-
From: Paolo Bonzini [mailto:pbonz...@redhat.com]
Sent: Tuesday, January 10, 2012 5:25 PM
Also, I'm not sure if the update in progress flag still works.
Clients are supposed to wait for UIP=0 before reading the RTC, and an
update is supposed to be at least 220
-Original Message-
From: Andreas Färber [mailto:afaer...@suse.de]
Sent: Saturday, January 07, 2012 1:44 AM
use int64 when compare two time
int32 only represent only 136 years when comparing two times based on
second. It would be better to use int64.
int32 and int64 are
-Original Message-
From: Paolo Bonzini [mailto:paolo.bonz...@gmail.com] On Behalf Of Paolo
Bonzini
Sent: Monday, January 09, 2012 4:19 PM
To: Zhang, Yang Z
Cc: qemu-devel@nongnu.org; a...@redhat.com; aligu...@us.ibm.com; Zhang,
Xiantao; Shan, Haitao; k...@vger.kernel.org
Subject
-Original Message-
From: Jan Kiszka [mailto:jan.kis...@web.de]
Sent: Saturday, January 07, 2012 1:27 AM
However, not having looked at details yet, two things jumped at me:
- You cannot simply change the vmstate format without caring about
migration from older qemu versions.
use int64 when compare two time
int32 only represent only 136 years when comparing two times based on second.
It would be better to use int64.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
diff --git a/qemu-common.h b/qemu-common.h
index b2de015..c14f506 100644
--- a/qemu-common.h
+++
Recently, I did some work for power optimization w/ KVM and I found
there was a periodic timer from qemu which stop the platform from staying deep
C state for a long period. After looking into the qemu code, there was a
periodic RTC update timer which is the culprit. In current RTC
change the RTC update logic to use host time with offset to calculate RTC clock.
There have no need to use two periodic timers to maintain an internal
timer for RTC clock update and alarm check. Instead, we calculate the real RTC
time by the host time with an offset. For alarm and
use gettimeofday() instead of time().
Please refer the patch zero for the description.
Signed-off-by: Yang Zhang yang.z.zh...@intel.com
diff --git a/vl.c b/vl.c
index 01c5a9d..9a51047 100644
--- a/vl.c
+++ b/vl.c
@@ -438,8 +438,11 @@ void qemu_get_timedate(struct tm *tm, int64_t offset)
{
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