u.c | 2 +-
> hw/i386/intel_iommu.c| 2 +-
> hw/i386/kvm/xen_evtchn.c | 2 +-
> hw/i386/pc.c | 8
> hw/i386/pc_piix.c| 6 +++---
> hw/i386/pc_q35.c | 2 +-
> hw/i386/x86-iommu.c | 2 +-
> 9 files changed, 14 insertions(+), 14 del
| 7 +++
> hw/i386/pc_q35.c | 2 +-
> hw/i386/x86.c | 7 +++
> 5 files changed, 9 insertions(+), 11 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/include/hw/i386/x86.h b/include/hw/i386/x86.h
> index 8e306db7bb..4dc30dcb4d 100644
> --- a/incl
cros in atomics.rst.
>
> Signed-off-by: Peter Maydell
> ---
> include/qemu/atomic.h | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
Reviewed-by: Zhao Liu
>
> diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h
> index f1d3d1702a9..99110abefb3 100644
> --- a/
On Fri, Feb 23, 2024 at 02:09:45PM +0100, Paolo Bonzini wrote:
> Date: Fri, 23 Feb 2024 14:09:45 +0100
> From: Paolo Bonzini
> Subject: [PATCH v2 4/7] target/i386: use separate MMU indexes for 32-bit
> accesses
> X-Mailer: git-send-email 2.43.0
>
> Accesses from a 32-bit environment (32-bit
;target/i386: Use atomic operations for pte updates",
> 2022-10-18)
> Co-developed-by: Michael Brown
> Signed-off-by: Michael Brown
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/cpu.h| 6 ++
> target/i386/cpu.c| 2
lper.c | 4 ++--
> 2 files changed, 12 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index dfe43b82042..8c271ca62e5 100644
> --- a/target/i386/cpu.h
> +++ b/target/i386/cpu.h
> @@ -2305,6 +2305,16 @@ uint64_t
perations for pte updates",
> 2022-10-18)
> Signed-off-by: Paolo Bonzini
> ---
> target/i386/tcg/sysemu/excp_helper.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/target/i386/tcg/sysemu/excp_helper.c
> b/target
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
From: Zhao Liu
IOAPICCommonClass implements its own private realize(), and this private
realize() allows error.
Since IOAPICCommonClass.realize() returns void, to check the error,
dereference @errp with ERRP_GUARD().
Signed-off-by: Zhao Liu
---
v2:
* Add the missing ERRP_GUARD(). (Markus
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
From: Zhao Liu
Hi all,
This is my v2 series to clean and fix @errp dereference.
Introduction
The patches 1-6 fix the cases that deference @errp without
ERRP_GUARD(), and they are based on my previsous v1 [1].
The patch 7 is merged in this series from another single patch [2
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
...
* ERRP_GUARD() lifts
-by: Binbin Wu
> Tested-by: Xuelian Guo
> ---
> target/i386/cpu.h| 7 ++-
> target/i386/helper.c | 4
> 2 files changed, 10 insertions(+), 1 deletion(-)
Reviewed-by: Zhao Liu
>
> diff --git a/target/i386/cpu.h b/target/i386/cpu.h
> index 18ea755644..598a3fa
f-by: Binbin Wu
> Tested-by: Xuelian Guo
> Reviewed-by: Xiaoyao Li
> ---
> target/i386/cpu.c | 2 +-
> target/i386/cpu.h | 2 ++
> 2 files changed, 3 insertions(+), 1 deletion(-)
Reviewed-by: Zhao Liu
>
> diff --git a/target/i386/cpu.c b/target/i386/cpu.c
s3adsp1800_mmu.c | 1 +
> hw/mips/cps.c| 1 +
> hw/nios2/10m50_devboard.c| 1 +
> hw/ppc/e500.c| 1 +
> hw/ppc/spapr.c | 1 +
> 7 files changed, 7 insertions(+)
Reviewed-by: Zhao Liu
&
fer QDev API for QDev objects, avoid the underlying QOM layer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/ppc/spapr_cpu_core.c | 3 +--
> 1 file changed, 1 insertion(+), 2 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr
Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/usb.h| 1 -
> hw/usb/bus.c| 9 ++---
> hw/usb/dev-serial.c | 2 +-
> 3 files changed, 3 insertions(+), 9 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/include/hw/usb.h b/include/hw/usb.h
> index
r QDev objects, avoid the underlying QOM layer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> target/mips/cpu.c | 2 +-
> target/xtensa/cpu.c | 2 +-
> 2 files changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/target/mips/cpu.c b/tar
).
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/usb/bus.c | 7 +--
> 1 file changed, 1 insertion(+), 6 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/hw/usb/bus.c b/hw/usb/bus.c
> index 59c39945dd..148224f06a 100644
> --- a/hw/usb/bus.c
> +++ b/hw/usb
r QDev objects, avoid the underlying QOM layer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/arm/musicpal.c | 2 +-
> hw/core/qdev.c| 2 +-
> hw/sparc/sun4m.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git
Hi Philippe,
On Fri, Feb 16, 2024 at 12:03:02PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Fri, 16 Feb 2024 12:03:02 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 11/21] hw/usb: Add QOM parentship relation with hub devices
> X-Mailer: git-send-email 2.41.0
>
> QDev objects created
Hi Philippe,
On Fri, Feb 16, 2024 at 12:03:08PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Fri, 16 Feb 2024 12:03:08 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 17/21] hw/i386/iommu: Prefer object_initialize_child over
> object_initialize
> X-Mailer: git-send-email 2.41.0
>
> When
fer QDev API for QDev objects, avoid the underlying QOM layer.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> hw/i386/pc_sysfw.c | 6 ++
> 1 file changed, 2 insertions(+), 4 deletions(-)
Reviewed-by: Zhao Liu
>
> diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sys
Hi Philippe,
On Fri, Feb 16, 2024 at 12:02:52PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Fri, 16 Feb 2024 12:02:52 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 01/21] hw/i386/pc: Do not use C99 mixed-declarations style
> X-Mailer: git-send-email 2.41.0
>
> QEMU's coding style
On Thu, Feb 22, 2024 at 09:04:14AM +0300, Michael Tokarev wrote:
> Date: Thu, 22 Feb 2024 09:04:14 +0300
> From: Michael Tokarev
> Subject: Re: [PATCH 0/6] [PATCH 0/6] Fix missing ERRP_GUARD() when
> dereference @errp
>
> 21.02.2024 12:43, Zhao Liu wrote:
> > From: Z
On Wed, Feb 21, 2024 at 12:47:33PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:47:33 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 4/6] hw/misc/xlnx-versal-trng: Fix missing ERRP_GUARD()
> in trng_prop_fault_event_set()
>
> Zhao Liu writes:
>
On Wed, Feb 21, 2024 at 12:53:10PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:53:10 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 6/6] hw/vfio/iommufd: Fix missing ERRP_GUARD() in
> iommufd_cdev_getfd()
>
> Zhao Liu writes:
>
> > From: Zhao
On Wed, Feb 21, 2024 at 12:31:06PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:31:06 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 1/6] hw/cxl/cxl-host: Fix missing ERRP_GUARD() in
> cxl_fixed_memory_window_config()
>
> Zhao Liu writes:
>
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
On Wed, Feb 21, 2024 at 01:46:21PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 13:46:21 +0100
> From: Markus Armbruster
> Subject: Re: [RFC 4/8] hw/core: Add cache topology options in -smp
>
> Zhao Liu writes:
>
> > From: Zhao Liu
> >
> > Add
From: Zhao Liu
Hi all,
Thanks to Markus's explanation about ERRP_GUARD() on my previsou
patch [1],
I realize that perhaps more @errp dereference cases need to be
double-checked to ensure that ERRP_GUARD() is being used correctly.
Therefore, there're the patches to add more missing ERRP_GUARD
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
On Wed, Feb 21, 2024 at 12:32:43PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:32:43 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 2/6] hw/display/macfb: Fix missing ERRP_GUARD() in
> macfb_nubus_realize()
>
> Zhao Liu writes:
>
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
On Wed, Feb 21, 2024 at 12:49:46PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:49:46 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 5/6] hw/pci-bridge/cxl_upstream: Fix missing
> ERRP_GUARD() in cxl_usp_realize()
>
> Zhao Liu writes:
>
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
On Wed, Feb 21, 2024 at 01:41:35PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 13:41:35 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU
>
> Zhao Liu writes:
>
> > From: Zhao Liu
> >
> >
On Wed, Feb 21, 2024 at 12:35:47PM +0100, Markus Armbruster wrote:
> Date: Wed, 21 Feb 2024 12:35:47 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH 3/6] hw/mem/cxl_type3: Fix missing ERRP_GUARD() in
> ct3_realize()
>
> Zhao Liu writes:
>
> > From: Zhao
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
From: Zhao Liu
As the comment in qapi/error, dereferencing @errp requires
ERRP_GUARD():
* = Why, when and how to use ERRP_GUARD() =
*
* Without ERRP_GUARD(), use of the @errp parameter is restricted:
* - It must not be dereferenced, because it may be null.
* - It should not be passed
From: Zhao Liu
IOAPICCommonClass implements its own private realize(), and this private
realize() allows error.
Therefore, return directly if IOAPICCommonClass.realize() meets error.
Signed-off-by: Zhao Liu
---
v2: Add the missing ERRP_GUARD(). (Markus)
---
hw/intc/ioapic_common.c | 4
, 2024 at 05:38:24PM +0800, Zhao Liu wrote:
> Date: Mon, 29 Jan 2024 17:38:24 +0800
> From: Zhao Liu
> Subject: Re: [PATCH 0/8] tests/unit/test-smp-parse.c: Add more CPU topology
> test cases
>
> Hi Philippe,
>
> A kindly ping.
>
> Thanks,
> Zhao
>
> On Thu,
From: Zhao Liu
Hi list,
This's our proposal for supporting (SMP) cache topology in -smp as
the following example:
-smp 32,sockets=2,dies=2,modules=2,cores=2,threads=2,maxcpus=32,\
l1d-cache=core,l1i-cache=core,l2-cache=core,l3-cache=die
With the new cache topology options ("l1d-
From: Zhao Liu
Define the cache topology based on CPU topology level for two reasons:
1. In practice, a cache will always be bound to the CPU container
(either private in the CPU container or shared among multiple
containers), and CPU container is often expressed in terms of CPU
From: Zhao Liu
Add "l1d-cache", "l1i-cache". "l2-cache", and "l3-cache" options in
-smp to define the cache topology for SMP system.
Signed-off-by: Zhao Liu
---
hw/core/machine-smp.c | 128 ++
hw/core/machine.c
From: Zhao Liu
User will configure SMP cache topology via -smp.
For this case, update the x86 CPUs' cache topology with user's
configuration in MachineState.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 21 +
1 file changed, 21 insertions(+)
diff --git a/target/i386
From: Zhao Liu
Signed-off-by: Zhao Liu
---
qemu-options.hx | 54 ++---
1 file changed, 47 insertions(+), 7 deletions(-)
diff --git a/qemu-options.hx b/qemu-options.hx
index 70eaf3256685..85c78c99a3b0 100644
--- a/qemu-options.hx
+++ b/qemu
From: Zhao Liu
Signed-off-by: Zhao Liu
---
hw/i386/pc.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw/i386/pc.c b/hw/i386/pc.c
index 25124a077eea..76148c3337cf 100644
--- a/hw/i386/pc.c
+++ b/hw/i386/pc.c
@@ -1848,6 +1848,9 @@ static void pc_machine_class_init(ObjectClass *oc, void
From: Zhao Liu
Use CPUTopology to honor the generic style of CPU capitalization
abbreviations.
Signed-off-by: Zhao Liu
---
hw/s390x/cpu-topology.c | 6 +++---
include/hw/boards.h | 8
include/hw/s390x/cpu-topology.h | 6 +++---
tests/unit/test-smp-parse.c
From: Zhao Liu
Allows cache to be defined at the thread and module level. This
increases flexibility for x86 users to customize their cache topology.
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 10 ++
1 file changed, 6 insertions(+), 4 deletions(-)
diff --git a/target/i386/cpu.c
From: Zhao Liu
Cache topology needs to be defined based on CPU topology levels. Thus,
move CPU topology enumeration into a common header.
To match the general topology naming style, rename CPU_TOPO_LEVEL_SMT
and CPU_TOPO_LEVEL_PACKAGE to CPU_TOPO_LEVEL_THREAD and
CPU_TOPO_LEVEL_SOCKET.
Also
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:11PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:11 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 5/5] hw/i386/q35: Include missing 'hw/acpi/acpi.h' header
> X-Mailer: git-send-email 2.41.0
>
> "hw/acpi/acpi.h" is
.0
>
> We need the VMStateDescription structure definition from
> "migration/vmstate.h" in order to declare vmstate_tco_io_sts.
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/acpi/ich9_tco.h | 1 +
> 1 file changed, 1 insertion(+)
Reviewed-by: Zhao Liu
>
&g
Hi Philippe,
On Mon, Feb 19, 2024 at 03:14:09PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Mon, 19 Feb 2024 15:14:09 +0100
> From: Philippe Mathieu-Daudé
> Subject: [PATCH 3/5] hw/acpi/ich9: Include missing headers
> X-Mailer: git-send-email 2.41.0
>
> The ICH9LPCPMRegs structure has
^
>
> Signed-off-by: Philippe Mathieu-Daudé
> ---
> include/hw/acpi/cpu.h| 1 +
> include/hw/acpi/memory_hotplug.h | 1 +
> 2 files changed, 2 insertions(+)
Reviewed-by: Zhao Liu
>
> diff --git a/include/hw/
Hi Daniel,
On Thu, Feb 08, 2024 at 04:52:33PM +, Daniel P. Berrangé wrote:
> Date: Thu, 8 Feb 2024 16:52:33 +
> From: "Daniel P. Berrangé"
> Subject: Re: [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU
>
> On Fri, Feb 02, 2024 at 12:10:58AM +0800, Zhao
Hi Markus,
On Wed, Feb 07, 2024 at 07:51:52AM +0100, Markus Armbruster wrote:
> Date: Wed, 07 Feb 2024 07:51:52 +0100
> From: Markus Armbruster
> Subject: Re: [PATCH] hw/intc: Handle the error of
> IOAPICCommonClass.realize()
>
> Zhao Liu writes:
>
> > Hi Phili
Ping Philippe & Markus,
Do you have furthur comment on such private realize()? ;-)
Thanks,
Zhao
On Thu, Feb 01, 2024 at 11:25:56AM +0800, Zhao Liu wrote:
> Date: Thu, 1 Feb 2024 11:25:56 +0800
> From: Zhao Liu
> Subject: Re: [PATCH] hw/intc: Handle the error of
> IOAPICCom
On Sat, Feb 03, 2024 at 05:30:48PM +0800, Zhao Liu wrote:
> Date: Sat, 3 Feb 2024 17:30:48 +0800
> From: Zhao Liu
> Subject: [RFC 0/6] Intel Thread Director Virtualization Support in QEMU
> X-Mailer: git-send-email 2.34.1
>
> From: Zhao Liu
>
> Hi list,
>
From: Zhao Liu
Hi list,
This is our refreshed RFC to support our ITD virtualization patch
series [1] in KVM, and bases on bd2e12310b18 ("Merge tag
'qga-pull-2024-01-30' of https://github.com/kostyanf14/qemu into
staging").
ITD is Intel's client specific feature to optimize schedulin
THREAD DIRECTOR
Tested-by: Yanting Jiang
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 49 ++-
target/i386/cpu.h | 8 ++-
target/i386/kvm/kvm.c | 21 +++
3 files
support since it's
emulated in KVM. This MSR is used to control the enabling of ITD's
history reset.
[1]: SDM, vol. 3B, section 15.6.11 Logical Processor Scope History
Tested-by: Yanting Jiang
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
Signed-off-by: Zhao Liu
---
target/i386
From: Zhao Liu
Intel Thread Director (ITD) is the extension of HFI, and it extends
the HFI to provide performance and energy efficiency data for advanced
classes of instructions [1].
>From Alder Lake, Intel's client products support ITD, and this feature
can be used in VM to optimize schedul
scenario.
Additionally, add save/load support for 2 PTS related MSRs.
Tested-by: Yanting Jiang
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
Signed-off-by: Zhao Liu
---
target/i386/cpu.c | 22 +-
target/i386/cpu.h | 13 +
target/i386/kvm
From: Zhao Liu
The property enable-itd will be used to set ITD related feature bits
for Guest, which includes PTS, HFI, ITD and HRESET.
Now PTS, HFI, ITD and HRESET are marked as no_autoenable_flags, since
PTS, HFI and ITD have additional restrictions on CPU topology, and
HRESET is only used
SDM, vol. 3B, section 15.8.4.1, Detection of Software Controlled
Clock Modulation Extension.
Tested-by: Yanting Jiang
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
---
target/i386/cpu.h | 9 +
target/i386/kvm/kvm.c | 25 +
Hi Daniel,
On Thu, Feb 01, 2024 at 09:21:48AM +, Daniel P. Berrangé wrote:
> Date: Thu, 1 Feb 2024 09:21:48 +
> From: "Daniel P. Berrangé"
> Subject: Re: [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU
>
> On Thu, Feb 01, 2024 at 10:57:32AM +0800, Zhao
From: Zhao Liu
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu
---
hw/arm/smmuv3.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c
index 68eeef3e1d4c..b3d8642a4990 100644
--- a/hw/arm
From: Zhao Liu
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu
---
hw/isa/vt82c686.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c
index d3e0f6d01fb6..a99eae4f6333 100644
--- a/hw
From: Zhao Liu
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu
---
hw/intc/s390_flic_kvm.c | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c
index 4d5cbb2a2fb6
From: Zhao Liu
Hi list,
Now we already have the device_class_set_parent_realize() to set
parent realize(), thus clean up the places where that helper was
forgotten.
Regards,
Zhao
---
Zhao Liu (4):
hw/isa/vt82c686: Consolidate the use of
device_class_set_parent_realize()
hw/isa/pc87312
From: Zhao Liu
Use device_class_set_parent_realize() to set parent realize() directly.
Signed-off-by: Zhao Liu
---
hw/isa/pc87312.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c
index ee23f3e164df..64dd17b537f2 100644
--- a/hw/isa
Hi Markus,
On Wed, Jan 31, 2024 at 09:14:21PM +0100, Markus Armbruster wrote:
> Date: Wed, 31 Jan 2024 21:14:21 +0100
> From: Markus Armbruster
> Subject: Dynamic & heterogeneous machines, initial configuration: problems
>
> This memo is the fruit of discussions with Philippe Mathieu-Daudé.
>
Hi Philippe,
On Wed, Jan 31, 2024 at 05:48:24PM +0100, Philippe Mathieu-Daudé wrote:
> Date: Wed, 31 Jan 2024 17:48:24 +0100
> From: Philippe Mathieu-Daudé
> Subject: Re: [PATCH] hw/intc: Handle the error of
> IOAPICCommonClass.realize()
>
> Hi Zhao,
>
> On 31/1/
Hi Daniel,
On Wed, Jan 31, 2024 at 10:28:42AM +, Daniel P. Berrangé wrote:
> Date: Wed, 31 Jan 2024 10:28:42 +
> From: "Daniel P. Berrangé"
> Subject: Re: [PATCH v8 00/21] Introduce smp.modules for x86 in QEMU
>
> On Wed, Jan 31, 2024 at 06:13:29PM +0800, Zhao
From: Zhao Liu
IOAPICCommonClass implements its own private realize(), and this private
realize() allows error.
Therefore, return directly if IOAPICCommonClass.realize() meets error.
Signed-off-by: Zhao Liu
---
hw/intc/ioapic_common.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/hw
From: Zhao Liu
Currently, by default, the cache topology is encoded as:
1. i/d cache is shared in one core.
2. L2 cache is shared in one core.
3. L3 cache is shared in one die.
This default general setting has caused a misunderstanding, that is, the
cache topology is completely equated
From: Zhao Liu
Linux kernel (from v6.4, with commit edc0a2b595765 ("x86/topology: Fix
erroneous smp_num_siblings on Intel Hybrid platforms") is able to
handle platforms with Module level enumerated via CPUID.1F.
Expose the module level in CPUID[0x1F] if the machine has more than
From: Zhao Liu
CPUID[0x801D].EAX[bits 25:14] NumSharingCache: number of logical
processors sharing cache.
The number of logical processors sharing this cache is
NumSharingCache + 1.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology
From: Zhao Liu
Introduce module-id to be consistent with the module-id field in
CpuInstanceProperties.
Following the legacy smp check rules, also add the module_id validity
into x86_cpu_pre_plug().
Tested-by: Yongwei Ma
Co-developed-by: Zhuocheng Ding
Signed-off-by: Zhuocheng Ding
Signed
From: Zhuocheng Ding
After i386 supports module level, it's time to add the test for module
level's parsing.
Signed-off-by: Zhuocheng Ding
Co-developed-by: Zhao Liu
Signed-off-by: Zhao Liu
Reviewed-by: Yanan Wang
Tested-by: Babu Moger
Tested-by: Yongwei Ma
Acked-by: Michael S. Tsirkin
From: Zhao Liu
For i-cache and d-cache, current QEMU hardcodes the maximum IDs for CPUs
sharing cache (CPUID.04H.00H:EAX[bits 25:14] and CPUID.04H.01H:EAX[bits
25:14]) to 0, and this means i-cache and d-cache are shared in the SMT
level.
This is correct if there's single thread per core
From: Zhao Liu
The commit 8f4202fb1080 ("i386: Populate AMD Processor Cache Information
for cpuid 0x801D") adds the cache topology for AMD CPU by encoding
the number of sharing threads directly.
>From AMD's APM, NumSharingCache (CPUID[0x801D].EAX[bits 25:14])
means [1]
From: Zhao Liu
Refer to the fixes of cache_info_passthrough ([1], [2]) and SDM, the
CPUID.04H:EAX[bits 25:14] and CPUID.04H:EAX[bits 31:26] should use the
nearest power-of-2 integer.
The nearest power-of-2 integer can be calculated by pow2ceil() or by
using APIC ID offset/width (like L3
From: Zhao Liu
Add "modules" parameter parsing support in -smp.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
---
Changes since v7:
* New commit to introduce module level in -smp.
---
hw/core/machine-smp.c | 39 +-
From: Zhao Liu
Support module level in i386 cpu topology structure "X86CPUTopoInfo".
Since x86 does not yet support the "modules" parameter in "-smp",
X86CPUTopoInfo.modules_per_die is currently always 1.
Therefore, the module level width in AP
From: Zhao Liu
CPUID[4].EAX[bits 25:14] is used to represent the cache topology for
Intel CPUs.
After cache models have topology information, we can use
CPUCacheInfo.share_level to decide which topology level to be encoded
into CPUID[4].EAX[bits 25:14].
And since with the helper
From: Zhao Liu
Add module_id member in X86CPUTopoIDs.
module_id can be parsed from APIC ID, so also update APIC ID parsing
rule to support module level. With this support, the conversions with
module level between X86CPUTopoIDs, X86CPUTopoInfo and APIC ID are
completed.
module_id can be also
From: Zhao Liu
At present, the subleaf 0x02 of CPUID[0x1F] is bound to the "die" level.
In fact, the specific topology level exposed in 0x1F depends on the
platform's support for extension levels (module, tile and die).
To help expose "module" level in 0x1F, decouple
From: Zhao Liu
Intel CPUs implement module level on hybrid client products (e.g.,
ADL-N, MTL, etc) and E-core server products.
A module contains a set of cores that share certain resources (in
current products, the resource usually includes L2 cache, as well as
module scoped features and MSRs
From: Zhao Liu
As module-level topology support is added to X86CPU, now we can enable
the support for the modules parameter on PC machines. With this support,
we can define a 5-level x86 CPU topology with "-smp":
-smp cpus=*,maxcpus=*,sockets=*,dies=*,modules=*,cores=*,threads=*.
Ad
From: Zhao Liu
Currently, QEMU checks the specify number of topology domains to detect
if there's extended topology levels (e.g., checking nr_dies).
With this bitmap, the extended CPU topology (the levels other than SMT,
core and package) could be easier to detect without touching the
topology
From: Zhao Liu
In cpu_x86_cpuid(), there are many variables in representing the cpu
topology, e.g., topo_info, cs->nr_cores and cs->nr_threads.
Since the names of cs->nr_cores/cs->nr_threads does not accurately
represent its meaning, the use of cs->nr_cores/cs->nr_threads is
From: Zhao Liu
Add module-id in CpuInstanceProperties, to locate the CPU with module
level.
Suggested-by: Xiaoyao Li
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
---
Changes since v7:
* New commit to introduce module_id to locate the CPU with module
level.
---
hw/core/machine-hmp
From: Zhao Liu
Hi list,
This is the our v8 patch series, rebased on the master branch at the
commit 11be70677c70 ("Merge tag 'pull-vfio-20240129' of
https://github.com/legoater/qemu into staging").
Compared with v7 [1], v8 mainly has the following changes:
* Introduced smp.modul
From: Zhao Liu
CPUID[0xB] defines SMT, Core and Invalid types, and this leaf is shared
by Intel and AMD CPUs.
But for extended topology levels, Intel CPU (in CPUID[0x1F]) and AMD CPU
(in CPUID[0x8026]) have the different definitions with different
enumeration values.
Though CPUID
From: Zhao Liu
Module is a level above the core, thereby supporting numa
configuration on the module level can bring user more numa flexibility.
This is the natural further support for module level.
Add module level support in numa configuration.
Tested-by: Yongwei Ma
Signed-off-by: Zhao Liu
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