Hi Marcel,
Marcel Apfelbaum 于2018年9月20日周四 下午2:39写道:
>
> Hi Zihan,
>
> On 09/18/2018 04:41 PM, Michael S. Tsirkin wrote:
> > Cc Laine, Eric for an opinion about the management interface.
> >
> > On Mon, Sep 17, 2018 at 10:57:31PM +0800, Zihan Yang wrote:
> >
Marcel Apfelbaum 于2018年9月20日周四 下午2:41写道:
>
> Hi Zihan, Gerd
>
> On 09/20/2018 09:09 AM, Gerd Hoffmann wrote:
> As for the management, will some checks when adding mcfg be enough for
> management? Or I can maintain a variable to indicate how many space
> have been consumed and warn t
Gerd Hoffmann 于2018年9月19日周三 下午12:26写道:
>
> > > > 2. Only 4x devices is supported, you need to be careful not to overuse
> > >
> > > Could you elaborate on this please? What happens if you are not careful?
> > > How does management know what the limits are?
> >
> > It means the user might use more
Michael S. Tsirkin 于2018年9月18日周二 下午9:41写道:
>
> Cc Laine, Eric for an opinion about the management interface.
>
> On Mon, Sep 17, 2018 at 10:57:31PM +0800, Zihan Yang wrote:
> > Hi all
> >
> > Here is a minimal working version of supporting multiple pci domains.
>
Gerd Hoffmann 于2018年9月18日周二 下午1:09写道:
>
> Hi,
>
> > +static void pxb_pcie_host_get_mmcfg_base(Object *obj, Visitor *v, const
> > char *name,
>
> > +void *opaque, Error **errp)
> > +{
> > +PCIExpressHost *e = PCI
This allows SeaBIOS to configure MCFG base during initialization.
The mcfg size is calculated using based on desired bus number
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 37 +
include/hw/pci-bridge/pci_expander_bridge.h | 7
Describe new pci segments of host bridges in AML as new pci devices,
with _SEG and _BBN to let them be in DSDT.
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 53 +---
1 file changed, 30 insertions(+), 23 deletions(-)
diff --git a/hw/i386
bus number of pxb-pcie device on pcie.0 bus
v2 <- v1:
- Allow user to configure whether to put pxb-pcie into seperate domain
- Add AML description part of each host bridge
- Modify the location of MCFG space to between RAM hotplug and pci hole64
Many thanks to
Please let me know if you have any
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
add a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 86 +++--
1 file changed, 82 insertions(+), 4 deletions
may only want a sub-range of busses(e.g. [3,9]),
this is when max_bus becomes useful. By reducing the memory each
domain consumes, we can support more domains in a limited space.
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 23 +--
1 file changed, 21 insert
pxb-pcie may only consumes a subset of 256 busses in a pci domain, but seabios
does not know it unless pxb-pcies passes it to seabios. This patch places
desired mcfg size into a hidden pci bar. The size is calculated based on
desired bus number of a pxb-pcie
Signed-off-by: Zihan Yang
---
hw/pci
in pci
domain 0 under q35 host
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 109 +---
hw/pci-bridge/pci_expander_bridge.c | 51 +
hw/pci/pci.c| 30 +++-
include/hw/pci-bridge
Gerd Hoffmann 于2018年8月27日周一 上午7:04写道:
>
> Hi,
>
> > > However, QEMU only binds port 0xcf8 and 0xcfc to
> > > bus pcie.0. To avoid bus confliction, we should use other port pairs for
> > > busses under new domains.
> >
> > I would skip support for IO based configuration and use only MMCONFIG
>
Marcel Apfelbaum 于2018年8月25日周六 下午8:08写道:
>
> Hi Zihan,
>
> On 08/19/2018 04:51 AM, Zihan Yang wrote:
> > Hi Marcel,
> >
> > Marcel Apfelbaum 于2018年8月18日周六 上午1:14写道:
> >> Hi Zihan,
> >>
> >> On 08/09/2018 09:33 AM, Zihan Yang
Marcel Apfelbaum 于2018年8月25日周六 下午7:58写道:
>
>
>
> On 08/19/2018 05:00 AM, Zihan Yang wrote:
> > Marcel Apfelbaum 于2018年8月18日周六 上午1:49写道:
> >>
> >>
> >> On 08/09/2018 09:34 AM, Zihan Yang wrote:
> >>> Describe new pci segments of host bridg
Marcel Apfelbaum 于2018年8月18日周六 上午1:54写道:
>
>
>
> On 08/09/2018 09:35 AM, Zihan Yang wrote:
> > The bus_nr indicates the bus number of pxb-pcie under pcie.0, but since pxb
> > host can be put into different pci domain, the start bus should always be 0
>
> I am not
Marcel Apfelbaum 于2018年8月18日周六 上午1:52写道:
>
>
>
> On 08/09/2018 09:35 AM, Zihan Yang wrote:
> > This enables seabios to read config file in pxb host bus other than sysbus
> >
> > Signed-off-by: Zihan Yang
> > ---
> > hw/pci-bridge/pci_expander_bridge.c
Marcel Apfelbaum 于2018年8月18日周六 上午1:49写道:
>
>
>
> On 08/09/2018 09:34 AM, Zihan Yang wrote:
> > Describe new pci segments of host bridges in AML as new pci devices,
> > with _SEG and _BBN to let them be in DSDT.
> >
> > Besides, bus_nr indicates the bus number o
Marcel Apfelbaum 于2018年8月18日周六 上午1:41写道:
>
> Hi Zihan,
>
> On 08/09/2018 09:33 AM, Zihan Yang wrote:
> > Allocate new segment for pxb-pcie host bridges in MCFG table, and reserve
> > corresponding MCFG space for them. This allows user-defined pxb-pcie
> > host bri
Hi Marcel,
Marcel Apfelbaum 于2018年8月18日周六 上午1:14写道:
>
> Hi Zihan,
>
> On 08/09/2018 09:33 AM, Zihan Yang wrote:
> > The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
> > change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PC
HI all,
Sorry about unthreaded messages, I forgot to add the in-reply-to field in
the email. Future
patches will be threaded, but as for this patch, you can refer to the
following links
[RFC 1/6]
http://lists.nongnu.org/archive/html/qemu-devel/2018-08/msg01364.html
[RFC 2/6]
http://lists.nongnu.or
Eric Blake 于2018年8月9日周四 下午9:23写道:
>
> On 08/09/2018 01:33 AM, Zihan Yang wrote:
> > The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
> > change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
>
> meta-comment:
>
> Your me
first element when traversing the list, because q35 host is
inserted beofre pxb-pcie hosts
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 116 +++-
hw/i386/pc.c| 14 +++-
hw/pci-bridge/pci_expander_bridge.c
This allows SeaBIOS to retrieve MCFG base and size when it initializes
pxb host bridges.
A backlink to PXBPCIEHost is added in PXBDev to achieve above goal
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 55 +
include/hw/pci-bridge
The bus_nr indicates the bus number of pxb-pcie under pcie.0, but since pxb
host can be put into different pci domain, the start bus should always be 0
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 14 ++
hw/pci-bridge/pci_expander_bridge.c | 10 +-
2
This enables seabios to read config file in pxb host bus other than sysbus
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 15 +++
include/hw/pci-bridge/pci_expander_bridge.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/hw/pci-bridge
Describe new pci segments of host bridges in AML as new pci devices,
with _SEG and _BBN to let them be in DSDT.
Besides, bus_nr indicates the bus number of pxb-pcie under pcie.0 bus,
but since we put it into separate domain, it should be zero, which is
equal to BBN.
Signed-off-by: Zihan Yang
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 127 ++--
1 file changed, 122 insertions(+), 5
eperate domain
- Add AML description part of each host bridge
- Modify the location of MCFG space to between RAM hotplug and pci hole64
Zihan Yang (6):
pci_expander_bridge: add type TYPE_PXB_PCIE_HOST
acpi-build: allocate mcfg for pxb-pcie host bridges
i386/acpi-build: descri
Glad to see such a quick fix, and ASAN looks like a great tool :)
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bugs.launchpad.net/bugs/1785670
Title:
Guest(ubuntu 18.04) crashes when trying uploading file
Status in QEMU
Marcel Apfelbaum 于2018年8月6日周一 下午7:46写道:
>
>
>
> On 08/02/2018 05:45 AM, Zihan Yang wrote:
> > The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
> > change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
>
> After an offl
It's indeed e1000e specific, when I change e1000e to e1000, I can upload
file freely. Looks like there is an overflow somewhere in e1000e that
corrupted the heap chunk header.
--
You received this bug notification because you are a member of qemu-
devel-ml, which is subscribed to QEMU.
https://bu
Public bug reported:
I speficy slirp network, and I can open websites, git clone repos. But
when I try to upload a file to slack, or try to do a git push, it
crashes.
My host is ubuntu 16.04 with kernel 4.15.0-29-generic, and qemu is
latest source in git(commit 1fb57da72ae0886e). The command I us
The former bus_nr property indicates the bus number of pxb-pcie device on
pcie.0 bus, not the Base Bus Number of pxb-pcie host bridge. Use start_bus
property to represent this BBN when building acpi table
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 22
This allows SeaBIOS to retrieve MCFG base and size when it initializes
pxb host bridges.
A backlink to PXBPCIEHost is added in PXBDev to achieve above goal
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 55 +
include/hw/pci-bridge
first element when traversing the list, because q35 host is
inserted beofre pxb-pcie hosts
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 115 +++-
hw/i386/pc.c| 14 +++-
hw/pci-bridge/pci_expander_bridge.c
pxb-pcie device on pcie.0 bus
v2 <- v1:
- Allow user to configure whether to put pxb-pcie into seperate domain
- Add AML description part of each host bridge
- Modify the location of MCFG space to between RAM hotplug and pci hole64
Zihan Yang (6):
pci_expander_bridge: add type TYPE_
This enables seabios to read config file in pxb host bus other than sysbus
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 15 +++
include/hw/pci-bridge/pci_expander_bridge.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/hw/pci-bridge
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 127 ++--
1 file changed, 122 insertions(+), 5
The former bus_nr property indicates the bus number of pxb-pcie device on
pcie.0 bus, not the Base Bus Number of pxb-pcie host bridge. Use start_bus
property to represent this BBN when building acpi table
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 22
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
change it to a new type TYPE_PXB_PCIE_HOST to better utilize ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 127 ++--
1 file changed, 122 insertions(+), 5
This enables seabios to read config file in pxb host bus other than sysbus
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 15 +++
include/hw/pci-bridge/pci_expander_bridge.h | 3 +++
2 files changed, 18 insertions(+)
diff --git a/hw/pci-bridge
This allows SeaBIOS to retrieve MCFG base and size when it initializes
pxb host bridges.
A backlink to PXBPCIEHost is added in PXBDev to achieve above goal
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 55 +
include/hw/pci-bridge
Describe new pci segments of host bridges in AML as new pci devices,
with _SEG and _BBN to let them be in DSDT
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 78 +++-
1 file changed, 53 insertions(+), 25 deletions(-)
diff --git a/hw/i386
Describe new pci segments of host bridges in AML as new pci devices,
with _SEG and _BBN to let them be in DSDT
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 78 +++-
1 file changed, 53 insertions(+), 25 deletions(-)
diff --git a/hw/i386
<- v1:
- Allow user to configure whether to put pxb-pcie into seperate domain
- Add AML description part of each host bridge
- Modify the location of MCFG space to between RAM hotplug and pci hole64
Zihan Yang (6):
pci_expander_bridge: add type TYPE_PXB_PCIE_HOST
acpi-build: allocate mcfg
first element when traversing the list, because q35 host is
inserted beofre pxb-pcie hosts
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c| 115 +++-
hw/i386/pc.c| 14 +++-
hw/pci-bridge/pci_expander_bridge.c
Marcel Apfelbaum 于2018年6月20日周三 下午3:46写道:
>
>
>
> On 06/12/2018 12:13 PM, Zihan Yang wrote:
> > Describe new pci segments of host bridges in AML. The host bridge list is
> > replaced by QTAILQ to let q35 host be processed first in every traverse
> >
> > Signed-
Thanks for your review.
Marcel Apfelbaum 于2018年6月20日周三 下午3:41写道:
>
>
>
> On 06/12/2018 12:13 PM, Zihan Yang wrote:
> > Allocate new segment for pxb-pcie host bridges in MCFG table, and reserve
> > corresponding MCFG space for them. This allows user-defined pxb-pcie
>
Marcel Apfelbaum 于2018年6月20日周三 下午2:38写道:
>
>
>
> On 06/12/2018 12:13 PM, Zihan Yang wrote:
> > The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
> > add a new type TYPE_PXB_PCIE_HOST to better utilize the ECAM of PCIe
> >
> > Signed-
Michael S. Tsirkin 于2018年6月13日周三 下午10:46写道:
>
> On Wed, Jun 13, 2018 at 04:23:40PM +0800, Zihan Yang wrote:
> > Michael S. Tsirkin 于2018年6月12日周二 下午9:43写道:
> > >
> > > On Tue, Jun 12, 2018 at 05:13:22PM +0800, Zihan Yang wrote:
> > > > Th
Michael S. Tsirkin 于2018年6月12日周二 下午9:43写道:
>
> On Tue, Jun 12, 2018 at 05:13:22PM +0800, Zihan Yang wrote:
> > The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
> > add a new type TYPE_PXB_PCIE_HOST to better utilize the ECAM of PCIe
> >
>
Describe new pci segments of host bridges in AML. The host bridge list is
replaced by QTAILQ to let q35 host be processed first in every traverse
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 69 ++-
hw/pci/pci.c | 9
The inner host bridge created by pxb-pcie is TYPE_PXB_PCI_HOST by default,
add a new type TYPE_PXB_PCIE_HOST to better utilize the ECAM of PCIe
Signed-off-by: Zihan Yang
---
hw/pci-bridge/pci_expander_bridge.c | 118 ++--
1 file changed, 114 insertions(+), 4
n RAM hotplug and pci hole64
Zihan Yang (3):
pci_expander_bridge: add type TYPE_PXB_PCIE_HOST
acpi-build: allocate mcfg for pxb-pcie host bridges
acpi-build: describe new pci domain in AML
hw/i386/acpi-build.c| 162
in Dell EMC.
>>
>> From https://www.outreachy.org. we find that you are working on the
>> Multiple PCI domain feature which we think may be very helpful to our
>> current work.
>>
>
> We are glad you are considering using the project.
> The project got de
2018-05-24 1:33 GMT+08:00 Marcel Apfelbaum :
>
>> * IOMMUs cannot span domains either, so bringing new domains introduces
>> the need
>> to add a VT-d DHRD or vIOMMU per PCIe domain
>
>
> Not really, you may have PCI domains not associated to an vIOMMU. As a first
> step,
> you should not deal wi
> > The original purpose was just to support multiple segments in Intel
> > Q35 archtecure for PCIe topology, which makes bus number a less scarce
> > resource. The patches are very primitive and many things are left for
> > firmware to finish(the initial plan was to implement it in SeaBIOS),
> > t
Hi all,
Thanks for all your comments and suggestions, I wasn't expecting so many
professional
reviewers. Some of the things you mentioned are beyond my knowledge right
now.
Please correct me if I'm wrong below.
The original purpose was just to support multiple segments in Intel Q35
archtecure
for
> Maybe we should add a parameter to the pxb-pci device specifying the PCI
domain
> instead of adding it on the fly. It will help ensuring the PCI domain
will not change over
> time due to code changes.In this case "bus sharing" should be off. For
the moment
> the pxb devices get the bus range from
> An interesting point is if we want to limit the MMFCG size for PXBs, as
we may not be
> interested to use all the buses in a specific domain.
OK, perhaps providing an option for the user to specify the desired bus
numbers?
> For each bus we require some address space that remains unused.
Does
> have no objection here, we'll see later how the modification helps.
The purpose is to place the q35 host at the start of queue. In the original
QLIST,
when a new pxb host is added, q35 host will be bumped to the end end list.
By replacing it with QTAILQ, we can always get q35 host bridges firs
Hi Marcel,
Thanks a lot for your feedback.
> I don't think we should try to place the MMCFGs before 4G even if there
> is enough room. Is better to place them always after 4G.
>
> "above_4g_mem" PCI hole it is reserved for PCI devices hotplug. We cannot
use if for
> MMCFGs. What I think we can do
Currently only q35 host bridge us allocated space in MCFG table. To put pxb host
into sepratate pci domain, each of them should have its own configuration space
int MCFG table
Signed-off-by: Zihan Yang
---
hw/i386/acpi-build.c | 83 +++-
1 file
before, that all pci expander bridges stay in the
same pci domain as a35 host.
Zihan Yang (3):
pci_expander_bridge: reserve enough mcfg space for pxb host
pci: Link pci_host_bridges with QTAILQ
acpi-build: allocate mcfg for multiple host bridges
hw/i386/acpi-build.c
QLIST will place the original q35 host bridge at the end of list because it is
added first. Replace it with QTAILQ to make q35 at the first of queue, which
makes it convinient and compatible when there are pxb hosts other than q35 hosts
Signed-off-by: Zihan Yang
---
hw/pci/pci.c
enough memory
to reserve for them
Signed-off-by: Zihan Yang
---
hw/i386/pc.c| 5 ++
hw/pci-bridge/pci_expander_bridge.c | 96 -
include/hw/pci-bridge/pci_expander_bridge.h | 7 +++
3 files changed, 107 insertions(+), 1 deletion
During smram region initialization some addresses are hardcoded,
replace them with macro to be more clear to readers.
Previous patch forgets about one value and exceeds the line
limit of 90 characters. The v2 breaks a few long lines
Signed-off-by: Zihan Yang
---
hw/pci-host/q35.c | 17
Currently part of mch_realize uses hardcoded value when initializing
smram regions. Use macro to be more clear to code readers
Signed-off-by: Zihan Yang
---
hw/pci-host/q35.c | 12 ++--
1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c
specific
header at last, although I'm not sure whether we will really need more
macros in the future.
P.S. I forgot to cc to qemu-devel, so I resend one. I apologize if two
identical
emails look confusing to you.
2018-03-08 4:27 GMT+08:00 Philippe Mathieu-Daudé :
> Hi Zihan Yang,
>
>
Hi all, this is a bitesized patch from me a while ago, it seems a little
old but I wonder if there is any opinion about it? Is it still valid?
Thanks.
2018-02-04 15:28 GMT+08:00 Zihan Yang :
> The ps2_mouse property of vmmouse is still pointer type which
> is defined by DEFINE_PROP_PT
e point now.
2018-02-14 18:13 GMT+08:00 Paolo Bonzini :
> On 14/02/2018 09:49, Zihan Yang wrote:
> > change the mutex member in RAMList structure from QemuMutex to
> CompatGMutex.
> > qemu_mutex_init() is just deleted instead of being replaced with
> g_mutex_init()
> > becau
change the mutex member in RAMList structure from QemuMutex to CompatGMutex.
qemu_mutex_init() is just deleted instead of being replaced with g_mutex_init()
because there is no need to do initialize a mutex that is statically allocated.
Signed-off-by: Zihan Yang
---
exec.c | 5
The ps2_mouse property of vmmouse is still pointer type which
is defined by DEFINE_PROP_PTR. But qdev pointer property should
be avoided. Convert it into QOM link relationship
Signed-off-by: Zihan Yang
---
hw/i386/pc.c | 2 +-
hw/i386/vmmouse.c | 19 ---
2 files changed
This allows the macro to be used elsewhere, for example,
when adding link property to vmmouse object.
Signed-off-by: Zihan Yang
---
hw/input/pckbd.c | 2 +-
hw/input/pckbd.h | 6 ++
2 files changed, 7 insertions(+), 1 deletion(-)
create mode 100644 hw/input/pckbd.h
diff --git a/hw/input
another file. The first patch put
this macro into a single header file so that the macro can
be used elsewhere. The second patch does the actual work.
Zihan Yang (2):
hw/input/pckdb: put TYPE_I8042 into a single header file
vmmouse: change qdev pointer property to qom link
hw/i386/pc.c | 2
net_socket_listen_init directly uses parse_host_port, bind and listen,
change it to use functions in include/qemu/sockets.h
Signed-off-by: Zihan Yang
---
net/socket.c | 30 +-
1 file changed, 9 insertions(+), 21 deletions(-)
diff --git a/net/socket.c b/net/socket.c
Hi, Daniel
>You've added all this extra functionality to pass arbitrary
>options, but then not used it in any of the later patches.
>We've been trying to remove complexity from this code, so
>I'm not in favour of adding new functionality that is not
>even used.
You are right, unused functionality
NULL pointer.
Note the caller who wants a non-blocking socket should always
check the errno after socket_connect returns to see if the
connection is really established or still inprogress.
Signed-off-by: Zihan Yang
---
block/sheepdog.c | 2 +-
block/ssh.c| 2 +-
include
Some functions in net/socket.c still uses bind/connect/listen
directly. Change it to use functions in include/qemu/sockets.h
Signed-off-by: Zihan Yang
---
net/socket.c | 41 +
1 file changed, 21 insertions(+), 20 deletions(-)
diff --git a/net/socket.c b
providing a NULL pointer.
Signed-off-by: Zihan Yang
---
include/qemu/sockets.h | 17 +++-
io/channel-socket.c| 2 +-
qga/channel-posix.c| 2 +-
util/qemu-sockets.c| 74 ++
4 files changed, 81 insertions(+), 14 deletions
using a non-blocking socket. It does not have to in other cases.
Zihan Yang (4):
qemu-socket: Allow custom socket option in socket_listen
qemu-socket: Allow custom socket options in socket_connect
net/socket: change net_socket_listen_init to use functions in
include/qemu/sockets.h
net
net_socket_connect_init still uses parse_host_port() and connect()
directly. Convert it into functions in include/qemu/sockets.h
Signed-off-by: Zihan Yang
---
net/socket.c | 52 +++-
1 file changed, 23 insertions(+), 29 deletions(-)
diff --git a
Currently the virtio_ccw_device_class_init function sets dc->exit, which is
the exit callback of DeviceClass. It should be converted to dc->unrealize
since exit callback of DeviceClass will be removed in the future.
Signed-off-by: Zihan Yang
---
hw/s390x/virtio-ccw.c | 5 ++---
1 file c
Only virtio_ccw_exit and the exit callback in VirtIOCCWDeviceClass are
converted to void in this patch. 'virtio_ccw_busdev_exit' belongs to
DeviceClass so it still returns int, DeviceClass::exit will return
void in future patches.
Signed-off-by: Zihan Yang
---
hw/s390x/virtio
Currently the console_exit function in sclpconsole-lm.c and sclpconsole.c
does nothing, so remove them and convert the callback in SCLPEventClass to
void. Since there is a NULL check on the DeviceClass exit callback, it
should be ok to simply remove them.
Signed-off-by: Zihan Yang
---
hw/char
class init function of virtio-ccw, because the exit
callback of DeviceClass will be removed in the future.
Zihan Yang (3):
hw/char/sclp*: remove console_exit function in sclp
hw/s390x: make virtio_ccw_exit function in virtio-ccw return void
hw/s390: replace exit with unrealize during class
OK, sorry for the confusion, I will give a new patch series. I'm not very
familiar with
the conventions so I wonder if someone could help clarify some principles
for me.
I'd like to replace all the init/exit callback of DeviceClass to
realize/unrealize, and
convert return type of exit callback of
Only virtio_ccw_exit and the callback in VirtIOCCWDeviceClass are
converted to void in this patch. 'virtio_ccw_busdev_exit' belongs to
DeviceClass so it still returns int at present, DeviceClass::exit
will return void in another patch.
Signed-off-by: Zihan Yang
---
hw/s390x/virtio
The exit callback of DeviceClass will be removed in the future, so
convert to unrealize in the init functioin
Signed-off-by: Zihan Yang
---
hw/audio/intel-hda.c | 5 ++---
1 file changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c
index 537face
Currently the virtio_ccw_device_class_init function sets dc->exit, the
exit callback of DeviceClass. It should be converted to dc->unrealize
since exit callback of DeviceClass will be removed in the future.
Signed-off-by: Zihan Yang
---
hw/s390x/virtio-ccw.c | 5 ++---
1 file chan
The exit callback always return 0, convert it to void
Signed-off-by: Zihan Yang
---
hw/audio/hda-codec.c | 3 +--
hw/audio/intel-hda.h | 2 +-
2 files changed, 2 insertions(+), 3 deletions(-)
diff --git a/hw/audio/hda-codec.c b/hw/audio/hda-codec.c
index 52d4640..5402cd1 100644
--- a/hw/audio
: Zihan Yang
---
hw/char/sclpconsole-lm.c | 6 --
hw/char/sclpconsole.c | 6 --
hw/s390x/event-facility.c | 6 +-
include/hw/s390x/event-facility.h | 2 +-
4 files changed, 2 insertions(+), 18 deletions(-)
diff --git a/hw/char/sclpconsole-lm.c b/hw/char
Cornelia Huck :
> On Sun, 16 Apr 2017 20:26:01 +0800
> Zihan Yang wrote:
>
> > According to the second suggestion listed on Dead code Removal
> > of BiteSizedTasks, I modify some *_exit functions to make them
> > return void. Some *_exit and *_exitfn functions
ld involve some other folders like hw/audio.
Signed-off-by: Zihan Yang
---
hw/s390x/event-facility.c | 6 +-
hw/s390x/virtio-ccw.c | 6 +++---
hw/s390x/virtio-ccw.h | 2 +-
3 files changed, 5 insertions(+), 9 deletions(-)
diff --git a/hw/s390x/event-facility.c b/hw/s390x/event-facili
Currently, the console_exit function in sclpconsole-lm.c and
sclpconsole.c does nothing, just remove them. Since there is
a NULL check on the DeviceClass exit callback as suggested by
Frederic Konrad, it should be safe to simply remove them.
Signed-off-by: Zihan Yang
---
hw/char
: Zihan Yang
---
hw/audio/hda-codec.c | 3 +--
hw/audio/intel-hda.c | 3 +--
hw/audio/intel-hda.h | 2 +-
hw/char/sclpconsole-lm.c | 3 +--
hw/char/sclpconsole.c | 3 +--
hw/core/qdev.c| 6 +-
hw/s390x/event
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