Re: [PATCH qemu v6 00/10] Add mask agnostic behavior for rvv instructions

Gentle ping. Regards, eop Chen > ~eopxd 於 2022年6月20日 下午2:50 寫道： > > According to v-spec, mask agnostic behavior can be either kept as > undisturbed or set elements' bits to all 1s. To distinguish the > difference of mask policies, QEMU should be able to simulate the mask

Re: [PATCH qemu v18 00/16] Add tail agnostic behavior for rvv instructions

Rebased to riscv-to-apply.next and submitted v19. Thank you WeiWei, Frank and Alistair for the reviews along the way. Regards, eop Chen > Alistair Francis 於 2022年6月6日 上午9:37 寫道： > > On Fri, May 13, 2022 at 9:55 PM ~eopxd wrote: >> >> According to v-spec, tail agnostic b

Re: [PATCH qemu v15 00/15] Add tail agnostic behavior for rvv instructions

> ~eopxd 於 2022年5月11日 上午12:49 寫道： > > According to v-spec, tail agnostic behavior can be either kept as > undisturbed or set elements' bits to all 1s. To distinguish the > difference of tail policies, QEMU should be able to simulate the tail > agnostic behavior as "set tail elements' bits to al

Re: [PATCH qemu v9 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

> Weiwei Li 於 2022年4月27日 下午7:55 寫道： > > > 在 2022/3/7 下午3:10, ~eopxd 写道: >> From: eopXD >> >> Destination register of unit-stride mask load and store instructions are >> always written with a tail-agnostic policy. >> >> Signed-off-by: eop Chen

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

> Weiwei Li 於 2022年4月27日 上午11:27 寫道： > > > > 在 2022/4/27 上午10:07, eop Chen 写道: >> >> >>> >>> 在 2022/4/27 上午2:20, eop Chen 写道: >>>> >>>>> Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 >>>>>

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

> > 在 2022/4/27 上午2:20, eop Chen 写道: >> >>> Weiwei Li mailto:liwei...@iscas.ac.cn>> 於 2022年4月26日 >>> 下午4:47 寫道： >>> 在 2022/3/17 下午3:26, ~eopxd 写道: >>>> From: Yueh-Ting (eop) Chen >>>> <mailto:eop.c...@sifive.com&g

Re: [PATCH qemu 1/9] target/riscv: rvv: Add mask agnostic for vv instructions

> Weiwei Li 於 2022年4月26日 下午4:47 寫道： > 在 2022/3/17 下午3:26, ~eopxd 写道: >> From: Yueh-Ting (eop) Chen <mailto:eop.c...@sifive.com> >> >> This is the first commit regarding the mask agnostic behavior. >> Added option 'rvv_ma_all_1s' to enable t

Re: [PATCH qemu v7 00/14] Add tail agnostic behavior for rvv instructions

Gentle ping, it is not picked to `riscv-to-apply.next` yet. Thank you. Yueh-Ting (eop) Chen > Alistair Francis 於 2022年3月31日 上午11:18 寫道： > > On Thu, Mar 31, 2022 at 11:24 AM Weiwei Li <mailto:liwei...@iscas.ac.cn>> wrote: >> >> >> 在 2022/3/31 上午8:11, Ali

Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions

r groups involved in this instruction. Therefore in a register group of 4 (LMUL = m2), NFIELD should be no more than 2. The `vlmax` here would be (VLEN * 4 / EEW). In this sense, if the `vl` provided for the vector instruction is within the range 2 * vlmax / 4 <= vl <= 3 * vlmax / 4, the elements in the 4th register (namely reg+3) will all be counted as tail elements. I hope this answers your question. Regards, eop Chen

Re: [PATCH qemu 00/13] Add tail agnostic behavior for rvv instructions

> LMUL=8 (i.e., all bits of the mask register can > be overwritten)." I will wait for you and other's reply on my comment on this. ======= Thanks again for your time. Best, Yueh-Ting (eop) Chen