Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

"Ho-Ren (Jack) Chuang" writes: > On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying wrote: >> >> "Ho-Ren (Jack) Chuang" writes: >> >> > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: >> >> >> >> "Ho-Ren (Jack) Chuang" writes: >> >> >> >> > The memory tiering component in the kernel is functionall

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

On Mon, Mar 4, 2024 at 10:36 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > >> > >> "Ho-Ren (Jack) Chuang" writes: > >> > >> > The memory tiering component in the kernel is functionally useless for > >> > CPUless memory/non-DRA

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

"Ho-Ren (Jack) Chuang" writes: > On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: >> >> "Ho-Ren (Jack) Chuang" writes: >> >> > The memory tiering component in the kernel is functionally useless for >> > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes >> > are lumped

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The memory tiering component in the kernel is functionally useless for > > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes > > are lumped together in the DRAM tier. > > https://lo

Re: [External] Re: [PATCH v1 0/1] Improved Memory Tier Creation for CPUless NUMA Nodes

On Sun, Mar 3, 2024 at 6:47 PM Huang, Ying wrote: > > "Ho-Ren (Jack) Chuang" writes: > > > The memory tiering component in the kernel is functionally useless for > > CPUless memory/non-DRAM devices like CXL1.1 type3 memory because the nodes > > are lumped together in the DRAM tier. > > https://lo