Palmer Dabbelt writes:
> I think, more concretely, the issues here are:
>
> * The only mention of "semihosting" in the RISC-V specification is in the
> commentary, which is not considered a normative part of the
> specification.
Ok, we're starting the process of creating a 'real' RISC-V semiho
On Thu, 30 Jan 2020 at 11:38, Palmer Dabbelt wrote:
> * The semihosting comment doesn't define the semihosting call numbers, just
> the
> sequence to get to a call. That said, we haven't written down the Linux ABI
> either -- though there's a much larger breadth of software out there that
>
On Thu, 30 Jan 2020 10:54:37 GMT (+), Peter Maydell wrote:
On Wed, 29 Jan 2020 at 16:45, Keith Packard wrote:
Peter Maydell writes:
> True but irrelevant. You need to refer to a proper
> risc-v specification for your semihosting.
The RISC-V Foundation defined semihosting as relative to
On Wed, 29 Jan 2020 at 16:45, Keith Packard wrote:
>
> Peter Maydell writes:
>
> > True but irrelevant. You need to refer to a proper
> > risc-v specification for your semihosting.
>
> The RISC-V Foundation defined semihosting as relative to the existing
> ARM specification, so using a link to th
The text you are referencing (the couple italic paragraphs below section
2.8 in the unprivileged ISA) is non-normative and "can be skipped if the
reader is only interested in the specification itself". This convention of
making indented italic text non-normative is described at the bottom of
page 1
Peter Maydell writes:
> True but irrelevant. You need to refer to a proper
> risc-v specification for your semihosting.
The RISC-V Foundation defined semihosting as relative to the existing
ARM specification, so using a link to that is appropriate here.
Here's the current specification of the u
On Tue, 28 Jan 2020 at 23:34, Keith Packard via wrote:
>
> Adapt the arm semihosting support code for RISCV. This implementation
> is based on the standard for RISC-V semihosting as documented in
>
> https://riscv.org/specifications/
>
> Signed-off-by: Keith Packard
>
> ---
> + * ARM Se
Adapt the arm semihosting support code for RISCV. This implementation
is based on the standard for RISC-V semihosting as documented in
https://riscv.org/specifications/
Signed-off-by: Keith Packard
---
v2:
Update PC after exception is handled to follow
change in the ARM
