Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-26 Thread Keith Packard
Richard Henderson writes: > On 10/23/20 2:49 PM, Keith Packard via wrote: >> static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) >> { >> -generate_exception(ctx, RISCV_EXCP_BREAKPOINT); >> +uint32_t pre= opcode_at(&ctx->base, ctx->base.pc_next - 4); >> +uint32_t ebreak =

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-26 Thread Keith Packard
Richard Henderson writes: > This is no different to EXCP_DEBUG, really, which is also internal to qemu but > user-visible in the same way. Just adjust the logging in > riscv_cpu_do_interrupt. I think that's already handled by the early return in riscv_cpu_do_interrupt after handling the RISCV_

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-26 Thread Richard Henderson
On 10/24/20 8:00 AM, Alistair Francis wrote: +#define RISCV_EXCP_SEMIHOST 0x10 >>> >>> I don't see this in the RISC-V spec, it seems to just be reserved, not >>> for semihosting. >> >> Hrm. It's entirely an internal implementation detail in QEMU and matches >> how semihost

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-26 Thread Richard Henderson
On 10/23/20 2:49 PM, Keith Packard via wrote: > static bool trans_ebreak(DisasContext *ctx, arg_ebreak *a) > { > -generate_exception(ctx, RISCV_EXCP_BREAKPOINT); > +uint32_t pre= opcode_at(&ctx->base, ctx->base.pc_next - 4); > +uint32_t ebreak = opcode_at(&ctx->base, ctx->base.pc_

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-24 Thread Alistair Francis
On Fri, Oct 23, 2020 at 10:56 PM Keith Packard wrote: > > Alistair Francis writes: > > Thanks much for taking time to review this patch in detail. I've left > the indicated changes in a new version of my riscv-semihost branch here: > > https://github.com/keith-packard/qemu/tree/riscv-semi

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-23 Thread Keith Packard
Alistair Francis writes: Thanks much for taking time to review this patch in detail. I've left the indicated changes in a new version of my riscv-semihost branch here: https://github.com/keith-packard/qemu/tree/riscv-semihost I'll post a new version once we've wound up discussion on the

Re: [PATCH] riscv: Add semihosting support [v8]

2020-10-23 Thread Alistair Francis
On Fri, Oct 23, 2020 at 2:51 PM Keith Packard via wrote: > > Adapt the arm semihosting support code for RISCV. This implementation > is based on the standard for RISC-V semihosting version 0.2 as > documented in > >https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 > > Signed-off

[PATCH] riscv: Add semihosting support [v8]

2020-10-23 Thread Keith Packard via
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handl

Re: [PATCH] riscv: Add semihosting support [v8]

2020-09-17 Thread no-reply
Patchew URL: https://patchew.org/QEMU/20200917211321.1591257-1-kei...@keithp.com/ Hi, This series seems to have some coding style problems. See output below for more information: N/A. Internal error while reading log file The full log is available at http://patchew.org/logs/20200917211321.

[PATCH] riscv: Add semihosting support [v8]

2020-09-17 Thread Keith Packard via
Adapt the arm semihosting support code for RISCV. This implementation is based on the standard for RISC-V semihosting version 0.2 as documented in https://github.com/riscv/riscv-semihosting-spec/releases/tag/0.2 Signed-off-by: Keith Packard --- v2: Update PC after exception is handl