On Thu, 2022-10-13 at 02:23 -0400, Yang Zhong wrote:
> > > enclave only supported SSE and x87 feature(xfrm=0x3).
> >
> > Is this true? Perhaps I am missing something, but it seems env-
> > > features[FEAT_XSAVE_XCR0_LO] only includes LBR bit, which is bit 15.
>
> We printed the XFRM value
On Wed, Oct 12, 2022 at 09:59:04AM +, Huang, Kai wrote:
> On Wed, 2022-10-12 at 04:26 -0400, Yang Zhong wrote:
> > The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> > FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX, which made SGX
>
On Wed, 2022-10-12 at 04:26 -0400, Yang Zhong wrote:
> The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
> FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX, which made SGX
^
Nit: both ECX and EDX are wrongly set, but not only ECX.
>
The previous patch wrongly replaced FEAT_XSAVE_XCR0_{LO|HI} with
FEAT_XSAVE_XSS_{LO|HI} in CPUID(EAX=12,ECX=1):ECX, which made SGX
enclave only supported SSE and x87 feature(xfrm=0x3).
Fixes: 301e90675c3f ("target/i386: Enable support for XSAVES based features")
Signed-off-by: Yang Zhong
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