Re: [PATCH] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

On Sun, Aug 25, 2024 at 3:34 AM Daniel Henrique Barboza wrote: > > Gitlab issue [1] reports a misleading error when trying to run a 'rv64' > cpu with 'zfinx' and without 'f': > > $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false > qemu-system-riscv64: Zfinx cannot be su

Re: [PATCH] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

On Sun, Aug 25, 2024 at 3:34 AM Daniel Henrique Barboza wrote: > > Gitlab issue [1] reports a misleading error when trying to run a 'rv64' > cpu with 'zfinx' and without 'f': > > $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false > qemu-system-riscv64: Zfinx cannot be su

[PATCH] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule

Gitlab issue [1] reports a misleading error when trying to run a 'rv64' cpu with 'zfinx' and without 'f': $ ./build/qemu-system-riscv64 -nographic -M virt -cpu rv64,zfinx=true,f=false qemu-system-riscv64: Zfinx cannot be supported together with F extension The user explicitly disabled F and the e