On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng
wrote:
>
> Zicsr/Zifencei is not in 'I' since ISA version 20190608,
> thus to fully express the capability of the CPU,
> they should be exposed in isa_string.
>
> Signed-off-by: Hongren (Zenithal) Zheng
Thanks!
Applied to
On Tue, May 24, 2022 at 2:51 AM Hongren (Zenithal) Zheng
wrote:
>
> On Mon, May 23, 2022 at 09:22:15AM +1000, Alistair Francis wrote:
> > On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng
> > wrote:
> > >
> > > Zicsr/Zifencei is not in 'I' since ISA version 20190608,
> > > thus to
On Mon, May 23, 2022 at 09:22:15AM +1000, Alistair Francis wrote:
> On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng
> wrote:
> >
> > Zicsr/Zifencei is not in 'I' since ISA version 20190608,
> > thus to fully express the capability of the CPU,
> > they should be exposed in isa_string.
>
On Wed, May 18, 2022 at 10:50 PM Hongren (Zenithal) Zheng
wrote:
>
> Zicsr/Zifencei is not in 'I' since ISA version 20190608,
> thus to fully express the capability of the CPU,
> they should be exposed in isa_string.
>
> Signed-off-by: Hongren (Zenithal) Zheng
> ---
> target/riscv/cpu.c | 2 ++
This patch could work successfully in qemu. With command "cat
/proc/device-tree/cpus/cpu@0/riscv\,isa", string "zicsr" and "zifencei" could
be found in linux device tree.
Tested-by: Jiatai He
Zicsr/Zifencei is not in 'I' since ISA version 20190608,
thus to fully express the capability of the CPU,
they should be exposed in isa_string.
Signed-off-by: Hongren (Zenithal) Zheng
---
target/riscv/cpu.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target/riscv/cpu.c
