On Fri, 11 Nov 2022 at 18:36, Alex Bennée wrote:
>
> This allows us to correctly model invalid accesses to the interrupt
> controller as well as avoiding the use of current_cpu hacks to find
> the APIC structure. We have to ensure we check for MSI signals first
> which shouldn't arrive from the CP
On 11/12/22 04:25, Alex Bennée wrote:
+switch (attrs.requester_type) {
+case MTRT_MACHINE: /* MEMTX_IOPIC */
Not checking the id?
+case MTRT_PCI: /* PCI signalled MSI */
+break;
+default:
+qemu_log_mask(LOG_GUEST_ERROR, "%s: rejectin
This allows us to correctly model invalid accesses to the interrupt
controller as well as avoiding the use of current_cpu hacks to find
the APIC structure. We have to ensure we check for MSI signals first
which shouldn't arrive from the CPU but are either triggered by PCI or
internal IOAPIC writes.
