PR for the spec fix, in case anyone is interested. Found a couple of other
references to Smcsrind that I also removed.
https://github.com/riscv/riscv-control-transfer-records/pull/29
On Tue, Jun 4, 2024 at 8:41 PM Beeman Strong wrote:
> Ah, good catch. We removed that dependency late. I'll
Ah, good catch. We removed that dependency late. I'll fix it.
On Tue, Jun 4, 2024 at 8:34 PM Jason Chien wrote:
> Thank you for pointing that out. CTR does not use miselect and mireg*.
> There is no dependency on Smcsrind. I believe the spec needs to be
> corrected.
>
> Chapter 1 states that:
Thank you for pointing that out. CTR does not use miselect and mireg*.
There is no dependency on Smcsrind. I believe the spec needs to be
corrected.
Chapter 1 states that:
Smctr depends on the Smcsrind extension, while Ssctr depends on the
Sscsrind extension. Further, both Smctr and Ssctr depe
There is no dependency on Smcsrind, only Sscsrind.
On Tue, Jun 4, 2024 at 12:29 AM Jason Chien wrote:
> Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind
> extension, and both Smctr and Ssctr depend upon implementation of S-mode.
> There should be a dependency check in riscv
Smctr depends on the Smcsrind extension, Ssctr depends on the Sscsrind
extension, and both Smctr and Ssctr depend upon implementation of S-mode.
There should be a dependency check in riscv_cpu_validate_set_extensions().
Rajnesh Kanwal 於 2024/5/30 上午 12:09 寫道:
This series enables Control Transfe
This series enables Control Transfer Records extension support on riscv
platform. This extension is similar to Arch LBR in x86 and BRBE in ARM.
The Extension has been stable and the latest release can be found here [0]
CTR extension depends on couple of other extensions:
1. S[m|s]csrind : The in
